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| IBM Processor for Network Resources Revision 2.5 Databook Preliminary Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America August 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo PowerPC Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com pnr25.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Contents Features .......................................................................................................................... 21 Description ..................................................................................................................... 21 Conventions ................................................................................................................... 22 Standards Compliance .................................................................................................. 23 Environmental Ratings .................................................................................................. 24 Functional Description .................................................................................................. 28 Subsystem Blocks ............................................................................................................................... 29 External Architecture ........................................................................................................................... 30 Internal Architecture ............................................................................................................................ 31 Logical Channel Support ................................................................................................................. 31 Virtual Memory Support ................................................................................................................... 31 Queues ............................................................................................................................................ 32 Scheduling ....................................................................................................................................... 32 System Environment ........................................................................................................................... 34 Data Flows ...................................................................................................................... 36 Transmit Path ....................................................................................................................................... 37 Receive Path ......................................................................................................................................... 39 Input/Output Definitions ................................................................................................ 41 DRAM Memory Bus Interface .............................................................................................................. 41 DRAM Memory Bus Interface .............................................................................................................. 44 NPBUS ................................................................................................................................................... 48 ATM PHY Bus Interface ....................................................................................................................... 51 Data Structures .............................................................................................................. 61 Packet Header ...................................................................................................................................... 61 Transmit Logical Channel Descriptor Data Structures .................................................................... 66 Field Definitions ............................................................................................................................... 74 Receive LCD Data Structure and Modes ........................................................................................ 78 Raw LCD ......................................................................................................................................... 80 Raw Routed LCD ............................................................................................................................. 81 Raw Routed Early Drop LCD ........................................................................................................... 82 Raw Scatter/Cut-Through LCD ........................................................................................................ 83 AAL5 LCD ........................................................................................................................................ 84 AAL5 Routed LCD ........................................................................................................................... 85 AAL5 Cut-Through/Scatter Mode LCD ............................................................................................ 86 Packet LCD ..................................................................................................................................... 87 Packet Routed LCD ......................................................................................................................... 88 Packet Cut-Through Scatter Mode LCD .......................................................................................... 89 Field Definitions ............................................................................................................................... 90 nrm.toc.01 August 14, 2000 Page 3 IBM3206K0424 IBM Processor for Network Resources Preliminary Internal Organization: Entity Descriptions ...................................................................93 Note on Set/Clear Type Registers ...................................................................................................93 Control Processor Bus Interface Entities ....................................................................93 The IOP Bus Specific Interface Controller (PCINT) ...........................................................................93 PCI Options Taken ...........................................................................................................................93 PCI Target Response ......................................................................................................................93 PCI Master Response ......................................................................................................................93 PCI Master Retry .............................................................................................................................94 PCINT Config Word 0 ......................................................................................................................94 PCINT Config Word 1 ......................................................................................................................95 PCINT Config Word 2 ......................................................................................................................97 PCINT Config Word 3 ......................................................................................................................98 PCINT Base Address 1 (I/O for Register) ........................................................................................99 PCINT Base Address 2 (Mem for Register) ...................................................................................101 PCINT Base Addresses 3-6 (Memory) ..........................................................................................103 PCINT CardBus CIS Pointer ..........................................................................................................105 PCINT Subsystem ID/Vendor ID ....................................................................................................106 PCINT ROM Base Address ...........................................................................................................107 Capabilities Pointer ........................................................................................................................108 PCINT Config Word 15 ..................................................................................................................109 PCINT Endian Control Register .....................................................................................................110 PCINT Base Address Control Register ..........................................................................................111 PCINT Window Offsets for Base Addresses 3-6 ...........................................................................113 PCINT Count Timeout Register .....................................................................................................114 PCINT 64-bit Control Register .......................................................................................................116 PCINT 64-bit Enable Register ........................................................................................................118 PCINT Perf Counters Control Register ..........................................................................................119 PCINT Perf Counter 1 ....................................................................................................................121 PCINT Perf Counter 2 ....................................................................................................................122 PCI Master Options Control ...........................................................................................................123 Power Management Program Control ...........................................................................................125 Message Signaled Interrupts-Word 1 ............................................................................................127 Message Signaled Interrupts-Word 2 ............................................................................................128 Message Signaled Interrupts-Word 3 ............................................................................................129 Message Signaled Interrupts-Word 4 ............................................................................................130 Power Management Interface-Word 1 ...........................................................................................131 Power Management Interface-Word 2 ...........................................................................................132 Vital Product Data Interface-Word 1 ..............................................................................................133 Vital Product Data Interface-Word 2 ..............................................................................................134 Interrupt and Status/Control (INTST) ................................................................................................135 INTST Interrupt 1 Prioritized Status ...............................................................................................135 INTST Interrupt 2 Prioritized Status ...............................................................................................136 INTST Control Register ..................................................................................................................137 INTST Interrupt Source ..................................................................................................................139 INTST Enable for Interrupt 1 (MINTA) ...........................................................................................140 INTST Enable for Interrupt 2 (MINT2) ............................................................................................141 INTST Interrupt Source without Enables .......................................................................................141 INTST CPB Status .........................................................................................................................142 INTST CPB Status Enable .............................................................................................................144 INTST IBM3206K0424 Halt Enable ...............................................................................................144 nrm.toc.01 August 14, 2000 Page 4 IBM3206K0424 Preliminary IBM Processor for Network Resources INTST CPB Capture Enable .......................................................................................................... 144 INTST CPB Captured Address ...................................................................................................... 145 INTST General Purpose Timer Pre-scaler .................................................................................... 145 INTST General Purpose Timer Compare ...................................................................................... 146 INTST General Purpose Timer Counter ........................................................................................ 146 INTST General Purpose Timer Status ........................................................................................... 147 INTST General Purpose Timer Mode Control ............................................................................... 148 INTST Enable for PCORE Normal Interrupt .................................................................................. 149 INTST Enable for PCORE Critical Interrupt ................................................................................... 149 INTST Debug States Control ......................................................................................................... 150 INTST Delayed Interrupts DMA System Address 1 ....................................................................... 152 INTST Delayed Interrupts DMA System Address 2 ....................................................................... 152 Current PCI Master Address Counter for Debug ........................................................................... 152 External Entity States Read ........................................................................................................... 153 DMA QUEUES (DMAQS) .................................................................................................................... 154 DMA Descriptors ........................................................................................................................... 154 DMA Types and Options ............................................................................................................... 155 Descriptor Based DMAs ................................................................................................................ 156 Register Based DMAs ................................................................................................................... 156 Polling, Interrupts, or Events ......................................................................................................... 156 Error Detection and Recovery ....................................................................................................... 156 DMA/Queue Scheduling Options ................................................................................................... 156 Address Size ................................................................................................................................. 156 Data Width ..................................................................................................................................... 157 Initialization of DMAQS .................................................................................................................. 157 DMAQS Lower Bound Registers ................................................................................................... 158 DMAQS Upper Bound Registers ................................................................................................... 159 DMAQS Head Pointer Registers ................................................................................................... 160 DMAQS Tail Pointer Registers ...................................................................................................... 160 DMAQS Length Registers ............................................................................................................. 161 DMAQS Threshold Registers ........................................................................................................ 161 DMAQS Interrupt Status ................................................................................................................ 162 DMAQS Interrupt Enable ............................................................................................................... 164 DMAQS Control Register .............................................................................................................. 164 DMAQS Enqueue DMA Descriptor Primitive ................................................................................. 166 DMAQS Source Address Register ................................................................................................ 166 DMAQS Destination Address Register .......................................................................................... 167 DMAQS Buffer Address Register .................................................................................................. 167 DMAQS Transfer Count and Flag Register ................................................................................... 168 DMAQS System Descriptor Address ............................................................................................. 171 DMAQS Checksum Register ......................................................................................................... 171 DMAQS Local Descriptor Range Registers ................................................................................... 173 DMAQS Event Queue Number Register ....................................................................................... 173 DMAQS DMA Request Size Register ............................................................................................ 174 DMAQS Enq FIFO Register .......................................................................................................... 174 General Purpose DMA (GPDMA) ...................................................................................................... 175 GPDMA Interrupt Status ................................................................................................................ 175 GPDMA Interrupt Enable ............................................................................................................... 176 GPDMA Control Register .............................................................................................................. 177 GPDMA Source Address Register ................................................................................................ 178 GPDMA Destination Address Register .......................................................................................... 179 nrm.toc.01 August 14, 2000 Page 5 IBM3206K0424 IBM Processor for Network Resources Preliminary GPDMA Transfer Count and Flag Register ...................................................................................179 GPDMA DMA Max Burst Time .......................................................................................................181 GPDMA Maximum Memory Transfer Count ..................................................................................181 GPDMA Checksum Register .........................................................................................................181 GPDMA Read DMA Byte Count ....................................................................................................182 GPDMA Write DMA Byte Count .....................................................................................................182 GPDMA Array Read Address ........................................................................................................182 GPDMA Array Write Address .........................................................................................................183 GPDMA Array ................................................................................................................................183 Memory Controlling Entities ........................................................................................184 The DRAM Controllers (COMET/PAKIT) ...........................................................................................184 Memory Reset Sequence ..............................................................................................................185 COMET/PAKIT Control Register ....................................................................................................186 COMET/PAKIT Status Register .....................................................................................................189 COMET/PAKIT Interrupt Enable Register ......................................................................................190 COMET/PAKIT Lock Enable Register ...........................................................................................190 COMET/PAKIT Memory Error Address Register ...........................................................................191 COMET/PAKIT SDRAM Command and Status Register ..............................................................192 COMET/PAKIT DRAM Refresh Rate Register ..............................................................................194 COMET/PAKIT Syndrome Register ...............................................................................................195 COMET/PAKIT Checkbit Inversion Register ..................................................................................197 COMET/PAKIT Memory Controller Write Enable Register ............................................................197 COMET/PAKIT Memory Configuration Error Sense Register ........................................................198 ATM Virtual Memory Logic (VIMEM) .................................................................................................200 VIMEM Virtual Memory Base Address ...........................................................................................200 On-Chip Memory Base Address ....................................................................................................201 VIMEM Control Memory Base Address .........................................................................................201 VIMEM Packet Memory Base Address ..........................................................................................202 VIMEM Virtual Memory Total Bytes ...............................................................................................203 VIMEM Virtual/Real Memory Buffer Size .......................................................................................204 VIMEM Packet Memory Offset .......................................................................................................205 VIMEM Maximum Buffer Size ........................................................................................................205 VIMEM Access Control Register ....................................................................................................206 VIMEM Access Status Register .....................................................................................................207 VIMEM Access Status Interrupt Enable Register ..........................................................................209 VIMEM Memory Lock Enable Register ..........................................................................................209 VIMEM State Machine Current State .............................................................................................210 VIMEM Last Processor Read Real Address ..................................................................................211 VIMEM Virtual Buffer Segment Size Register ................................................................................212 VIMEM Buffer Map Base Address .................................................................................................214 VIMEM Real Buffer Base Addresses .............................................................................................215 ATM Packet/Control Memory Arbitration Logic (ARBIT) ................................................................217 ARBIT Control Priority Resolution Register High ...........................................................................217 ARBIT Control Priority Resolution Register Low ............................................................................218 ARBIT Control Error Mask Register ...............................................................................................219 ARBIT Control Error Source Register ............................................................................................220 ARBIT Control Winner Register .....................................................................................................221 ARBIT Control Address Register A ................................................................................................222 ARBIT Control Address Register B ................................................................................................222 ARBIT Control Length Register .....................................................................................................223 nrm.toc.01 August 14, 2000 Page 6 IBM3206K0424 Preliminary IBM Processor for Network Resources ARBIT Control Lock Entity Enable Register .................................................................................. 224 ARBIT Control Config Register ...................................................................................................... 225 ARBIT Packet Priority Resolution Register High ........................................................................... 225 ARBIT Packet Priority Resolution Register Low ............................................................................ 227 ARBIT Packet Entity Error Mask Register ..................................................................................... 228 ARBIT Packet Error Source Register ............................................................................................ 229 ARBIT Packet Winner Register ..................................................................................................... 230 ARBIT Packet Address Register A ................................................................................................ 231 ARBIT Packet Address Register B ................................................................................................ 231 ARBIT Packet Length Register ...................................................................................................... 232 ARBIT Packet Lock Entity Enable Register ................................................................................... 233 ARBIT Packet Config Register ...................................................................................................... 234 ARBIT Performance Counter Control ............................................................................................ 235 Arbit Memory Performance Counter .............................................................................................. 237 The Bus DRAM Cache Controller (BCACH) ..................................................................................... 238 BCACH Control Register ............................................................................................................... 239 BCACH Status Register ................................................................................................................ 241 BCACH Interrupt Enable Register ................................................................................................. 242 BCACH High Priority Timer Value ................................................................................................. 242 BCACH Line Tag Registers ........................................................................................................... 243 BCACH Line Valid Bytes Register ................................................................................................. 244 BCACH Line Status Register ......................................................................................................... 245 BCACH Cache Line Array ............................................................................................................. 246 Buffer Pool Management (POOLS) ................................................................................................... 247 Basic Operation in Real Memory Mode ......................................................................................... 247 Basic Operation in Virtual Memory Mode ...................................................................................... 247 Resource Controls ......................................................................................................................... 247 Virtual Memory Overview .............................................................................................................. 248 POOLS Get Pointer Primitive ........................................................................................................ 252 POOLS Free Pointer Primitive ....................................................................................................... 253 POOLS Common Pools Count Registers ...................................................................................... 253 POOLS Client Thresholds Array .................................................................................................... 254 POOLS User Threshold and Client Active Packet Count Array .................................................... 255 POOLS Pointer Queues DRAM Head Pointer Offset Address Register ....................................... 256 POOLS Pointer Queues DRAM Tail Pointer Offset Address Register .......................................... 257 POOLS Pointer Queues DRAM Lower Bound Address Register .................................................. 258 POOLS Pointer Queues DRAM Upper Bound Register ................................................................ 259 POOLS Pointer Queues Length Registers .................................................................................... 261 POOLS Interrupt Enable Register ................................................................................................. 261 POOLS Event Enables .................................................................................................................. 262 POOLS Event Hysteresis Register ................................................................................................ 262 POOLS Event Data Register ......................................................................................................... 263 POOLS Status Register ................................................................................................................. 265 POOLS Control Register ............................................................................................................... 267 POOLS Buffer Threshold Registers 0-4 ........................................................................................ 269 POOLS Index Threshold Registers 0-4 ......................................................................................... 269 POOLS Last Primitive Trap Register ............................................................................................. 270 POOLS Last Buffer Map Read on Free Register .......................................................................... 270 POOLS Error Lock Enable Register .............................................................................................. 270 POOLS Packet and Control Memory Access Threshold ............................................................... 271 POOLS Buffer Map Group ............................................................................................................. 271 nrm.toc.01 August 14, 2000 Page 7 IBM3206K0424 IBM Processor for Network Resources Preliminary Transmit Data Path Entities .........................................................................................273 Transmit Buffer (CSKED) ...................................................................................................................273 Scheduling Overview .....................................................................................................................273 Operational Description .................................................................................................................274 LCD Initialization ............................................................................................................................274 A Scheduling Example ...................................................................................................................274 CSKED Initialization .......................................................................................................................275 Packet Initialization ........................................................................................................................276 Scheduling Options ........................................................................................................................276 ABR Scheduling .............................................................................................................................276 Frame Scheduling ..........................................................................................................................276 Path Scheduling .............................................................................................................................277 Primitives .......................................................................................................................................277 Enqueue .........................................................................................................................................277 Close Connection ...........................................................................................................................277 Start/Stop Timer .............................................................................................................................278 Transmit Enqueue Primitive ...........................................................................................................278 Resume Transmission Primitive ....................................................................................................278 Start/Stop Timer Primitive ..............................................................................................................279 Close Connection Primitive ............................................................................................................279 Timeslot Prescaler Register ...........................................................................................................280 Current Timeslot Counter ...............................................................................................................280 CSKED Control Register ................................................................................................................281 Transmit Segmentation Throttle Register ......................................................................................283 Transmit Segmentation Throttle Counter .......................................................................................284 MPEG Conversion Register ...........................................................................................................284 ABR Timer Prescaler Register .......................................................................................................285 RM Cell Timer ................................................................................................................................285 CSKED LCD Update Data Registers .............................................................................................286 CSKED LCD Update Mask Registers ............................................................................................286 CSKED LCD Update Operation Registers .....................................................................................287 Drop Access Control Register ........................................................................................................288 Performance Registers ......................................................................................................................289 High Priority Bandwidth Limit Register ...........................................................................................289 Medium Priority Bandwidth Limit Register .....................................................................................290 Low Priority Bandwidth Limit Register ...........................................................................................290 High Priority Cells Transmitted Counter .........................................................................................291 Medium Priority Cells Transmitted Counter ...................................................................................291 Low Priority Cells Transmitted Counter .........................................................................................292 Bytes Queued Counters .................................................................................................................293 Debugging Register Access ..............................................................................................................294 Fast Serviced Counters .................................................................................................................294 Slow Serviced Counters .................................................................................................................294 Timer Serviced Counters ...............................................................................................................295 CSKED Status Register .................................................................................................................296 CSKED Interrupt Enable Register ..................................................................................................297 CSKED Timing Data Array Pointer ................................................................................................297 CSKED Timing Data Array Data ....................................................................................................298 CSKED Time Wheel Array Pointer ................................................................................................298 CSKED Time Wheel Array Data ....................................................................................................299 CSKED LCD Cache Array Pointer .................................................................................................299 Page 8 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources CSKED LCD Cache Array Data .................................................................................................... 300 CSKED Congestion Control Register ............................................................................................ 300 State Machine Variables ................................................................................................................ 301 ATM Transmit Buffer Segmentation (SEGBF) ................................................................................. 302 SEGBF Software LCD Enqueue .................................................................................................... 305 SEGBF Control Register ............................................................................................................... 306 SEGBF Status Register ................................................................................................................. 308 SEGBF Invalid LCD Register ........................................................................................................ 309 SEGBF Software LCD Complete ................................................................................................... 310 SEGBF Interrupt Enable Register ................................................................................................. 311 SEGBF Programmable Counters .................................................................................................. 311 SEGBF Transmit LCD Size ........................................................................................................... 312 SEGBF Cell Queue Status ............................................................................................................ 313 SEGBF Processor 1 Control/Status .............................................................................................. 314 SEGBF Processor 2 Control/Status .............................................................................................. 315 SEGBF Programmable Counter Source Specification .................................................................. 316 SEGBF Cell Staging Array Pointer ................................................................................................ 317 SEGBF Cell Staging Array Data .................................................................................................... 318 SEGBF Instruction SRAM Pointer ................................................................................................. 318 SEGBF Instruction SRAM Data ..................................................................................................... 319 MPEG-2 PCR Increment Register ................................................................................................. 319 Receive Data Path Entities .......................................................................................... 320 Cell/Packet Re-assembly (REASM) .................................................................................................. 320 Miscellaneous Reassembly Functions .......................................................................................... 322 ATM OAM Cell Processing ............................................................................................................ 322 TCP/IP Receive Checksum Verification ........................................................................................ 323 Scatter/Cut Through Receive Processing ..................................................................................... 324 REASM Logical Channel Descriptor Base Register ...................................................................... 328 REASM Mode Register ................................................................................................................. 329 REASM Reassembly Modes Register ........................................................................................... 330 REASM Status Register ................................................................................................................ 331 REASM Interrupt Enable Register ................................................................................................. 332 REASM DEBUG State Selector Register ...................................................................................... 332 RXBUF Functional Description ...................................................................................................... 333 RXBUF Cell Data Buffer Address .................................................................................................. 333 RXBUF Cell Data Buffer Read/Write Port ..................................................................................... 334 RXBUF Cell Info Buffer Address ................................................................................................... 334 RXBUF Cell Info Buffer Read/Write Port ....................................................................................... 334 RXBUF Receive Buffer Threshold ................................................................................................. 335 RXXLT Functional Description ...................................................................................................... 336 RXXLT Register Array Address Port ............................................................................................. 340 RXXLT Register Array Read/Write Port ........................................................................................ 340 RXXLT Processor State Selector .................................................................................................. 341 RXXLT Processor State Read/Write Port ...................................................................................... 341 RXXLT Instruction Array Address Port .......................................................................................... 342 RXXLT Instruction Array Read/Write Port ..................................................................................... 342 RXXLT Last LCD Index Register ................................................................................................... 343 RXCRC Functional Description ..................................................................................................... 344 RXCRC Instruction Array Address Port ......................................................................................... 344 RXCRC Instruction Array Read/Write Port .................................................................................... 345 nrm.toc.01 August 14, 2000 Page 9 IBM3206K0424 IBM Processor for Network Resources Preliminary RXCRC Processor State Selector .................................................................................................345 RXCRC Processor State Read/Write Port .....................................................................................346 RXCRC Last LCD Index Register ..................................................................................................346 RXCRC Checksum Protocol Registers ..........................................................................................346 RXAAL Functional Description .......................................................................................................347 RXAAL Instruction Array Address Port ..........................................................................................348 RXAAL Instruction Array Read/Write Port .....................................................................................348 RXAAL Processor State Selector ..................................................................................................349 RXAAL Processor State Read/Write Port ......................................................................................349 RXAAL Last LCD Index Register ...................................................................................................350 RXAAL Transmit Queue Length Compression Configuration ........................................................351 RXAAL Packet Header Configuration ............................................................................................352 RXAAL Error Count Register .........................................................................................................353 RXAAL Dropped Count Register ...................................................................................................354 RXAAL Maximum SDU Length Register ........................................................................................354 RXAAL OAM LCD Information Register ........................................................................................354 RXALL - Scatter/Cut Through Info Registers .................................................................................355 RXALL - Scatter/Cut Through Flag Registers ................................................................................358 RXLCD Functional Description ......................................................................................................359 RXLCD Cache Data Array Address Port .......................................................................................359 RXLCD Cache Data Array Read/Write Port ...................................................................................360 RXLCD Cache Line Info Registers ................................................................................................360 RXLCD Mode Register ..................................................................................................................361 RXRTO Functional Description ......................................................................................................362 Reassembly Timeout (RTO) Processing ....................................................................................362 RXRTO LCD Update Data Registers .............................................................................................363 RXRTO LCD Update Mask Registers ............................................................................................363 RXRTO LCD Update Op Registers ................................................................................................364 RXRTO RTO LCD Table Bound Registers ....................................................................................364 RXRTO Reassembly Timeout Value Register ...............................................................................365 RXRTO Reassembly Timeout Pre-Scaler Register .......................................................................365 Receive Queues (RXQUE) .................................................................................................................366 Functional Description ...................................................................................................................366 Receive Queue Interface ...............................................................................................................366 AAL5 Packet Events ......................................................................................................................370 Cell Events .....................................................................................................................................371 LC Events ......................................................................................................................................372 ABR Events ....................................................................................................................................372 RXQUE Structure ...........................................................................................................................377 RXQUE Initialization ......................................................................................................................377 RXQUE Event Routing ...................................................................................................................378 RXQUE Normal Operation .............................................................................................................379 RXQUE Queue Full Operation .......................................................................................................379 RXQUE Event Timestamping ........................................................................................................380 RXQUE System Receive Queues ..................................................................................................380 RXQUE Lower Bound Registers ....................................................................................................382 RXQUE Properties Registers .........................................................................................................383 RXQUE Head Pointer Registers ....................................................................................................386 RXQUE Tail Pointer Registers .......................................................................................................387 RXQUE Length Registers ..............................................................................................................388 RXQUE Threshold Registers .........................................................................................................389 Page 10 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXQUE Dequeue Registers .......................................................................................................... 390 RXQUE Enqueue Registers .......................................................................................................... 391 RXQUE Next Lower Bound Registers ........................................................................................... 392 RXQUE Last Event Dropped Register ........................................................................................... 393 RXQUE Timestamp Register ......................................................................................................... 393 RXQUE Timestamp Pre-Scaler Register ....................................................................................... 393 RXQUE Timestamp Shift Register ................................................................................................ 394 RXQUE Event Routing Registers .................................................................................................. 394 RXQUE Event Latency Timer Register ......................................................................................... 395 RXQUE Queues Status Register ................................................................................................... 396 RXQUE Interrupt Enable Registers ............................................................................................... 397 RXQUE Status and Enabled Status Registers .............................................................................. 398 RXQUE Control Register ............................................................................................................... 400 Debugging Register Access .......................................................................................................... 401 RXQUE RXQ State Machine Variable Register ............................................................................ 401 RXQUE RXQ ENQ State Machine Variable Register .................................................................... 401 RXQUE Enq FIFO Head Ptr Register ............................................................................................ 402 RXQUE Enq FIFO Tail Ptr Register .............................................................................................. 402 RXQUE Enq FIFO Array ................................................................................................................ 402 PHY Level Interfaces ................................................................................................... 403 The PHY Interface (LINKC) ................................................................................................................ 403 Functional Description ................................................................................................................... 403 Multi-Drop ...................................................................................................................................... 403 POS-PHY ...................................................................................................................................... 403 Moving Cells To and From the IBM3206K0424 ............................................................................. 404 LINKC Global Control Register ...................................................................................................... 404 LINKC Configuration 0 Transmit & Receive Control Register ....................................................... 407 LINKC Configuration 1 Transmit & Receive Control Register ....................................................... 410 LINKC Configuration 2 Transmit & Receive Control Register ....................................................... 413 LINKC Configuration 3 Transmit & Receive Control Register ....................................................... 416 LINKC Map Transmit Configurations to Port Addresses ............................................................... 419 LINKC Map Receive Configurations to Port Addresses ................................................................ 420 LINKC Transmitted HEC Control Byte ........................................................................................... 421 LINKC Interrupt/Status Register .................................................................................................... 422 LINKC Interrupt Enable Register ................................................................................................... 424 LINKC Prioritized Interrupts ........................................................................................................... 424 LINKC Transmit State Machine Register ....................................................................................... 425 LINKC Receive State Machine Register ........................................................................................ 425 LINKC LAN Address Register ....................................................................................................... 426 LINKC Canonical LAN Address Register ...................................................................................... 426 LINKC Passed TX Data Register .................................................................................................. 427 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data ........................................................................................................................ 428 NPBUS Control Register ............................................................................................................... 428 NPBUS Status Register ................................................................................................................. 431 NPBUS Interrupt Enable Register ................................................................................................. 432 NPBUS EPROM Address/Command Register .............................................................................. 433 NPBUS EPROM Data Register ..................................................................................................... 434 PHY 1 Registers ............................................................................................................................ 434 PHY 2 Registers ............................................................................................................................ 434 nrm.toc.01 August 14, 2000 Page 11 IBM3206K0424 IBM Processor for Network Resources Preliminary Hardware Protocol Assist Entities ..............................................................................435 On-chip Checksum and DRAM Test Support (CHKSM) ..................................................................435 Functional Description ...................................................................................................................435 CHKSM Base Address Register ....................................................................................................435 CHKSM Read/Write Count Register ..............................................................................................436 CHKSM TCP/IP Checksum Data Register ....................................................................................437 CHKSM Ripple Base Register .......................................................................................................437 CHKSM Ripple Limit Register ........................................................................................................438 CHKSM Interrupt Enable Register .................................................................................................438 CHKSM Status Register ................................................................................................................439 CHKSM Control Register ...............................................................................................................440 Debugging Register Access ...........................................................................................................441 CHKSM Internal State ....................................................................................................................441 Software Use of CHKSM ...............................................................................................................442 Running a TCP/IP Checksum in Packet/Control Memory ..............................................................443 Processor Core (PCORE) ..................................................................................................................444 DCR Interface ................................................................................................................................444 Interrupt Controller .........................................................................................................................444 Bridge-Address Translation ...........................................................................................................444 OCM SRAM ...................................................................................................................................444 Control Memory .............................................................................................................................444 Packet Memory ..............................................................................................................................444 PCI Master Interface-External ........................................................................................................444 Processor Register Space .............................................................................................................444 Address Translation Examples ......................................................................................................445 Cobra Structure ..............................................................................................................................445 Cobra Core "Glossy" Description ...................................................................................................446 Features .........................................................................................................................................446 Interfaces .......................................................................................................................................448 Performance ..................................................................................................................................449 Instruction Set ................................................................................................................................449 Cobra Instruction Overview ............................................................................................................449 Cobra Facilities Overview ..............................................................................................................450 Cobra Specific Register Definitions ...............................................................................................455 Hardware Implementation Detail 0 Register (HID0) .......................................................................456 Machine State Register (MSR) ......................................................................................................458 Exception Status Register (ESR) ...................................................................................................460 Machine Check Enable Register (MCHK) ......................................................................................461 PCORE Register Definitions ..........................................................................................................463 PCORE Control Register ...............................................................................................................463 PCORE Reset Control Register .....................................................................................................466 PCORE Status Register .................................................................................................................467 PCORE User Status Register ........................................................................................................468 PCORE Cobra Core External Status Register ...............................................................................469 PCORE Cobra Core External Machine Check Status Register .....................................................471 PCORE JTAG Debug Control Register .........................................................................................473 PCORE JTAG Debug Status Register ...........................................................................................474 PCORE JTAG Instruction Stuff Buffer ...........................................................................................475 PCORE JTAG Debug Data Register .............................................................................................476 PCORE Cobra Core Boot Address ................................................................................................477 PCORE Cobra Core Access Priority Control Register ...................................................................478 Page 12 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PCORE Transaction Dead Man Timer Value Registers ................................................................ 480 PCORE High Priority Access Timer Value Registers .................................................................... 481 PCORE Transaction Dead Man Timer Register ............................................................................ 481 PCORE IBM3206K0424 Shadow Status Register ........................................................................ 481 PCORE IBM3206K0424 Packet Last Write with Error Address .................................................... 482 PCORE IBM3206K0424 RXQUE Master Status Register ............................................................. 482 PCORE IBM3206K0424 RXQUE Enabled Status Register 1 ....................................................... 482 PCORE IBM3206K0424 RXQUE Enabled Status Register 2 ....................................................... 483 PCORE IBM3206K0424 RXQUE Upper Queues Status Register ................................................ 483 PCORE IBM3206K0424 RXQUE Lower Queues Status Register ................................................ 483 PCORE DMAQS Master Status Register ...................................................................................... 484 PCORE DMAQS Enabled Status Register .................................................................................... 484 PCORE RXQUE Queue Length Registers .................................................................................... 484 PCORE DMAQS Queue Length Registers .................................................................................... 485 PCORE Interrupt Enable Register ................................................................................................. 485 PCORE User Interrupt Enable ....................................................................................................... 485 PCORE Cobra Core Interrupt Enable Register ............................................................................. 486 PCORE Cobra Core External Machine Check Enable Register .................................................... 486 PCORE Error Lock Enable Register .............................................................................................. 486 PCORE User Error Lock Enable Register ..................................................................................... 487 PCORE RXQUE Event Interface Enqueue Register ..................................................................... 487 PCORE DMAQS DMA Enqueue Register ..................................................................................... 487 PCORE RXQUE Event Interface Deque Register ......................................................................... 488 PCORE Cobra SPR Read Data Access Register ......................................................................... 488 PCORE Cobra SPR Write Data Access Register .......................................................................... 488 PCORE Cobra SPR Access Address Register ............................................................................. 489 PCORE Address Translation Offset Address Facilities ................................................................. 490 PCORE PCI 64 Bit Address Translation Facilities ......................................................................... 491 PCORE PCI Master Target Tag Controls ...................................................................................... 492 PCORE Last Packet Address Register ......................................................................................... 494 PCORE Last Control Address Register ......................................................................................... 494 PCORE Last PCI Lower Address Register .................................................................................... 494 PCORE Last Register Address Register ....................................................................................... 495 PCORE SRAM Base Address ....................................................................................................... 495 PCORE Read Data Transfer Buffers ............................................................................................. 496 PCORE Write Data Transfer Buffers ............................................................................................. 496 PCORE Polling Register ................................................................................................................ 497 PCORE Integer Input Rate Conversion Register .......................................................................... 497 PCORE ABR Output Rate Register ............................................................................................... 498 PCORE Debug States Control ...................................................................................................... 498 PCORE Debug States Config ........................................................................................................ 499 PowerPC On-Chip Memory (PPOCM) Entity .................................................................................... 500 DMA Controller .............................................................................................................................. 500 PPOCM Control Register .............................................................................................................. 500 PPOCM Status Register ................................................................................................................ 501 PPOCM Interrupt Enable Register ................................................................................................ 502 PPOCM DMA Off-Chip Effective Address Register ....................................................................... 502 PPOCM DMA On-Chip Effective Address Register ....................................................................... 503 PPOCM DMA Length Register ...................................................................................................... 504 PPOCM DMA Timeout Timer Register .......................................................................................... 504 nrm.toc.01 August 14, 2000 Page 13 IBM3206K0424 IBM Processor for Network Resources Preliminary RS-232 Interface Logic (RS-232) .......................................................................................................505 RS-232 Interface Logic Registers ..................................................................................................505 RS-232 Control Register ................................................................................................................505 RS-232 Status Register .................................................................................................................506 RS-232 Interrupt Enable Register ..................................................................................................507 RS-232 Transmit Buffer .................................................................................................................507 RS-232 Receive Buffer ..................................................................................................................508 RS-232 Baud Rate Register ..........................................................................................................508 RS-232 CTS/DSR Glitch Timer Rate .............................................................................................509 RS-232 Reset Register ..................................................................................................................509 RS-232 Error Forcing Register ......................................................................................................510 Reset and Power-on Logic (CRSET) .................................................................................................511 Reset and Power-on Logic Registers ............................................................................................511 Reset Status Register ....................................................................................................................511 Software Reset Enable Register ....................................................................................................512 Software Reset Register ................................................................................................................512 Memory Type Register ...................................................................................................................513 CRSET PLL Range Debug ............................................................................................................514 CRSET Control Register ................................................................................................................515 Clock Control Register (Nibble Aligned) ........................................................................................516 CBIST PRPG Results ....................................................................................................................518 CBIST MISR Results .....................................................................................................................518 CBIST BIST Rate ...........................................................................................................................518 CBIST PRPG Expected Signature .................................................................................................518 CBIST MISR Expected Signature ..................................................................................................519 CBIST CYCT Load Value ..............................................................................................................519 JTAG Interface Logic (CJTAG) ..........................................................................................................520 Scanning ........................................................................................................................................520 Instruction Format ..........................................................................................................................521 Instructions .....................................................................................................................................522 IDCODE .........................................................................................................................................522 SAMPLE/PRELOAD ......................................................................................................................522 EXTEST .........................................................................................................................................522 BYPASS .........................................................................................................................................522 RUNBIST .......................................................................................................................................523 BIST_RESULTS ............................................................................................................................523 WALNUT_MODE ...........................................................................................................................523 COMPLIANT_MODE .....................................................................................................................523 STOP .............................................................................................................................................523 SCAN .............................................................................................................................................523 SCAN_IN .......................................................................................................................................524 SCAN_OUT ...................................................................................................................................524 Private_RW1 ..................................................................................................................................524 Private_RW2 ..................................................................................................................................524 Private_RW3 ..................................................................................................................................524 Page 14 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Sonet Framer Core (FRAMR Chiplet Address Mapping) .......................................... 525 GPPINT Architecture .......................................................................................................................... 525 Overview ........................................................................................................................................ 525 Reset Register ............................................................................................................................... 525 Interrupt Registers ......................................................................................................................... 525 Handshaking Error Registers ........................................................................................................ 526 Clock Monitor Status Registers ..................................................................................................... 526 Local Gppint Configuration Registers ............................................................................................ 526 Global Static Configuration Registers ............................................................................................ 526 Status Registers ............................................................................................................................ 526 GPPINT Register Description ............................................................................................................ 528 Chiplet Reset Register (RESGP) ................................................................................................... 528 Chiplet Interrupt and Mask Registers (IRQGP1 (IRMGP1)) .......................................................... 529 Handshaking Error Indication and Mask Registers (HShake1) ..................................................... 530 Clock Monitor Status and Mask Registers (ClkStat1 (ClkMask1)) ................................................ 531 Clock Monitor Test Period Register (CMonGP1) ........................................................................... 532 Watchdog Timer Period Register (WDTGP1) ................................................................................ 532 GPPINT Local Configuration Registers (ConfGP1) ....................................................................... 533 Vital Macro Data Register (VPD) ................................................................................................... 534 Static Configuration Register (GATMCS) ...................................................................................... 534 GCasc ............................................................................................................................................ 535 GLoopTx ........................................................................................................................................ 535 GLoopRx ....................................................................................................................................... 536 GExtRes ........................................................................................................................................ 536 OFPTXGP ..................................................................................................................................... 537 OFPRXGP1 ................................................................................................................................... 537 OFPRXGP2 ................................................................................................................................... 538 PIMRConf2 .................................................................................................................................... 538 SIMStat .......................................................................................................................................... 539 GPPHandler Architecture .................................................................................................................. 540 Overview ........................................................................................................................................ 540 Counter Registers .......................................................................................................................... 540 Reset Registers ............................................................................................................................. 540 Command Registers ...................................................................................................................... 540 Event Latch Registers ................................................................................................................... 541 Interrupt Registers ......................................................................................................................... 541 Configuration Registers ................................................................................................................. 541 Register Types .............................................................................................................................. 541 ATM Cell Handler Architecture : Transmit Direction ...................................................................... 542 ACH Tx Register Description ............................................................................................................ 543 Counter Registers .......................................................................................................................... 543 ROFmid ......................................................................................................................................... 543 ROFhi ............................................................................................................................................ 543 ACBC ............................................................................................................................................. 544 IUC ................................................................................................................................................ 544 ACBE ............................................................................................................................................. 545 ACBETh11 ..................................................................................................................................... 546 CntEn1 ........................................................................................................................................... 546 Reset Register (RESET) ............................................................................................................... 547 Status Registers ............................................................................................................................ 548 STAT1 ........................................................................................................................................... 548 nrm.toc.01 August 14, 2000 Page 15 IBM3206K0424 IBM Processor for Network Resources Preliminary IUCSTAT1 ......................................................................................................................................549 Interrupt Request and Mask Registers ..........................................................................................549 MainIRQ .........................................................................................................................................549 M_MainIRQ ....................................................................................................................................550 CntrIRQ1 ........................................................................................................................................551 M_CntrIRQ1 ...................................................................................................................................552 Configuration Registers .................................................................................................................553 CELLTENABLE ..............................................................................................................................553 ACBTXTHRPAE ............................................................................................................................554 SDBTXTHRPAF .............................................................................................................................554 HEADERBYTE1 .............................................................................................................................555 HEADERBYTE2 .............................................................................................................................555 HEADERBYTE3 .............................................................................................................................556 HEADERBYTE4 .............................................................................................................................556 HEADERBYTE5 .............................................................................................................................557 PAYLOADBYTE .............................................................................................................................557 HECENCTRL .................................................................................................................................558 HECOFFSET .................................................................................................................................559 HECMASKAND ..............................................................................................................................559 HECMASKOR ................................................................................................................................560 ATM Cell Handler Architecture: Receive Direction .........................................................................561 ACH_Rx Register Description ........................................................................................................562 Counter Registers ..........................................................................................................................562 ROFmid ..........................................................................................................................................562 ROFhi .............................................................................................................................................562 FHR ................................................................................................................................................563 IHR .................................................................................................................................................563 EHR1 .............................................................................................................................................564 EHR1Th11 .....................................................................................................................................564 EHT1Th12 ......................................................................................................................................565 BHR ...............................................................................................................................................565 BHRTh11 .......................................................................................................................................566 BHRTh12 .......................................................................................................................................566 CntEn1 ...........................................................................................................................................567 Reset Register (RESET) ................................................................................................................568 Command Register (CMD1) ..........................................................................................................568 Status Register (STAT1) ................................................................................................................569 Interrupt Request and Mask Registers ..........................................................................................570 MainIRQ .........................................................................................................................................570 M_MainIRQ ....................................................................................................................................571 CntrIRQ1 ........................................................................................................................................572 M_CntrIRQ1 ...................................................................................................................................573 Configuration Registers .................................................................................................................574 CONF5 ...........................................................................................................................................574 CONF6 ...........................................................................................................................................575 CONFC ..........................................................................................................................................575 H1CONF ........................................................................................................................................576 H2CONF ........................................................................................................................................576 H3CONF ........................................................................................................................................577 H4CONF ........................................................................................................................................577 H5CONF ........................................................................................................................................578 Page 16 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Overhead Frame Processor Architecture: Transmit Direction ...................................................... 579 OFP_Tx Register Description ........................................................................................................ 582 Counter Registers .......................................................................................................................... 582 PTRINC ......................................................................................................................................... 582 PTRDEC ........................................................................................................................................ 582 ND_EVCNT ................................................................................................................................... 583 JUSCNT ........................................................................................................................................ 583 JUSCNTTh11 ................................................................................................................................ 584 CntEn1 ........................................................................................................................................... 584 Reset Register (RESET) ............................................................................................................... 585 Command Register (CMD1) .......................................................................................................... 586 Status Registers ............................................................................................................................ 587 STAT1 ........................................................................................................................................... 587 STAT2 ........................................................................................................................................... 587 Interrupt and Mask Registers ........................................................................................................ 588 MainIRQ ........................................................................................................................................ 588 M_MainIRQ ................................................................................................................................... 589 CntrIRQ1 ....................................................................................................................................... 590 M_CntrIRQ1 .................................................................................................................................. 591 IRQ3 .............................................................................................................................................. 592 M_IRQ3 ......................................................................................................................................... 593 Configuration Registers ................................................................................................................. 594 CONF1 .......................................................................................................................................... 594 CONF2 .......................................................................................................................................... 595 CONF3 .......................................................................................................................................... 595 CONF4 .......................................................................................................................................... 596 CONF5 .......................................................................................................................................... 596 CONF6 .......................................................................................................................................... 597 CONF7 .......................................................................................................................................... 598 CONF8 .......................................................................................................................................... 598 CONF9 .......................................................................................................................................... 599 CONF10 ........................................................................................................................................ 599 Overhead Frame Processor Architecture: Receive Direction ........................................................ 600 Counter Registers .......................................................................................................................... 604 ROFmid ......................................................................................................................................... 604 B1BITCNT ..................................................................................................................................... 604 B1BITCNTTh11 ............................................................................................................................. 605 B1BITCNTTh12 ............................................................................................................................. 605 B1BLKCNT .................................................................................................................................... 606 B1BLKCNTTh11 ............................................................................................................................ 606 B1BLKCNTTh12 ............................................................................................................................ 607 B2BITCNT ..................................................................................................................................... 607 B2BITCNTTh11 ............................................................................................................................. 608 B2BITCNTTh12 ............................................................................................................................. 608 B2BITCNTTh21 ............................................................................................................................. 609 B2BITCNTTh22 ............................................................................................................................. 609 B2BLKCNT .................................................................................................................................... 610 B2BLKCNTTh11 ............................................................................................................................ 610 B2BLKCNTTh12 ............................................................................................................................ 611 B2BLKCNTTh21 ............................................................................................................................ 611 B2BLKCNTTh22 ............................................................................................................................ 612 nrm.toc.01 August 14, 2000 Page 17 IBM3206K0424 IBM Processor for Network Resources Preliminary B3BITCNT ......................................................................................................................................612 B3BITCNTTh11 .............................................................................................................................613 B3BITCNTTh12 .............................................................................................................................613 B3BLKCNT ....................................................................................................................................614 B3BLKCNTTh11 ............................................................................................................................614 B3BLKCNTTh12 ............................................................................................................................615 MSREICNT ....................................................................................................................................615 MSREICNTTh11 ............................................................................................................................616 MSREICNTTh12 ............................................................................................................................616 HPREICNT .....................................................................................................................................617 HPREICNTTh11 ............................................................................................................................617 HPREICNTTh12 ............................................................................................................................618 PJ_EVCNT .....................................................................................................................................618 NJ_EVCNT ....................................................................................................................................619 ND_EVCNT ....................................................................................................................................619 CntEn1 ...........................................................................................................................................620 CntEn2 ...........................................................................................................................................621 Reset Register (RESET) ................................................................................................................622 Status Registers .............................................................................................................................622 STAT1 ............................................................................................................................................622 STAT2 ............................................................................................................................................623 STAT3 ............................................................................................................................................624 STAT4 ............................................................................................................................................625 Interrupt and Mask Registers .........................................................................................................626 MainIRQ .........................................................................................................................................626 M_MainIRQ ....................................................................................................................................627 CntrIRQ1 ........................................................................................................................................628 M_CntrIRQ1 ...................................................................................................................................629 CntrIRQ2 ........................................................................................................................................630 M_CntrIRQ2 ...................................................................................................................................631 CntrIRQ3 ........................................................................................................................................632 M_CntrIRQ3 ...................................................................................................................................633 IRQ6 ...............................................................................................................................................634 M_IRQ6 ..........................................................................................................................................635 IRQ7 ...............................................................................................................................................636 M_IRQ7 ..........................................................................................................................................637 IRQ8 ...............................................................................................................................................638 M_IRQ8 ..........................................................................................................................................639 Configuration Registers .................................................................................................................640 CONF1 ...........................................................................................................................................640 CONF2 ...........................................................................................................................................641 CONF3 ...........................................................................................................................................642 CONF4 ...........................................................................................................................................643 CONF7 ...........................................................................................................................................644 CONF8 ...........................................................................................................................................645 CONF9 ...........................................................................................................................................645 Page 18 nrm.toc.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Memory Map for Registers and Arrays ...................................................................... 647 Signal Pin Listing By Signal Name ............................................................................. 648 AC Timing Characteristics .......................................................................................... 653 Synchronous DRAM Timing Diagrams ............................................................................................ 656 SRAM Timing Diagrams .................................................................................................................... 666 EPROM Timing Diagrams .................................................................................................................. 670 PHY Timing Diagrams ........................................................................................................................ 674 Revision Log ................................................................................................................ 676 nrm.toc.01 August 14, 2000 Page 19 IBM3206K0424 IBM Processor for Network Resources Preliminary Page 20 nrm.toc.01 August 14, 2000 . IBM3206K0424 IBM Processor for Network Resources Preliminary Features * Supports multiple protocols, including ATM, POS, Frame Relay, and 10/100/Gigabit Ethernet * Has a customizable on-chip 133 MHz PowerPC processor core * Manages up to 65535 simultaneous logical channels, individually or in groups * Integrated 155 Mb/s SONET (Synchronous Optical Network) Framer for simpler, low bandwidth designs * Flexible ATM Forum-compliant UTOPIA II interface with up to four PHYs * Switch Interface Extensions * PCI 32/64-bit interface up to 66MHz. * Configurable for sustained performance through the subsystem: - 155Mb/s full duplex internal SONET framer - 622Mb/s full duplex using an external SONET framer - 622Mb/s across up to four full duplex 155Mb/s links using an external quad framer * JTAG Test Interface * Package: 624 lead, 32 mm x 32 mm CBGA * Power Supply: 2.6 V 2%; 3.3 V 5%. Description The IBM Processor for Network Resources (IBM3206K0424) is an Asynchronous Transfer Mode (ATM) support device. It is an interface and translator between a Peripheral Component Interconnect (PCI) bus and an ATM Utopia or similar interface to an ATM PHY. The IBM3206K0424 has an integrated Packet/Frame Memory (DRAM controller) and performs Segmentation and Reassembly (SAR) functions for several of the ATM Adaptation Layers (AALs). The IBM3206K0424 functions are illustrated in the Block Diagram on page 21. A Network Interface Card example is shown in System Context of an ATM Subsystem on page 34. Block Diagram (See page 29 for descriptions of subsystems) Control Memory Packet Memory 66MHz PCI Bus Interface Virtual/Real Memory Interfaces Each supports up to 4MB SRAM or 128MB DRAM DMA Engine IBM Processor for Network Resources PowerPC 133MHz (ABR & User Fxn) Transmit Queuing Interface Receive Queuing Interface PHY Interface UTOPIA (622Mb/s) SONET Framer (155Mb/s) SAR Control Bus Cell Scheduling & Segmentation Cell Buffering Frame Reassembly EPROM (init) pnr25.chapt01.01 August 14, 2000 Features Page 21 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Ordering Information Part Number IBM3206K0424 Network Resource Manager Description Conventions The bit notation is non-IBM, meaning that bit zero is the least significant bit and bit 31 is the most significant bit for a four-byte word. The internal addressing view of the IBM3206K0424 registers and memory is big endian. In most cases, a system will wire its PCI bus interface to make the register view transparent, that is, the most significant bit in this specification will be the most significant bit in the register. If registers are read and written 32 bits at a time (which is the only way to access many of the registers), the endian-ness should not be a programming issue with respect to the registers. The IBM3206K0424 DMA controller can transfer data in either big endian or little endian mode. See General Purpose DMA (GPDMA) on page 175 for details. Numeric notation is as follows: * Hexadecimal values are usually preceeded by x or X. For example: X'0B00'. For individual registers, Address values are hexadecimal without any special markings. For example, XXXX 1C3C. * Binary values in text are either spelled out (zero and one) or appear in quotation marks. For example: `10101'. * Binary values in the Default and Description columns of the register sections are often isolated from text as in this example: 0: No action on read access 1: Auto-reset interrupt request register upon read access Conventions Page 22 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Standards Compliance The IBM Processor for Network Resources, part number IBM3206K0424, has been designed with a number of standards in mind. These standards are listed below, grouped according to the area of IBM3206K0424 functionality they address. * Network (defined by ITU-TS (formerly CCITT), ANSI and ATM Forum) ITU Recommendation I-361 - B-ISDN ATM layer specification ITU Recommendation I.362 - B-ISDN ATM Adaptation Layer (AAL) functional description ITU Recommendation I.363 - B-ISDN ATM Adaptation Layer (AAL) specification ITU Recommendation I.413 - B-ISDN user-network interface ITU Recommendation I-432 - B-ISDN user-network interface - Physical Layer specification ITU Recommendation I-610 - OAM principles of B-ISDN access ANSI T1.ATM-199x Draft, Broadband ISDN - ATM Layer Functionality and Specification ANSI T1.CBR-199x Draft, Broadband ISDN - ATM Adaptation Layer for Constant Bit Rate Service Functionality and Specification - ATM Forum 93-620R2 - ATM User-Network Interface Specification - Version 2.3 (July 27, 1993) - Bellcore TA-NWT-001248 Generic Requirements for Operations of Broadband Switching Systems (October 1993) * System Interface - PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995. Interface Technical Reference, 11/89, Part number 15F2160 * PHY Interface - SATURN User Network Interface, PMC-Sierra, Inc., February 1995 - ATM Forum 93-727 An ATM PHY Data path interface, Version 2.01, March 24, 1994 - Am7968/Am7969 TAXIchip(tm) Handbook, Transparent Asynchronous Transmitter/Receiver Interface, published by Advanced Micro Devices, 1994 pnr25.chapt01.01 August 14, 2000 Standards Compliance Page 23 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Environmental Ratings Absolute Maximum Ratings Parameter Supply Voltage, VDD 1 Supply Voltage, VDD 2 Storage Temperature Ambient Temperature with Power Applied Rating 2.3 to 2.7 3.0 to 3.6 -65 to 150 -40 to 100 Unit V V Note 1 1 1 1 C C 1. These are the maximum ratings that can be applied to the device without damage. The device function and specifications are valid only within the Recommended Operating Conditions. Recommended Operating Conditions Parameter Junction Temperature Supply Voltage, VDD 1, with respect to Ground Supply Voltage, VDD 2, with respect to Ground Rating 0 to 85 2.6 2% 3.3 5% Unit C V V Power Dissipation Parameter VDD1 (nominal) V DD2 (nominal) Rating 6 2 Unit W W Standards Compliance Page 24 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Package Diagram Top View IBM3206K0424 A01 Locator also No Ball 32.5mm 32.5mm Side View Linear Tolerances: +- 0.5mm This View pnr25.chapt01.01 August 14, 2000 0.9 0.1 1.75 min 2.15 max Standards Compliance Page 25 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Pinout Viewed from Above Standards Compliance Page 26 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Dataflow EPROM Access/ PHY Control PCI Bus Test Entities CRSET CBIST SCLCK CJTAG PHY Bus Interface NPBUS PCI Interface PCINT Processor Core PCORE Interrupt Status INTST DMA Queues DMAQS General DMA Checksum CHKSM Internal Memory Bus Bus Cache BCACH GPDMA Cell Scheduler CSKED RxQ Mgmt RXQUE Arbiter ARBIT Memory Pools Control POOLS Segmentation SEGBF Reassembly REASM Virtual Memory VIMEM Async Cell Interface LINKC SONET Framer FRAMR Control Mem Controller Packet Mem Controller 8/16 Bit PHY Interface Serial Interface Control Memory Packet Memory pnr25.chapt01.01 August 14, 2000 PCI Master Interface Standards Compliance Page 27 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Functional Description The IBM3206K0424 has been designed by breaking the implementation of the various functions and dataflows into separate entities (major functional units). This processor acts as a conversion unit from a bus memory interface (which is Work Queue oriented) to a PHY level ATM. To accomplish this, the IBM3206K0424 contains the major functional units listed below and shown in the Dataflow on page 27. Control Processor Bus Interface PCINT INTST GPDMA DMAQS Memory Control MEMRY VIMEM ARBIT BCACH POOLS Transmit Data Path CSKED SEGBF Receive Data Path REASM RAALL RXQUE PHY Level Interfaces LINKC NPBUS FRAMR Hardware Protocol Assist CHKSM PCORE Base Device Functions SCLCK CRSET CBIST CJTAG Standards Compliance PCI Interface entity Interrupt Status entity General Purpose DMA entity Queue control for DMA activity DRAM controlling entity containing the COMET (Control) and PAKIT (Packet) memory controllers Virtual Memory controller Memory subsystem requestor arbitration Bus Cache entity Memory Pool manager Cell Scheduler Cell Segmentation entity Cell Re-assembly entity AAL processor Receive Queue manager Asynchronous Physical Layer interface Nodal Processor Bus interface Full SONET framing support logic TCP/IP Checksum Logic Embedded 401 Processor Core System Clock Generation and Repowering entity Hardware and Software Reset Controlling entity Built-In Self Test logic entity JTAG Test Interface Logic entity pnr25.chapt01.01 August 14, 2000 Page 28 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources Subsystem Blocks The IBM Processor for Network Resources provides the host bus interfacing, memory management for buffers and control, cell segmentation and reassembly, and PHY hardware control for an ATM adapter. External Memory consists of a number of SRAM modules, or two SDRAM arrays used for the storage of packet data and the control structures used by the IBM3206K0424. Both the Packet and Control Memory arrays consist of two 32-bit wide banks. When running at 102Mb/s or slower (full duplex aggregate throughput), a single array of memory can be used. Both control and data store are contained in this single array of memory. For a detailed description of the external memory organization refer to The DRAM Controllers (COMET/PAKIT) on page 184. The PHY (Physical) Layer interface connects to several available hardware support devices. This layer of hardware converts a parallel data stream into a serial data stream to be shipped to and from the PMD layer. The PHY and PMD end of a card design can be implemented as one of several encoding schemes and speeds, supporting both copper and fibre optic serial links. The interface will support the ATM Forum "Utopia spec," the PMC chip, and a 25Mb/s serial interface to the IBM UTP solution. (See Standards Compliance on page 23 for documents which describe these interfaces.) The PMD (Physical Media Dependent) Layer interface connects to the line drivers and receivers. This could be either a copper or a fibre optic transceiver. pnr25.chapt01.01 August 14, 2000 Subsystem Blocks Page 29 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary External Architecture The IBM Processor for Network Resources has four major interfaces: A System Bus which acts as an actively cached memory slave and as a master for the PCI 32-bit bus. The Physical (PHY) Interface which supports several physical layer hardware devices that perform parallel to serial data conversion and the rest of the transmission convergence. An External DRAM Interface that controls one or two arrays of two-bank interleaved DRAM with 60 ns access time for Packet and Control Memory. The interface is direct drive to the DRAM. The Control and Configuration Interface which covers a number of functions. It gives access from the system bus to the PHYs and to EPROM. The EPROM can also be used to hold initial device configuration, up to and including PVC configurations. Note: IBM3206K0424 has built-in, self-test logic. The four major interfaces allow the IBM Processor for Network Resources to be used in both "deep" and "shallow" adaptors with minimal external logic. (See Block Diagrams of Possible Systems on page 33 for examples.) External Architecture Page 30 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Internal Architecture Logical Channel Support The Logical Channel is the unit of resource allocation in ATM. At one level, the End Station negotiates with the Network Interface to determine the characteristics of each End Station-to-End Station connection. The resources that may be reserved in the network are defined in the ATM UNI (User Network Interface) Specification (see references in Standards Compliance on page 23). These resources include (but are not limited to) the peak and average bandwidth to be used by the logical channel, the maximum burst length that may be transmitted at the burst rate, the latency and variance of the connection, and the loss probability. The term Logical Channel rather than virtual circuit or VPI/VCI is used in this databook to provide a level of abstraction from these specific instances. A Switched Virtual Circuit (SVC) can be negotiated with specific characteristics specifically for it. A virtual path can be negotiated with the network. Several virtual circuits within that path can then be multiplexed, using the VCI on that single VPI, without having to renegotiate for each additional VCI. The Logical channel, with respect to the network, would be the Virtual Path. There would be multiple logical channels internal to the End Station based on the Virtual Circuits used within the path. Using ATM Adaptation Layers 3 and 4, a Multiplexing IDentifier (MID) can be used to provide multiple Logical Channels across a single VPI/VCI. All of these Logical Channels are dealt with uniformly in IBM3206K0424. A hierarchy of Logical Channel Descriptors can be built up, and frames or buffers can be queued to each of the LCDs. See Transmit Buffer (CSKED) on page 273 for details. Virtual Memory Support The Packet Memory space appears on the bus as a group of up to 128K buffers (configurable size). A level of indirection has been added to the addressing of Packet memory to provide these large frame buffers without requiring memory behind all of them at the same time. This has been done for a number of reasons: * The frames on the network can be up to 64KB long. * The receiver does not know how long a frame will be until it is completely received. * Software generally has a much easier time dealing with contiguous memory. The memory does not page or swap. There are two major efficiencies used internally: * The first N bytes of memory in a buffer are directly referenced. * The blocks that make up the buffers are of multiple sizes. pnr25.chapt01.01 August 14, 2000 Internal Architecture Page 31 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Queues The IBM Processor for Network Resources makes extensive use of cached single memory operation atomic queues: Transmit queues Receive queues The interface to the scheduling entity. Blocks and Frames can be queued to Logical Channels. Based on the settings in the Logical Channel Descriptor (receive side). Cells arriving can be queued individually, collected into frames, or stored in FIFO buffers. When a frame is transmitted, its memory can be "garbage collected" or a reference to the frame can be placed on an event queue for software to handle. If either a FIFO buffer scheme or frame buffer scheme is used to source or sink data on a logical channel, it is possible to set thresholds on the buffering that will cause events to be queued. When a threshold is crossed (for instance if a transmitting LC is about to run out of data to transmit), an event will be queued. Software can read these events either by polling or by being interrupted and can schedule tasks to provide more data. Events can be scheduled on the reception of the first N bytes of a frame so that header processing can begin even before the complete frame is received. This will allow "cut-through" routing to be supported. Event queues Note: In order to maintain the atomicity of 64-bit atomic transfers, the user must ensure that 64-bit transfers are bus atomic within the particular bus system in which the IBM3206K0424 is being used. Scheduling There is extensive support for transmit scheduling. Please see Transmit Path on page 37 and Transmit Scheduling Capabilities on page 38 for details. Internal Architecture Page 32 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Block Diagrams of Possible Systems Shallow Adapter for 155Mb/s PCI Bus Memory 2-256MB ECC IBM3206K0424 Optical Transceiver Short PCI Card 100 Mb/sec Card Using a TAXI Chipset PCI Bus Transmit Device Memory 2-256MB ECC IBM3206K0424 Receive Device Short PCI Card Optical Transceiver pnr25.chapt01.01 August 14, 2000 Internal Architecture Page 33 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary System Environment The dataflow context of an ATM subsystem is shown in the diagram below. The purpose of the communications subsystem of any digital device is to allow the application to share data and to adjudicate the flow of control with other devices. System Context of an ATM Subsystem Object Data Data Frames Application Object Data Communication Stack Frame Headers and Data Device Driver LAN Emulation TCP/IP Mapping Packet Memory Local Channels Segmentation Scheduling Physical Layer (TC) PMD / Transceiver Control Memory ATM Cells As shown in the figure above, data, in the form of application objects or control structures, are divided into communication frames at the communication stack interface. The stack may further partition the frames to fit reliability, efficiency, latency, and protocol requirements. In most cases, the communication stack encapsulates the data frame with protocol headers and/or trailers. These header blocks are often located in memory in areas apart from the data frames. A device driver is often given the task of moving this scattered memory to the actual transmission device. Scatter DMA is often used to make this operation efficient. In the case of the IBM Processor for Network Resources, the data can be DMAed into virtually contiguous buffers connected to and controlled by the IBM3206K0424. It is also possible to write the frame headers directly from the processor to the IBM3206K0424 memory. The fully assembled frame is enqueued for transmission over a particular logical channel. (See more on the richness of logical channels in ATM and the IBM3206K0424 in Data Structures on page 61). The logical channels with pending work are serviced by the ATM Segmentation Layer which breaks the enqueued data into 48-byte chunks (depending on the ATM Adaptation Layer (AAL)) and prefixes it with a five-byte header (yielding the prime number 53) in preparation for transmission. A Transmission Convergence (TC) sublayer appropriate for the Physical Layer (PHY) and Physical Media Dependent (PMD) connection is then exercised, making ATM cells suitable for transmission. The receiving process is the reverse of the transmission process, except that the scheduling performed during transmission is replaced by an identification-demultiplexing step during the reception of cells. System Environment Page 34 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Note: Not all of these separate parts or steps described in this section are necessary for a dedicated function system. IBM3206K0424 can easily be used in dedicated systems due to the goal of minimal processor intervention for steady state operations. pnr25.chapt01.01 August 14, 2000 System Environment Page 35 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Data Flows This section describes the data and control flow to and through the IBM3206K0424. In order for cell traffic to flow through an ATM interface, the cells require that Logical Channels be allocated. For information on Logical Channels, please see Data Structures on page 61. Feature summary * Virtual memory * Memory pools * Register read/write interface for memory allocation * Transmit path scheduling * Receive path demultiplexing * Event queues Operation summary * Basic Assurance Tests (BATs) * Initialize and configure * Test path to switch * Permanent Virtual Circuit setup * Identify LAN servers * Initialize SVCs * Run, initializing circuits (Q.93B) and transmitting data System Environment Page 36 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Transmit Path A typical transmit operation begins with the software requesting a buffer from POOLS and filling it with data via slave DMA, master DMA, or processor writes. If virtual buffers are being used, the data write operation can fail due to lack of physical buffers. In the event of a failure, the header of the packet is updated to indicate the failure. The software can audit the header after the buffer has been completely transferred, and either take action to recover the data immediately or allow CSKED to generate an event later in the transmit cycle for any buffers that have had a data write failure. Before the data can be transmitted, the buffer header must be updated to contain information required for correct transmission. Information such as data length, starting offset, and Logical Channel (LC) address are just a few of the fields that must be correctly reflected in the buffer header. For a complete list of the fields in the buffer header refer to Packet Header on page 61. In addition to the fields in the buffer header, the scheduling and segmentation sections of the Logical Channel Descriptor (LCD), such as peak rate, average rate, and AAL type, must also be set up correctly prior to transmission. For a complete list of the fields in the LCD, refer to Transmit Logical Channel Descriptor Data Structures on page 66. After the data have been transferred into packet storage and both the buffer header and the LCD structure have been correctly initialized, the buffer address is queued to CSKED. When it receives a buffer, CSKED checks the buffer header (Packet Memory) to make sure that the data transfer operation that filled the buffer completed without error. If it finds an error, CSKED posts an event to software and does nothing further with this buffer. If no error is indicated in the buffer header, CSKED fetches several fields from the LCD (Control Memory) indicated in the buffer header to determine the current state of that LCD. If the LCD is busy sending another buffer, the new buffer is queued to this LCD and will be processed when all previously enqueued buffers have been transmitted. If the LCD is not busy, CSKED updates the LCD based on several fields in the buffer header and queues the LCD to the next time slot on the time wheel (Control Memory). When CSKED detects a previously enqueued LCD on the time wheel, several fields are retrieved from the LCD. Among other things, these fields are used by CSKED to determine where on the time wheel to reschedule this LCD. The LCD address is then provided to SEGBF for processing. When CSKED provides an LCD address to SEGBF, the segmentation portion of the LCD is retrieved from Control Memory to determine both the current address at which to continue buffer segmentation and the type of cell to construct. Depending on the AAL type bits in the segmentation portion of the LCD, the cell is constructed in an internal array using data from the LCD as well as data fetched from Packet Memory. When the cell construction is complete, status is raised to LINKC indicating that a new cell is available for transmission. Transmit opportunities are repeatedly provided to SEGBF by CSKED at the desired rate until all the data in the buffer has been passed to LINKC via the cell buffer array. When SEGBF detects that no more data exists for a buffer, the LCD address is passed back to CSKED, indicating buffer completion. At this point, CSKED removes the LCD from the time wheel if no more buffers are queued in it. If more buffers are queued, the LCD is updated and the segmentation process continues until all buffers on the LCD queue are serviced. A bit in the buffer header generates a transmit complete event when no buffers remain in the queue. pnr25.chapt01.01 August 14, 2000 Transmit Path Page 37 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Transmit Scheduling Capabilities Transmit Queues and Logical Channel Traffic Shaping Extra Pin Pointer Cell based Transmission 3 Level Priority Scheduling Wheels pnr25.chapt01.01 August 14, 2000 External Control ADD Block FIFO Byte Count Threshold Stream based Transmission Fixed Rate VCI Start variable length frames as fixed intervals VPI/VCI Tail Pointer Frame Frame Based Transmission Frame Head Pointer Frame Frame Frame Frame Frame VCI desc. VCI desc. VCI desc. VPI Transmit Path Page 38 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources Receive Path As cells arrive, they pass from LINKC to REASM. REASM uses a portion of the ATM header to look up the LCD address for this cell. The LCD address is then passed to RAALL. RAALL reads the receive portion of the LCD, and then processes the cell based on the LCD information. For example, the LCD specifies what AAL to use and maintains the current reassembly state. Using the current reassembly state, the cell data is written to Packet Memory. While the data is written to Packet Memory, other functions such as CRC generation and verification are performed in parallel. If a packet is complete, all trailer verification is performed. If the packet is good, an event is placed on a receive queue in the RXQUE entity. For error scenarios, see Receive Queues (RXQUE) on page 366. At this point, software can dequeue the packet event from RXQUE using the dequeue operation. It can then examine headers, DMA the data into user space, and perform TCP checksums. When these actions are complete, the buffer is returned to the IBM3206K0424 by performing a POOLS-free buffer operation. pnr25.chapt01.01 August 14, 2000 Receive Path Page 39 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Receive Path Page 40 of 676 pnr25.chapt01.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Input/Output Definitions The several interfaces to IBM3206K0424 are described in the following sections. There are 443 active I/O pins, assigned as follows: * 90 for the PCI bus * 86 for the NPBUS * 76 for the PHY bus * 156 for the Packet Memory interface * 35 strictly for configuration and testing DRAM Memory Bus Interface PCI Bus Connections MFRAME PCBE(3-0) MSERR PAD(31-0) PPAR MPERR MINTA MINT2 PIDSEL IBM3206K0424 PCI Bus MDEVSEL MTRDY MIRDY MSTOP MGNT MREQ PAD64(63-32) PCBE64(7-4) MREQ64 MACK64 PPAR64 MPMEVENT MEXTPMEVENT pnr25.chapt02.01 August 14, 2000 DRAM Memory Bus Interface Page 41 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary PCI Bus Interface Pin Descriptions Quantity 1 4 1 32 1 1 1 1 1 1 1 1 1 1 1 Pin Name MFRAME PCBE(3-0) MSERR PAD(31-0) PPAR MPERR MINTA MINT2 PIDSEL MDEVSEL MTRDY MIRDY MSTOP MGNT MREQ Input/Output S/T/S1 T/S O/D S/T/S1 T/S S/T/S1 O/D Pin Description Cycle Frame is driven by the current master to indicate the beginning and duration of an access. Bus Command and Byte Enables are multiplexed on the same PCI pins. During address phase they define the bus command; during data phase they define the byte enables. System Error reports address parity errors, data parity errors on the Special Cycle command, or any other system error where the result will be catastrophic. Address and Data are multiplexed on the same pins. A bus transaction consists of one address phase and one or more data phases. Parity is even parity across ad(31-0) and C/BE(3-0). Parity generation is required by all PCI agents. Parity Error is for reporting data parity errors during all PCI bus transactions except Special Cycle. Interrupt A is used to request an interrupt. This is an interrupt line that will go active low when sources within the IBM3206K0424 go O/D or S/T/S1 active. It can be optionally connected to PCI interrupt B. See Entity 2: on page 135 for more details. IN S/T/S1 S/T/S1 S/T/S1 S/T/S1 IN S/T/S1 S/T/S1 Initialization Device Select is a chip select during configuration transactions. Device Select indicates the driving device has decoded its address as the target of the current transaction. Target Ready signals the target agent's ability to complete the current data phase of the transaction. Initiator Ready indicates the bus master's ability to complete the current data phase. Stop indicates the current target is requesting the master to stop the current transaction. Receives the Bus Grant line after a request has been made. Requests the bus for an initiator transfer. Address and Data are multiplexed on the same pins and provide 32 additional bits. Also, these pins are multiplexed with the ENSTATE outputs, which allow debug of various internal state machines and signals. Bus Command and Byte Enables are multiplexed on the same PCI pins for 64-bit transfer support. Request 64-bit transfer. Has the same timing as MFRAME. Acknowledge 64-bit transfer. Has the same timing as MDEVSEL. Parity Upper DWORD is the even parity bit that protects MAD64(63-32) and PCBE(7-4). When not on a PCI bus supporting 64 bits, this will drive ENSTATE outputs. 32 PAD64(63-32) 4 1 1 1 PCBE64(7-4) MREQ64 MACK64 PPAR64 T/S S/T/S1 S/T/S1 S/T/S1 1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. DRAM Memory Bus Interface Page 42 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PCI Bus Interface Pin Descriptions (Continued) Quantity Pin Name Input/Output Pin Description As a PME source, this signal is active low and indicates a power management event signalled from the IBM3206K0424. The output need to be conditioned with a card-level FET circuit so that the resulting signal (PME# on the PCI bus) can be driven with the proper driver characteristics. This signal can also function as the PME_enable function for an external source when programmable in this mode in PCINT. 1 MEXTPMEVENT IN Active low by default but programmable, this input indicates a power management event signalled from some other card component to the IBM3206K0424. 1 MPMEVENT O/D 1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it, and must be provided by the central resource. pnr25.chapt02.01 August 14, 2000 DRAM Memory Bus Interface Page 43 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary DRAM Memory Bus Interface One Control Memory and one Packet Memory bus provide the attachment to the external DRAM. Up to two arrays of 32 data bits plus potential error detection bits may be connected to each bus. DRAM Memory Bus Connections PMnCS(3-0) Packet Memory Bus PMnDQM(3-0) PMSYNRAS(1-0) PMSYNCAS(1-0) PMWE(1-0) PMCLK(4-0) PMCLKE PMADDR(20-0) PMDATA(38-0) IBM3206K0424 CMnCS(3-0) Control Memory Bus CMnDQM(3-0) CMSYNRAS(1-0) CMSYNCAS(1-0) CMSYNRAS CMWE(1-0) CMCLK(4-0) CMCLKE CMADDR(20-0) CMDATA2(38-0) DRAM Memory Bus Interface Page 44 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources DRAM Memory Bus Interface Pin Descriptions Quantity Pin Name Input/Output Pin Function Pin Description PMnCS(3:2) are bank address lines 1 and 0 and PMnCS(1:0) are the chip selects for the two arrays when using SDRAM for Packet Memory. When using SRAM, they are either the four chip selects or are eight-encoded chip selects and a valid signal. CMnCS(3:2) are bank address lines 1 and 0 and CMnCS(1:0) are the chip selects for the two arrays when using SDRAM for Control Memory. When using SRAM, they are either the four chip selects or are eight-encoded chip selects and a valid signal. PMDQM(3:0) are the DQM lines when using SDRAM for Packet Memory. They are identical copies of output enable when using SRAM. PMDQM(3:2) is just another copy of PMDQM(1:0) to reduce loading on the nets. CM0DQM(3:0) are the DQM lines when using SDRAM for Control Memory. They are identical copies of output enable when using SRAM. CMDQM(3:2) is just another copy of CMDQM(1:0) to reduce loading on the nets. 2 PMSYNRAS(1:0) Output RAS signal for packet synchronous DRAM RAS signal for control synchronous DRAM CAS signal for packet synchronous DRAM CAS signal for control synchronous DRAM Packet Memory write enable Control Memory write enable Packet Memory clock PMSYNRAS(1:0) are identical copies of the RAS signal for Packet Memory when using SDRAM. They are byte enables (3:2) when using SRAM. CMSYNRAS(1:0) are identical copies of the RAS signal for Control Memory when using SDRAM. They are byte enables (3:2) when using SRAM. PMSYNCAS(1:0) are identical copies of the CAS signal for Packet Memory when using SDRAM. They are byte enables (1:0) when using SRAM. CMSYNCAS(1:0) are identical copies of the CAS signal for Control Memory when using SDRAM. They are byte enables (1:0) when using SRAM. Packet memory write enable. Control memory write enable. There are five copies to minimize loading. Clock enable for Packet Memory when using SDRAM. There are five copies to minimize loading. Clock enable output for Control Memory when using SDRAM. 4 PMnCS(3:0) Output Packet Memory SRAM chip selects 4 CMnCS(3:0) Output Control Memory SRAM chip selects 2 PMnDQM(3:0) Output Packet memory DQM lines 2 CMnDQM(3:0) Output Control memory DQM lines 2 CMSYNRAS(1:0) Output 2 PMSYNCAS(1:0) Output 2 2 2 5 1 5 1 21 21 39 39 CMSYNCAS(1:0) PMWE(1:0) CMWE(1:0) PMCLK(4:0) PMCLKE CMCLK(4:0) CMCLKE PMADDR(20:0) CMADDR(20:0) PMDATA(38:0) CMDATA(38:0) Output Output Output Output Input/Output Packet Memory clock enable Output Control Memory clock Input/Output Control Memory clock enable Output Output Input/Output Input/Output Address signals to Packet Memory Address signals to Control Memory Data signals to and from the Packet Memory Data signals to and from the Control Memory. pnr25.chapt02.01 August 14, 2000 DRAM Memory Bus Interface Page 45 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Memory I/O Cross Reference By Device Type IBM3206K0424 I/O xxADDR(20:0) xxCS(3) xxCS(2) xxCS(1:0) xxDQM(3:2) xxDQM(1:0) xxCLKE xxWE(1:0) xxSYNRAS(1:0) xxSYNCAS(1:0) xxDATA(31:0) xxDATA(35:32) xxDATA(38:36) 1. 2. 3. 4. Sync DRAM 2-Bank Device Address(20:0) N/A Bank Address(0) Chip Select(1:0) DQM(1:0) DQM(1:0) CKE WE(1:0)1 RAS(1:0) 1 CAS(1:0) 1 Data(31:0) ECC(3:0) ECC(6:4) Sync DRAM 4-Bank Device Address(20:0) Bank Address(1) Bank Address(0) Chip Select(1:0) DQM(1:0) DQM(1:0) CKE WE(1:0)1 RAS(1:0)1 CAS(1:0)1 Data(31:0) ECC(3:0) ECC(6:4) WE(1:0)1 Byte Enable(3:2) Byte Enable(1:0) Data(31:0) Parity(3:0) N/A SRAM Address(20:0) Chip Select(3) Chip Select(2) Chip Select(1:0) OE(1:0) 1 OE(1:0) 1 All signal groups marked by an asterisk are active at the same time. xx = CM for Control Memory or PM for Packet Memory. For SDRAMs, the DQM signals are active independently for shared ECC configurations. For SDRAMs with split ECC, the DQMs are usually active unless doing burst length two and the DQM is needed to terminate a burst. DRAM Memory Bus Interface Page 46 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Possible Memory Configurations Using SDRAM With Shared ECC One Array plus ECC Module Size Storage Size 1Mx16 2Mx8 4Mx16 8Mx8 16Mx16 32Mx8 4MB 8MB 16MB 32MB 64MB 128MB Number of Devices 3 5 3 5 3 5 128MB 5 32MB 5 Storage Size 8MB Number of Devices 5 Two Arrays plus ECC Note: While it is possible to connect more than five SDRAM modules to each controller on the IBM3206K0424, it is likely the capacitive loading will not allow the interface to work at 7.5ns. The memory interface would need to be slowed down to allow the interface to work. Possible Memory Configurations Using SRAM Module Size 2Mx18 1Mx18 512Kx18 256Kx18 1Mx36 512Kx36 256Kx36 128Kx36 Memory Size for One Module N/A N/A N/A N/A 4MB 2MB 1MB N/A Memory Size for Two Modules 8MB 4MB 2MB 1MB 8MB 4MB 2MB 1MB Memory Size for Four Modules 16MB 8MB 4MB 2MB 16MB 8MB 4MB 2MB 1. For x18 SRAM modules, half the data bus goes to one module, and the other half goes to a second module. The chip select to the two modules is common. Therefore, two x18 modules can be connected to a single chip select while only one x32 module can. Therefore, given a constant number of chip selects, using pairs of x18 "x" Mb modules results in a memory that is twice as deep as what is possible with x32 modules. Using x18 modules also lowers the overall capacitance on the memory data nets. 2. While it is possible with the number of chip selects available (multiplexed or not) to connect more than four SRAM modules to each controller on the IBM3206K0424, it is likely the capacitive loading will not allow the interface to work at 7.5ns. The memory interface would need to be slowed down to allow the interface to work. pnr25.chapt02.01 August 14, 2000 DRAM Memory Bus Interface Page 47 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary NPBUS The NPBUS supports access to either an EPROM or PHY level hardware microprocessor interface. The NPBUS can operate with an eight-bit multiplexed addr/data bus or an eight-bit data bus with 18 separate address pins. Generic transfer control signals work with the PHY level hardware microprocessor interface or EPROM to accomplish data transfers. NPBUS Connections PBnPHY1 PBnPHY2 ENSTATE PBnEPRM PBALE1 NPBUS Signals PBALE2 PBADDR16 PBADDR17 PBSCLK PBSDATA PBRNWRT 8 PBRDRDY PBDATA(7-0) PBINTRA PBPHYRST IBM3206K0424 NPBUS Page 48 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources NPBUS Pin Descriptions Quantity 1 Pin Name PBnPHY1 Input/Output Output Pin Function Select PHY 1 Pin Description When low, indicates that the IBM3206K0424 has selected PHY 1 to write to control registers inside PHY 1 or to read either the control or status registers. When low, indicates that the IBM3206K0424 has selected PHY 2 to write to control registers inside PHY 2 or to read either the control or status registers. See NPBUS Control Register on page 428 for more details. If configured, this pin can also be odd parity across the eight-bit wide bidirectional data bus. It can also be configured as MPMDSEL - this control pin, under register bit control, can drive a logical value out. The intention is to select between the different PMD types on the 155 Mb/s copper card (UTP verses STP). If it is in cascade mode, this bit functions as PIDSELO (+idsel out), which the primary IBM3206K0424 will drive to the secondary IBM3206K0424 when trying to update configuration space via configuration cycles. This multiplexed pin also carries the PBDATAP signal. When programmed, drives out the real-time state-of-entity state machines, counters, etc. for debug purposes. The (47-32) bits of this bus are also PBADDR(15 - 0), which are the address lines for the external parallel EPROM or PHY. Additionally, bits 47 - 40 can be used as bi-directional data bus bits to extend the PBDATA bus by providing bits 15 - 8 of this bus. This allows operation with PHY parts that have a fixed 16-bit data but limits the addressing to this PHY to only eight address bits. (LSSD test function - scanout(13 to 0) -SO -BDY) When low, indicates that the IBM3206K0424 has selected the external EPROM to read from. After reset, the IBM3206K0424 will start accessing the optional on-card ROM/EPROM and do the chip initialization function if it does not find a serial EPROM attached. 1 PBnPHY2 Output Select PHY 2 63 ENSTATE (63-0) Output 1 PBnEPRM Output EPROM Select 1 PBALE1 Output When high, indicates that the IBM3206K0424 has generated an address on the PBDATA bus and should be latched by either a Address Latch Enable 1 PHY that supports this muxing or an external octal latch TTL part. For an external EPROM, it will also latch bits 7-0 of the address for an external EPROM access. When high, indicates that the IBM3206K0424 has generated an address on the PBDATA bus and should be latched by an external Address Latch Enable 2 octal latch TTL part that holds bits 15-8 of the address for an external EPROM or PHY access. Supplies address 16 to an external EPROM. The pin will also function as PBALE3, an address latch enable, that indicates that the IBM3206K0424 has generated an address on the PBDATA bus and should be latched by an external octal latch TTL part that holds bits 23-16 of the address for an external EPROM access. The mechanism used to set this mode is to put a pull-down resistor on this pin. At reset time, it will be detected and set this bit in PBALE3 mode. Otherwise it will be in PBADDR16 mode. 1 PBALE2 Output 1 PBADDR16 Output Address Send 16 1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it and must be provided by the central resource. pnr25.chapt02.01 August 14, 2000 NPBUS Page 49 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary NPBUS Pin Descriptions (Continued) Quantity 1 1 Pin Name PBADDR17 PBSCLK Input/Output Output Output Pin Function Address Send 17 Clock for the I2C serial EPROM accesses This is the data bit that connects to the external serial EPROM to read from or write to. It must have a pullup resistor attached and supports the I2C protocol. The range of supported serial EPROM is from 256 to 2K bytes. After reset, the IBM3206K0424 will start accessing the optional on-card serial EPROM and do the chip initialization function. If this chip is pulled down (or no pullup), the IBM3206K0424 will assume that no serial EPROM is attached and will go try to fetch from a parallel EPROM. This pin allows the IBM3206K0424 to read from or write to internal registers of the PHY parts. This signal acts as the write strobe when talking to PMC-Sierra chips such as the Suni-Lite. This pin allows the IBM3206K0424 to read from or write into internal registers of the PHYs by acting as a data acknowledge signal from the memory slaves. This signal acts as the read strobe when talking to PMC-Sierra chips such as the Suni-Lite. The PB-Bus is an eight-bit wide bidirectional data bus used to interface the PHYs to the IBM3206K0424. When a data transfer is not happening, the lower four bits act as MLED(3-0) - four control pins that, under register bit control, can drive general status to LED devices. This input from PHY A is an attention line that, when low, indicates that one or more unmasked flags are set in the status registers of PHY 1. If additional PHY parts are added, they should also dot their interrupt line onto this input. This signal implements the network safety features of the Implements the network IBM3206K0424. It is the ORed value of RESET and all of the status safety features of the bits cause the IBM3206K0424 to stop transferring data. It is device asserted for a pulse, and then removed. This signal is asserted low. Pin Description Supplies address 17 to an external EPROM. 1 PBSDATA Output or Data 1 PBRNWRT Output Read or Write 1 PBRDRDY S/T/S 1 8 PBDATA(7-0) Input or Output 1 PBINTRA Input 1 PBPHYRST Output 1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it and must be provided by the central resource. NPBUS Page 50 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources ATM PHY Bus Interface The PHY Bus consists of a transmit data path, receive data paths, and control signals. PHY Bus Interface Connections 16 16 2 FYTDAT(15-0) FYTPAR(1-0) FYTSOC FYRRDB FYTWRB FYnTENB FYnRENB FYRRDB 16 2 FYRDAT(15-0) FYRPAR(1-0) FYRSOC FYRCA FYTCA FYnFUL FYEMP FYRADR(4-0) FYTADR(4-0) FYREOP FYTEOP FYRMOD FYTMOD IBM3206K0424 2 2 2 2 ATM PHY Signals FYTSDATP/N FYTSCLKP/N FYRSDATP/N FYRSCLKP/N FYDTCT FYDISCRD pnr25.chapt02.01 August 14, 2000 ATM PHY Bus Interface Page 51 of 676 IBM3206K0424 IBM Processor for Network Resources : Preliminary PHY Bus Pin Descriptions (Page 1 of 3) Quantity Pin Name Input/Output Pin Function Pin Description When using an external PHY, this 16-pin bus carries the ATM CELL octets that are loaded in the PHY Transmit FIFO. When using the internal framer, bits 15, 14, and 13 are used for the RX HDLC interface signals OFPrxR1Data, OFPrxR1DS, and OFPrxRclk, respectively. When using an external PHY, these are byte parity signals for FYTDAT. When using the internal framer, bit 1 provides the RX Out-Of-Frame indication, OOF, and bit 0 provides the optical/ electrical module transmit shutdown control signal, OFPtxSDown. When using a POS-PHY, bit zero provides the TERR signal. When using an external PHY, this indicates the start of cell on FYTDAT. When using the internal framer, this provides the TX HDLC interface signal, OFPtxT1Dclk. When using a POS-PHY, this indicates TSOP. When using an external PHY, this signal is used to write ATM cells to the transmit FIFO. When using the internal framer, this signal provides the 19.44MHz TX clock, RefClkT. When using a Utopia Cell or POS-PHY interface, this signal provides the write clock based on the clock received on the TXCLK pin. When using an external PHY, this indicates that transmit data to the PHY is valid. When using the internal framer, this provides the TX HDLC interface signal, OFPtxT1DS. When using an external PHY, this indicates to the PHY that the IBM3206K0424 is ready to accept data. When using the internal framer, this provides the clock recovery reset signal, RSTCRec1. When using an external PHY, this is used to read ATM cells from the PHY receive FIFO. When using the internal framer, this signal provides the 19.44MHz RX clock, RxByClk. When using a Utopia Cell or POS-PHY interface, this signal provides the write clock based on the clock received on the RXCLK pin. When using an external PHY, this 16-pin bus carries the ATM CELL octets that are read from the PHY Receive FIFO. 16 FYTDAT (15 - 0) Output PHY Transmit Data 2 FYTPAR (1 - 0) Output Transmit Data Parity 1 FYTSOC Output Transmit start of Cell 1 FYTWRB Output Transmit write strobe 1 FYnTENB Output Transmit write enable 1 FYnRENB Output Receive write enable 1 FYRRDB Output Receive ready strobe 16 FYRDAT(15 - 0) Input PHY Receive Data 2 FYRPAR(1 - 0) Input When using an external PHY, these are byte parity signals for FYRDAT. When using the internal framer, bit 1 provides the PHY Receive Data Parity optical/electrical module low power indication signal, OFPtxLPow, and bit 0 is not used. When using a POS-PHY, bit 0 should be connected to RERR. Note: Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being used. 2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtxLPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface. 3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the function of FYTDAT(15-13). ATM PHY Bus Interface Page 52 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PHY Bus Pin Descriptions (Page 2 of 3) Quantity 1 Pin Name FYRSOC Input/Output Input Pin Function Receive start of Cell Pin Description When using an external PHY, this signal indicates the start of cell on the FYRDAT bus. When using an external PHY, this indicates that a cell is available in the receive FIFO. When using an internal framer, this signal is not used. When using a POS-PHY, this signal must be connected to PRPA. When using an external PHY, this indicates that a cell is available in the PHY transmit FIFO. When using the internal framer, this provides the TX HDLC interface signal, OFPtxT1Data. When interfacing to POS-PHY, this signal should be connected to PTPA. When using an external PHY, this is asserted low by the PHY when it can accept no more than four more data transfers before it is full. This pin should be pulled up to the inactive state when using a PHY that does not drive it. When using the internal framer, this provides the TX HDLC interface signal, OFPtxT1DFrm. When using a POS-PHY interface, this signal must be connected to STPA When using an external PHY, this is asserted low by the PHY to indicate that in the current cycle there is no valid data for delivery to the IBM3206K0424. When the PHY does not drive FYEMP, this input should be tied to the inactive state. When using the internal framer, this signal is not used. When using a POS-PHY interface, this signal is connected to RVAL. When using an external PHY (Cell or POS-PHY based), this address is used to select and poll up to 31 PHYs on the receive side. Bits (1-0) are used to select which of the four PHYs and bit two is used to indicate the null address. When bit two is B'1', bits 1-0 are also '1'. When bit 2 is '0', bits 1-0 are "00", "01", "10", or "11". When using an external PHY (Cell or POS-PHY based), this address is used to select and poll up to 31 PHYs on the transmit side. Bits (1-0) are used to select which of the four PHYs and bit two is used to indicate the null address. When bit two is '1', bits 1-0 are also '1'. When bit 2 is '0', bits 1-0 are "00", "01", "10", or "11". When using an external POS-PHY, this signal indicates if the FYRDATA (15-0) contains the last data of a packet. If the external PHY is not a POS-PHY, this signal should be tied to GND. 1 FYRCA Input Receive Cell Available 1 FYTCA Input Transmit Cell Available 1 FYnFUL Input PHY Transmit Full 1 FYEMP Input PHY Receive Empty 5 FYRADR(4-0) Output PHY Receive Address 5 FYTADR(4-0) Output PHY Transmit Address 1 FYREOP Input PHY Receive EOP Note: Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being used. 2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtxLPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface. 3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the function of FYTDAT(15-13). pnr25.chapt02.01 August 14, 2000 ATM PHY Bus Interface Page 53 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary PHY Bus Pin Descriptions (Page 3 of 3) Quantity 1 Pin Name FYTEOP Input/Output Output Pin Function PHY Transmit EOP Pin Description When using an external POS-PHY, this signal indicates if the FYTDATA (15-0) contains the last data of a packet. If the external PHY is not a POS-PHY, this signal should ignored. When using an external POS-PHY, this signal indicates if the FYRDATA (7-0) contains valid data. If FYRMOD is '1', FYRDATA(7-0) is ignored. FYRMOD is only relevant when FYREOP is '1'. A value of '1' any other time will be ignored. If a POS-PHY is not connected, this signal should be tied to GND. When using an external POS-PHY, this signal indicates if the FYTDATA (7-0) contains valid data. If FYTMOD is '1', FYRDATA(7-0) will be ignored. FYTMOD is only driven to a '1' when FYTEOP is '1'. When using the internal framer and the internal SERDES, these signals provide the serial transmit data stream. When the transmit side of LINKC is connected to an Echo interface, this differential driver will provide the clock that goes with the data FYRDAT(7-0), parity FYTPAR(7-0), and SOC FYTSOC. When using the internal framer and the internal SERDES, the reference 155.52MHz clock is supplied on these signals. When not in use, these should be tied to (TBD). When using the internal framer and the internal SERDES, the recovered receive data is supplied on these signals. When not in use, these should be tied to (TBD). When using the internal framer and the internal SERDES, the recovered 155.52MHz clock is supplied on these signals. When not in use, these should be tied to (TBD). When using an external PHY, the PHY uses this signal to indicate carrier detect. When using the internal framer, this signal provides the deserializer lock detect signal, ELockDet, from the deserializer. When using an external PHY, this signal causes the current cell being received to be discarded. In this case it should only be asserted for the duration of one of the 53 bytes of the ATM cell. When using the internal framer, this signal provides the optical/electrical module Loss-Of-Signal indication, LossSig. 1 FYRMOD Input PHY Receive MOD 1 FYTMOD Output PHY Transmit MOD 2 FYTSDATP/N Output SERDES Transmit Data (Differential) 2 FYTSCLKP/N Input SERDES Transmit Clock (Differential) SERDES Receive Data (Differential) SERDES Receive Clock (Differential) 2 FYRSDATP/N Input 2 FYRSCLKP/N Input 1 FYDTCT Input PHY Carrier Detect 1 FYDISCRD Input PHY Cell Discard Note: Because some of the PHY transmit I/Os are used for receive framer functions and vice versa, there are some restrictions on how the interfaces can be used. 1. If the transmit path is using an external PHY and the receive path is using the internal framer, FYTPAR(1) will assume the OOF function and not be available as a parity output. This is only a concern if the PHY uses a 16-bit data interface and parity is being used. 2. If the receive path is using an external PHY and the transmit path is using the internal framer, FYRPAR(1) will assume the OFPtxLPow function and not be available as a parity input. This is only a concern if the PHY uses a 16-bit data interface. 3. If the transmit path is using an external PHY and the receive path is using the internal framer, and the external PHY has a 16-bit data interface, then the receive HDLC interface cannot be used. The three I/O for the RX HDLC interface will instead take on the function of FYTDAT(15-13). ATM PHY Bus Interface Page 54 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Transmit PHY I/O Cross Reference IBM3206K0424 I/O FYTWRB FYTCA FYnFUL FYnTENB FYTSOC FYTDAT(15) FYTDAT(14) FYTDAT(13) FYTDAT(12-8) FYTDAT(7-0) FYTPAR(1) FYTPAR(0) FYTADR(4-0) FYTMOD FYTEOP FYTDATP FYTDATN FYTCLKP FYTCLKP Suni-Lite TFCLK TCA N/A TWRENB TSOC N/A N/A N/A N/A TDAT(7-0) N/A N/A N/A N/A N/A N/A N/A N/A N/A Utopia TxCLK TxClav TxFull TxEnb TxSOC TxData(15) TxData(14) TxData(13) TxData(12-8) TxData(7-0) TxPrty(1) TxPrty(0) TxADDR(4-0) N/A N/A N/A N/A N/A N/A POS-PHY TFCLK PTPA STPA TEnb TSOP TData(15) TData(14) TData(13) TData(12-8) TData(7-0) TPRTY TERR TADR(4-0) TMOD TEOP N/A N/A N/A N/A Internal Framer RefClkT OFPtxT1Data OFPtxT1DFrm OFPtxT1DS OFPtxT1Dclk OFPrxR1Data OFPrxR1DS OFPrxR1Dclk N/A TxExtDat(7-0) OOF OFPtxSDown N/A N/A N/A TSDATP TSDATN TSCLKP TSCLKN Note: Signals marked with an overbar are active low. Inputs listed as N/A should be tied to their inactive Utopia state. pnr25.chapt02.01 August 14, 2000 ATM PHY Bus Interface Page 55 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Receive PHY I/O Cross Reference IBM3206K0424 I/O FYRRDB FYRCA FYEMP FYRENB FYRSOC FYRDAT(15-8) FYRDAT(7-0) FYRPAR(1) FYRPAR(0) FRYADR(4-0) FYRMOD FYREOP FYRSDATP FYRSDATN FYRSCLKP FYRSCLKN FYDTCT FYDISCRD FYSETCLP Suni-Lite RFCLK RCA N/A RRDENB RSOC N/A RDAT(7-0) N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Utopia RxCLK RxClav RxEmpty RxEnb RxSOC RxData(15-8) RxData(7-0) RxPrty(1) RxPrty(0) RXADDR(4-0) N/A N/A N/A N/A N/A N/A N/A N/A N/A POS-PHY RFClk PRPA RVAL RENB RSOP RDat(15-8) RDat(7-0) RPRTY RERR RADR(4-0) RMOD REOP N/A N/A N/A N/A N/A N/A N/A Internal Framer RxByClk N/A N/A RSTCRec1 N/A N/A N/A OFPtxLPow N/A N/A N/A N/A RSDATP RSDATN RSCLKP RSCLKN DTCT DISCRD SETCLP Note: Signals marked with an overbar are active low. Inputs listed as N/A should be tied to their inactive Utopia state. ATM PHY Bus Interface Page 56 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Clock, Configuration, and LSSD Connections 16 MPCIRST PCICLK PM66EN TXCLK RXCLK MPEGCLK TESTM MHALTPPC PFFCFG(2-0) PFFOSC PLLTI PVDDA NSELFT JTAGnRST JTAGTCK JTAGTMS JTAGTDI JTAGTD0 PINTCLK PDBLCLK PPLLOUT BISTnDI1 DTR CTS TXD RXD RTS DSR IBDINH1 IBDINH2 IBDRINH LEAKTST PLLTUNE(1:0) MPLLRESET JTCOMPLY pnr25.chapt02.01 August 14, 2000 Signals IBM3206K0424 ATM PHY Bus Interface Page 57 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Clock, Configuration, and LSSD Pin Descriptions Quantity 1 1 1 1 1 1 Pin Name MPCIRST PCICLK PM66EN TXCLK RXCLK MPEGCLK Input/Output Input Input Input Input Input Input Pin Description This signal causes a hardware reset when asserted low. See Entity 20: on page 511 for more details on resets. The PCICLK is a 0-33, 66MHz clock. This pin is high when on a PCI bus that runs at 33MHz - 66MHz. It is used to tell the on-chip PLL how to generate clocks. This is the LinkC asynchronous transmit clock. This is the LinkC asynchronous receive clock. An oscillator should be connected to RXCLK even if it is not functionally used. Without the RXCLK input oscillating, the chip may not reset properly. This is the MPEG asynchronous clock. When the test mode pin is not asserted, this chip runs as specified. When the test mode pin is asserted, the chip is in LSSD test mode. Transparent latches become clocked latches and I/Os change to primary test inputs and test outputs. The precise connections are specified in the VHDL. This signal is asserted high when in test mode. Used by RISCWatch to halt the Power PC core for debug purposes. This does not need to be in a TEST/NOSCAN I/O location. These bits control the "find frequency" function which sets the range bits of the PLL. Below is the encoded meaning of these bits. 000 = Enable internal register of these bits in CRSET 001 = Disable auto range function: set range to < 25.0MHz operation 3 PFFCFG (2 - 0) Input 010 = Disable auto range function: set range to 25.0MHz - 33.3MHz-011 = Disable auto range function: set range to 50.0MHz operation 100 = Enable auto range function for 19.44MHz 101 = Reserved 110 = Enable auto range function for 25.0MHz 111 = Enable auto range function for 32.0MHz This input is the auto range known frequency input that is used to time the PCI clock input. This should be connected to some oscillator on the card, for example, the PHY oscillator. This is also used as the BIST clock. Without this input oscillator, the chip will not run BIST nor will it properly reset; it is required for proper operation. When tied to '1', this input will cause the PLL to do a parametric testing at the wafer and module level. Normal mode for this pin is a '0'. Filtered Vdd source to the PLL logic. See technology application notes for filter circuit. Minus active SELFTEST input. Normal mode is a `1'. JTAG Test Reset provides an asynchronous initialization of the TAP controller. JTAG Test Clock is used to clock state information and test data into and out of the device during operation of the TAP. JTAG Test Mode Select is used to control the state of the TAP controller in the device. (LSSD test function - RARRYTCLKC - SC) JTAG Test Data Input is used to serially shift test data and test instructions into the device during TAP operation. (LSSD test function - CLKDIVTCLKC-SC) 1 TESTM Input 1 MHALTPPC Input 1 PFFOSC Input 1 1 1 1 1 1 1 PLLTI PVDDA NSELFT JTAGnRST JTAGTCK JTAGTMS JTAGTDI Input Input Input Input Input Input Input ATM PHY Bus Interface Page 58 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Clock, Configuration, and LSSD Pin Descriptions (Continued) Quantity 1 Pin Name JTAGTDO Input/Output Output Pin Description Test Data Output is used to serially shift test data and test instructions out of the device during TAP operation. (LSSD test function - PRSRAMABDONE and PLLLOCK output) This is the external test point to measure the jitter effects of the phase-lock loop circuit. PINTCLK does not serve any LSSD or MFG test function. It does not need to be on a TEST/NOSCAN location. This is the external test point that is double the frequency of the PINTCLK. It is used to clock ENSTATE state signals at this frequency. PDBLCLK does not serve any LSSD or MFG test function. It does not need to be on a TEST/NOSCAN location. This is an observation output only. This makes the output of the PLL observable. This is also the DTR signal when the SELRS232 is active. Drives the DI input during BIST. RS232 DTR for the core debugger. (LSSD test function - TCLKA-AC) RS232 CTS for the core debugger. (LSSD test function - LPRA bypass-TI) RS232 TXD for the core debugger. (LSSD test function - CLKDIVTCLKB-BC) RS232 RXD for the core debugger. (LSSD test function - BSCANTCLKB-BC) RS232 RTS for the core debugger. (LSSD test function - BSCANTCLKC-SC) RS232 DSR for the core debugger. (LSSD test function - pll testout) This is the Boundary Scan input for BSINH1. This is the Boundary Scan input for BSINH2(*). This is the Boundary Scan input for rinh. This is the STI driver/receiver leak test input. These inputs help tune the PLL operation. (LSSD test function SCANOUT(15,14)) This input is active low and resets the PLL at power up to avoid VCO runaway. This requires a reset circuit that delays a low-to-high level after power-on-reset by 150 s. (LSSD test function - this pin functions as the TESTCT [Test Clock Tree] input. When not asserted, this chip runs as specified. When asserted, the clock tree uses this input to control the clokc tree outputs - TI) This input is high for JTAG compliance and low for RISCWatch/BIST-friendly use. When this pin is high, JTAG boundary scan operations may be used to test chip I/O operation and card wiring without supplying clocks to the rest of the chip. Also, when the TAP controller enters the TEST LOGIC RESET state, the JTAG instruction is IDCODE. When this pin is low, the JTAG boundary scan logic works only if the other chip clocks are running in a normal functional manner. When the TAP controller enters the TEST LOGIC RESET state, the JTAG instruction is BYPASS in order to make this more compatible with RISCWatch. (LSSD test function - SRAM BIST result output) 1 PINTCLK Output 1 PDBLCLK Output 1 1 1 1 1 1 1 1 1 1 1 1 2 PPLLOUT BISTnDI1 DTR CTS TXD RXD RTS DSR IBDINH1 IBDINH2 IBDRINH LEAKTST PLLTUNE(1:0) Output Output Input or Output Input Input or Output Input or Output Input or Output Input or Output Input Input Input Input Input 1 MPLLRESET Input 1 JTCOMPLY Input pnr25.chapt02.01 August 14, 2000 ATM PHY Bus Interface Page 59 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary ATM PHY Bus Interface Page 60 of 676 pnr25.chapt02.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Data Structures These structures reside in Control Memory for each of the logical channels that are set up for transmission or reception. Packet Header Each packet buffer consists of two parts. The first part is the control information used by the IBM3206K0424. The second portion of the packet buffer is used to hold the actual packet data. The following figures show the structure of the transmit and receive packet headers: Transmit Packet Header Structure struct tx_min_packhead { bit32 next_buffer; bit8 AAL5_user_byte1; bit8 buffer_offset; bit16 buffer_length; bit25 lc_address; bit1 EFCI_status; bit1 reserved; bit1 dma_on_xmit; bit1 generate_CRC10; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 cell_loss_priority; }; struct tx_packhead { bit32 next_buffer; bit8 AAL5_user_byte; bit8 buffer_offset; bit16 buffer_length; bit25 lc_address; bit1 EFCI_status; bit1 reserved; bit1 dma_on_xmit; bit1 generate_CRC10; bit1 free_on_xmit; bit1 queue_on_xmit; bit1 cell_loss_priority; bit32 dma_desc_addr; bit16 bit16 }; AAL5_user_byte1_2; reserved The minimum transmit packet header size (and transmit offset) is 0xC bytes. Receive Packet Header Structure struct rx_packhead { bit32 rx_label_flags; bit8 AAL5_user_byte1; bit8 buffer_offset; bit16 buffer_length; bit25 bit1 bit5 bit1 lc_address; EFCI_status; reserved; cell_loss_priority; bit32 optional_words[7]; }; See RXAAL Packet Header Configuration on page 352 for available word choices and definitions. pnr25.chapt03.01 August 14, 2000 Packet Header Page 61 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Receive Packet Definitions // aal 5 definition struct rx_label flags { bit16 rx_label; bit2 ip_chksm_flags; bit2 proto_chksm_flags; bit1 toobig_status; bit1 memchk_status; bit1 fabort_status; bit1 badlen_status; bit1 badcpi_status; bit1 badcrc_status; bit1 reserved; bit1 reserved; bit1 reserved; bit1 route_status; bit1 error_status; bit1 done_status; }; // raw definition struct rx_label flags { bit16 rx_label; bit2 reserved; bit2 reserved; bit1 toobig_status; bit1 memchk_status; bit1 reserved; bit1 reserved; bit1 reserved; bit1 badcrc_status; bit1 reserved; bit1 reserved; bit1 reserved; bit1 route_status; bit1 error_status; bit1 done_status; }; // packet mode definition struct rx_label flags { bit16 rx_label; bit2 ip_chksm_flags; bit2 proto_chksm_flags; bit1 toobig_status; bit1 memchk_status; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 reserved; bit1 route_status; bit1 error_status; bit1 done_status; }; The minimum receive packet offset is 0xC bytes. When the optional fields are enabled, the receive packet offset increases and should be set appropriately in the receive LCD. See RXAAL Packet Header Configuration on page 352 for available word choices and definitions. Transmit and Receive Packet Header Field Descriptions (Page 1 of 3) Field Name Field Description This field is used by the hardware to chain buffers together on queues. It contains the address of the next buffer if one exists. For transmit buffers allocated in virtual memory, this field is written by the hardware with a distinctive pattern ('zzzzzBAD'x) where zzzzz is the offset of the failure when a write operation was not able to complete due to a shortage of the real buffers needed to map into the virtual address space. This field can be checked after all buffer write operations and the appropriate recovery actions are taken immediately, or when a buffer that has had a write failure is enqueued to CSKED (an event will be generated and the buffer will not be processed by CSKED). A status bit also exists in the BCACH status register indicating that a write to virtual memory has failed. With cache performance in mind, this status bit could be checked first; if it is not set, there is no need to access the header of the packet. Note: This automatic error recovery mechanism results in the restriction that this first four bytes of a transmit packet must never be written via programmed IO or DMA during preparation for transmission. If this field is written by a software or DMA operation, the automatic error detection will not work properly and undesirable results are likely. On transmit, this field contains the value to be sent in the user byte in the last cell of an AAL5 packet, if INTST is configured for one user byte. AAL5_user_byte1 On receive, this field contains the user byte from the AAL5 trailer, if INTST is configured for one user byte. When not configured for AAL5, this field is redefined. The two most significant bits contain the drop number. When in packet mode, the low five bits of this byte contain the number of bytes dropped due to the dropNBytes field in the LCD. If this bit is set, a DMA descriptor address placed in the packet header (offset 0xC) will be queued for execution. If this bit is set, CRC10 will be generated over the cell(s) in this packet. If this bit is set, the buffer will be freed after the transmission completes. If this bit is set, the buffer will be queued on the transmit complete queue after the transmission completes. next_buffer dma_on_xmit generate_CRC10 free_on_xmit queue_on_xmit Packet Header Page 62 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Transmit and Receive Packet Header Field Descriptions (Page 2 of 3) Field Name This bit is used on both transmit and receive: EFCT_status Transmit - If this bit is set, the EFCI bit in the ATM cell header will be set for each cell in this packet. Receive - This bit contains the ORed EFCI bits across all the cells that comprised this packet if this LCD is using AAL5. This bit is used on both transmit and receive: cell_loss_priority Transmit -If this bit is set, the cell loss priority bit in the ATM cell header will be set for each cell in this packet Receive - This bit contains the ORed cell loss priority bits across all the cells that comprised this packet if this LCD is using AAL5. This field contains the offset into the buffer where the data starts. This field contains the length of the packet. This is the address of the logical connection descriptor on which this packet was received. On reception, the four-byte ATM header (no HEC) is copied from the first and last cell into this area. This is an optional header word. This field contains the value to be sent in the user bytes, one and two, in the last cell of an AAL5 packet if INTST is configured for two-user byte. The normal one-byte AAL5 user byte field is not used. This field contains the AAL5 user bytes, one and two, in the last cell of an AAL5 packet if INTST is configured for two-user byte. The normal one-byte AAL5 user byte field is not filled in. This is an optional packet header word. This field is written with "RA" in ASCII (0x5241) to signal that this buffer was used by RAALL. This field contains the IP checksum status if enabled. The possible values are: 00 bit2 ip_chksm_flags 01 10 11 Not checked Good Bad Unknown Field Description buffer_offset buffer_length lc_address rx_atm_header AAL5_user_byte2 (tx) AAL5_user_byte2 (rx) bit16 rx_label This field contains the protocol checksum status if enabled. The possible values are: 00 bit2 proto_chksm_flags 01 10 11 bit1 toobig_status bit1 memchk_status bit1 fabort_status bit1 badlen_status bit1 badcpi_status bit1 badcrc_status bit1 route_status bit1 error_status bit1 done_status host_data Not checked Good Bad Unknown Indicates the current packet exceeded the maximum packet size. Indicates the current packet had a memory check (real size exceeded or virtual error). Indicates the current packet was aborted (AAL5 forward abort). Indicates the current packet had a bad AAL5 length in the trailer. Indicates the current packet had a bad AAL5 CPI field (not zero). Indicates the current packet had a bad AAL5 CRC. This bit is written when the packet is completed if it is internally routed. This bit is written when the packet is completed if an error condition occurs. This bit is written when the packet is completed. It can be used when thresholding. This is an optional word that can be copied from the LCD to the packet header. pnr25.chapt03.01 August 14, 2000 Packet Header Page 63 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Transmit and Receive Packet Header Field Descriptions (Page 3 of 3) Field Name VBA Field Description This is the IBM3206K0424 virtual buffer address of the current receive buffer. This is an optional packet header word. These words provide the current transmit queue length. See RXAAL Transmit Queue Length Compression Configuration on page 351 for more information on the format of these words. These are optional packet header words. A timestamp can be inserted in the packet header when the packet is started. The timestamp is sourced from the RXQUE timestamp register. The location of this timestamp is important so it is not overwritten when the packet is completed. For this reason, it should be the last word in the packet header. This is an optional header word. A timestamp can be inserted in the packet header when the packet is started. The timestamp is sourced from the RXQUE timestamp register. This is an optional header word. If the dma_on_xmit bit is set in the packet header, this field contains the address of the DMA descriptor that will be queued when transmission is complete. TxQueueLenH/M/L start_timestamp end_timestamp dma_desc_addr Packet Header Page 64 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Logical Channel Data Structure If LCD-based memory management is used, a 64-bit section with the following layout is inserted at byte offset 18x: Threshold Threshold Pool 1 2 ID1 Pool Bytes waiting ID1 to be transmitted Offset 0x00 CSKED Scheduling Information (3) 64-bit words 16 16 4 4 24 Four different formats, determined by whether scheduling is based on virtual path parameters or is configured for ABR. See Scheduling Portion of a Transmit Descriptor. Tx Length 16 Misc. Flags 16 ATM Header 32 Partial CRC 32 Segmentation Pointer Transmit Portion CSKED/SEGBF Shared Information (2) 64-bit words 16 MPEG-2 or ABR Data 0x50 SEGBF Segmentation Information (0-3) 64-bit words 32 OAM Data 32 total user cells 0x78 32 OAM Data User Data 32 total user cells 32 128-byte LCD total user cells 32 OAM Data 32 Unused 56 ABR Code Variables 64 On ABR Connections, the ABR code running in PCORE uses ten bytes of the LCD starting at offset 0x46 for managing the connection. LCD Cell Status LCD Cell Status LCD Cell Status 32 Fixed Blocking Data 32 total user cells with CLP=0 32 for AAL types 0x4 and 0x6 for AAL type 0x7 Receive Portion Fixed Blocking Data 32 total user cells with CLP=0 32 total user cells with CLP=0 32 Fixed Blocking Data 32 ABR Variables 8 for all other AAL types ABR code portion pnr25.chapt03.01 August 14, 2000 Packet Header Page 65 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary General LCD Layout struct lcd_struct { tx_lcd_struct tx_lcd ;/* transmit portion of the lc descriptor */ bit8 fill[N] ;/* the fill area depends on the type of tx lcd */ rx_lcd_struct rx_lcd ;/* receive portion of the lc descriptor */ }; Transmit Logical Channel Descriptor Data Structures Logical Channel Data Structure on page 65 and Scheduling Portion of a Transmit Descriptor on page 67 show the layout of the transmit portion of a Logical Channel Descriptor. When initializing an LCD, any locations that are not written to a specific value should be initialized to zeros. Fields that typically need to be initialized to a non-zero value are flagged with a # in the structure below. Note: This is only one possible layout of the transmit portion of the LCD. Some field locations vary and are further defined later in this section. Care must be taken when updating fields in the LCD and then immediately causing the updated fields to be accessed by other IBM3206K0424 entities. For example, it is possible, although not likely, under the right conditions, for a normal LCD update followed by a SEGBF cell enqueue operation to actually execute in reverse order. This is due to IBM3206K0424 internal priority levels and could result in SEGBF fetching the LCD data before it has been updated to the new value. For this reason, it is highly advisable to use the LCD update mechanism in Cell/Packet Re-assembly (REASM). The transmit portion of the LCD can be subdivided into three distinct parts based on which chip functions or entities access that particular part of the LCD. The first three 64-bit words are scheduling related and are accessed only by CSKED. The next two 64-bit words (four if using switch fabric header) are related to both scheduling and segmentation and are accessed and shared by both CSKED and SEGBF. The words following these shared locations are related only to segmentation and are accessed only by SEGBF. The number of 64-bit words in this portion of the LCD can vary from one to three. The actual number being used in an LCD is determined by the segmentation processor code entry point field of that LCD. The following figure is the layout of the entire transmit portion of the LCD. Overall Transmit LCD Layout CSKED Scheduling Information Three 64-Bit Words CSKED/SEGBF Shared Information Two 64-Bit Words SEGBF Segmentation Information Zero - Three 64-Bit Words The three 64-bit words containing CSKED scheduling information can have four different formats depending upon whether scheduling is based on virtual path parameters or is configured for ABR. If LCD-based memory management is used, a 64-bit section is inserted at byte offset `18'X. Packet Header pnr25.chapt03.01 August 14, 2000 Page 66 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources On ABR connections, the ABR code running in PCORE will use ten bytes of the LCD for managing the connection, starting at offset 0x46 in the LCD. Scheduling Portion of a Transmit Descriptor Next descriptor in chain 32 Time Stamp 32 Transmit Packet Queue Head Pointer 32 Peak Interval 16 Average Interval 16 for a standard virtual circuit Timing Data 32 Transmit Packet Queue Tail Pointer 32 Next Descriptor in Chain 32 Peak Interval 16 ABR Parameters 16 using ABR ABR Values and Timing Data 64 Transmit Packet Queue Head Pointer 32 Transmit Packet Queue Tail Pointer 32 Peak Interval 16 Average Interval 16 Reserved 32 Transmit Packet Queue Tail Pointer 32 Peak Interval 16 Average Interval 16 CSKED Scheduling Information (3) 64-bit words Next Descriptor in Chain 32 Virtual Path Descriptor Address 32 Transmit Packet Queue Head Pointer 32 for a Virtual Circuit on a Virtual Path Next Descriptor in Chain 32 Time Stamp 32 Transmit LCD Queue Head Pointer 32 Timing Data 32 Transmit LCD Queue Tail Pointer 32 for a Virtual Path pnr25.chapt03.01 August 14, 2000 Packet Header Page 67 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Transmit Logical Channel Descriptor Structure . typedef struct { bit32 next_lcd; bit16 #peak_interval; bit16 #average_interval; bit32 bit11 bit1 bit1 bit3 bit2 bit1 bit3 bit10 bit26 bit1 bit1 bit1 bit1 bit26 bit6 #timestamp; Reserved; remove_lcd; lc_on_timewheel; #alter_sched; #transmit_priority; #max_resolution; #max_burst_mult; #max_burst_value; head_packet_pointer; free_on_xmit; queue_on_xmit; conn_suss; #drop; tail_packet_pointer; reserved; bit16 transmit_length; bit8 buffer_offset; bit2 bit2 bit4 xmt_cmp_evt_mod; reserved; seg_prc_Entry_point; bit32 #ATM_header; bit32 segmentation_pointer; bit32 current_CRC; bit32 xmit_stat1; bit32 xmit_stat2; } tx_lcd_struct, *tx_lcd_struct_ptr; Packet Header Page 68 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Transmit Logical Path Descriptor Structure . typedef struct { bit32 next_lcd; bit16 #peak_interval; bit16 #average_interval; bit32 bit11 bit1 bit1 bit3 bit2 bit1 bit3 bit10 #timestamp; Reserved; remove_lcd; lc_on_timewheel; #alter_sched; #transmit_priority; #max_resolution; #max_burst_mult; #max_burst_value; bit26 forward_LCD_pointer; bit6 reserved; bit26 backwared_LCD_pointer; bit6 reserved; } tx_lpd_struct, *tx_lpd_struct_ptr; pnr25.chapt03.01 August 14, 2000 Packet Header Page 69 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Redefinition of Transmit Logical Channel Descriptor for Connections Sharing (Logical Path Bandwidth) typedef struct { bit32 next_lcd; bit32 reserved; bit32 bit11 bit1 bit1 bit3 bit2 bit14 bit26 bit1 bit1 bit1 bit1 bit2 bit26 bit6 bit16 bit8 bit2 bit2 bit4 bit32 lcd_pointer; reserved; remove_lcd; lc_on_timewheel; #alter_sched; #transmit_priority; reserved; head_packet_pointer; free_on_transmit; queue_on_transmit; dma_on_transmit; conn_suss; #drop; tail_packet_pointer; reserved; transmit_length; buffer_offset; xmt_cmp_evt_mod; reserved; seg_prc_Entry_point; #ATM_header; bit32 segmentation_pointer; bit32 current_CRC; bit32 xmit_stat1; bit32 xmit_stat2; } tx_lcd_struct, *tx_lcd_struct_ptr; Packet Header Page 70 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Redefinition of Shared and Segmentation Portion of Transmit LCD for ABR typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 bit2 bit4 xmt_cmp_evt_mod; reserved; seg_prc_Entry_point; bit32 #ATM_header; bit32 segmentation_pointer; bit32 current_CRC; bit32 xmit_stat1; bit32 xmit_stat2; bit16 bit16 bit16 bit16 reserved; explicit_rate; current_rate; minimum_rate; bit32 backward_ptr; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; Owing to the use of certain LCD fields, a connection running ABR cannot be set up for segmentation AAL types 0x6 (fixed-sized blocking) or 0x7 (MPEG-2 assist). pnr25.chapt03.01 August 14, 2000 Packet Header Page 71 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Redefinition of Segmentation Portion of Transmit LCD for Fixed Size AAL5 Blocking (segmentation type 0x6) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 bit2 bit4 xmt_cmp_evt_mod; reserved; seg_prc_Entry_point; bit32 #ATM_header; bit32 segmentation_pointer; bit32 current_CRC; bit32 xmit_stat1; bit32 xmit_stat2; bit8 bit8 bit8 bit8 bit32 #Packets_per_AAL5_frame #Blocking_size (4 bytes x'2F' for MPEG-2) Current_transport_stream_packet Current_Blocking_Count (4 bytes) reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; Redefinition of Segmentation Portion of Transmit LCD for MPEG2 (segmentation type 0x7) typedef struct { bit16 transmit_length; bit8 buffer_offset; bit2 bit2 bit4 xmt_cmp_evt_mod; reserved; seg_prc_Entry_point; bit32 #ATM_header; bit32 segmentation_pointer; bit32 current_CRC; bit32 xmit_stat1 bit32 xmit_stat2 bit8 bit8 bit8 bit8 bit32 #Packets_per_AAL5_frame #Blocking_size (4 bytes x'2F' for MPEG-2) Current_transport_stream_packet Current_Blocking_Count (4 bytes) reserved; bit32 reserved; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; Packet Header Page 72 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Redefinition of Scheduling Portion of Transmit LCD for ABR typedef struct { bit32 next_lcd; bit16 #peak_interval; bit3 #Nrm; bit3 #Trm; bit10 #Tadtf; bit8 bit8 bit16 bit11 bit1 bit1 bit3 bit2 bit1 bit13 bit26 bit1 bit1 bit4 bit26 bit6 #Nc; #Ncrm; Reserved; Tlrm1; remove_lcd; lc_on_timewheel; #alter_sched; #transmit_priority; #max_resolution; Tlrm2; head_packet_pointer; free_on_xmit; queue_on_xmit; reserved; tail_packet_pointer; reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; Redefinition of Scheduling Portion of Transmit LCD for Timers typedef struct { bit32 next_lcd; bit32 #timer_period; bit32 bit12 bit1 bit1 bit2 bit2 bit1 bit13 #timestamp; reserved; lc_on_timewheel; reserved; #timer_type; #transmit_priority; #max_resolution; reserved; bit32 #dma_desc_addr; bit32 reserved; } tx_lcd_struct, *tx_lcd_struct_ptr; Definition of LCD-Based Memory Management of Transmit LCD typedef struct { bit16 #threshold_1; bit16 #threshold_2; bit4 #pool_id1; bit4 #pool_id2; bit24 #bytes_queued; } tx_lcd_struct, *tx_lcd_struct_ptr; pnr25.chapt03.01 August 14, 2000 Packet Header Page 73 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Definition of ABR Code Variables typedef struct { bit8 #CRM; bit8 #iCDF; bit16 #iMCR; bit16 #PCR; bit8 #iRDF; bit8 #iRIF; bit16 #ICR; } tx_lcd_struct, *tx_lcd_struct_ptr; Field Definitions The following is a detailed description of the fields listed above. This data structure should be initialized at connection setup but not modified while transmission is occurring on the connection. Only those fields marked with a # typically need to be initialized to something other than zero. ABR Code Variables Definitions (Page 1 of 4) Field Name next_lcd Field Description This field is used by the hardware to chain LCDs together on queues. It contains the address of the next LCD if one exists. This field contains the minimum spacing allowed between consecutive cells on this connection. This spacing is expressed in cell times. A connection that can transmit every cell time would have a value of `1' for this field. This field contains the minimum average spacing allowed between cells transmitted on this connection. It is the inverse of the Sustainable Cell Rate. The value for this field is expressed in cell times. This field specifies the maximum number of cells a source may send for each forward RM cell. Number of cells = (2**Nrm)+1. This field provides an upper bound on the time between forward RM cells for an active source. Time = 100*(2**-Trm) msec. The ACR Decrease Time Factor is the time permitted between sending RM cells before the rate is decreased to ICR. Time = Tadtf* 0.01 sec. This field is used as a counter to determine when IBM3206K0424 cells have been sent. It should be initialized at connection setup time to `0'. This field is used as a counter to determine when CRM RM cells have been sent. It should be initialized at connection setup time to CRM. This field contains a timestamp used by the hardware to determine if transmit opportunity credits exist and if the Burst Tolerance has been exceeded. It should be initialized at connection setup time to the value in the current timeslot counter. These fields are used by the hardware to determine when the last RM cell was sent. They should be initialized to `0'. This field indicates if the LCD is currently queued to the timewheel. It should be initialized to `0'. If this bit is set, the LCD will be removed from the time wheel at next transmission opportunity. It should be initialized to `0'. peak_interval # average_interval # Nrm # Trm # Tadtf # Nc # Ncrm # timestamp # Tlrm1 & 2 lc_on_timewheel # remove_lcd # Packet Header Page 74 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources ABR Code Variables Definitions (Page 2 of 4) Field Name Field Description These encoding bits alter the scheduling of cells on a Virtual Circuit (VC) 000 = Normal Scheduling 001 = VC on VP Scheduling is not altered. This VC is contained on a virtual path and will share the VP bandwidth after one packet is sent. The scheduling parameters are contained in the descriptor for the virtual path that is pointed to by the Virtual Path Descriptor Address field in this LCD. The cells being sent out on this connection are monitored for a Peak Cell Rate (PCR). If a PCR is found, the AAL5 packet is terminated at the end of the MPEG-2 frame and the last cell is scheduled to go out at the time specified in the PCR. 010 = MPEG-2 Scheduling alter_sched # 011 = Packet-based scheduling Packets will be scheduled at the average interval and cells within the packet will be scheduled at the peak interval. This is useful for sending information where variably-sized packets need to be sent at regular intervals. 100 = ABR scheduling This VC will send Resource Management cells and adjust its transmission rate according to the behaviors specified in the ATM Forum Traffic Management Specification, Version 4.0. This VC is contained on a virtual path and will share the VP bandwidth after one cell is sent. The scheduling parameters are contained in the descriptor for the virtual path which is pointed to by the Virtual Path Descriptor Address field in this LCD. For MPEG-2 scheduling. 101 = Fair VC on VP 110 = Reserved 111 = Reserved transmit_priority # This field specifies the priority of transmission on this connection: 0=high, 1=medium, 2=low. If this bit is set, the lower eight bits of the average interval and peak interval parameters contain a fractional component. This allows a finer resolution for scheduling. For example, for a peak interval of 1.5 time units, the value written to the peak_interval field should be hex 0180. If this bit is set, the initial value of timestamp should contain the current timeslot counter shifted 16 bits to the left. The values in this field and the next field are used to limit the number of cells that can be transferred at the peak rate. The max_burst_value will be multiplied by four to the power of the value in this field to yield the maximum credit time. This time is expressed in cell times and represents the time it would take to acquire the maximum number of cell credits. This maximum credit time should equal the maximum number of cells that can be transferred at the peak rate (MBS) times the difference between the average and intervals. Maximum credit time = MBS * (AI-PI) where MBS = maximum burst size, AI = average interval, and PI = peak interval. MBS must be at least one to transmit at peak rate. If MBS is not at least one, the peak interval should be set to the average interval. The value in this field will be multiplied by four to the power of the value in the max_burst_mult field to yield the maximum credit time. This field is used to chain buffers to LCDs. This field is used to chain buffers to LCDs. This field contains the length of the currently transmitted packet. This bit is set if the header of the currently transmitted packet has specified that the packet is to be freed after transmission. This bit is set if the header of the currently transmitted packet has specified that the packet is to be queued after transmission. This bit is set if the header of the currently transmitted packet has specified that a DMA descriptor is to be queued after transmission. max_resolution # max_burst_mult # max_burst_value # head_packet_pointer tail_packet_pointer transmit_length free_on_xmit queue_on_xmit dma_on_xmit pnr25.chapt03.01 August 14, 2000 Packet Header Page 75 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary ABR Code Variables Definitions (Page 3 of 4) Field Name conn_suss drop buffer_offset Field Description This bit is used on ABR connections to suspend transmission. It should be initialized to `0'. These two bits are used to indicate which physical drop will be used for this connection. Traffic can be scheduled on up to four drops. This field contains the offset into the buffer that the transmit data starts. This two-bit field can optionally (based on a bit in the SEGBF control register) be logically ORed with bits 8-7 of a transmit complete buffer event when it is generated by the segmentation logic. This field will only be ORed when buffer address events are being generated. It will have no affect when LCD addresses are being enqueued when a transmit complete event occurs. This four-bit field is loaded into the instruction pointer for both the LCD update processor and the cell generation processor when a cell opportunity occurs for the LCD. The value loaded into this field defines what type of cell will be generated by the segmentation logic. Possible types include raw 48and 52-byte cells, AAL5 cells, switch bound cells (48-byte payload), extended switch bound cells (54-byte payload), and frame-based cells. The actual values that are associated with each type of cell will be defined at a later time. This field contains the first four bytes of the ATM header. This field contains a pointer to the next data to be transmitted. In normal operation, this field is initialized by the cell scheduler when a new frame is queued for segmentation. This field contains the CRC as it is being built. This eight-bit field contains the current count of four-byte values that have been assembled into cells and sent out on this LCD for all fix block or MPEG AAL types. Other than initialization, this field should only be accessed by the hardware. This eight-bit field should be initialized by the software to contain the number of four-byte values that constitute a packet. For MPEG2, this register should be set to x'2F' (4*x'2F' = 188 byte transport stream packet). This eight-bit field contains the number of the current transport stream packet that is being segmented. Other than initialization, this field should only be accessed by the hardware. This eight-bit field should be initialized by the software to indicate how many packets should be concatenated into an AAL5 frame. This 16-bit field contains the explicit cell rate as defined for ABR traffic on this LCD. This 16-bit field contains the current cell rate as defined for ABR traffic on this LCD. This 16-bit field contains the minimum cell rate as defined for ABR traffic on this LCD. When software needs to send a backward RM cell, this 32-bit field should be updated with the address of a buffer that contains the desired backward RM cell. After the segmentation logic transmits the cell, this field is cleared by the hardware. This 32-bit field contains a count of one of three things: the total number of user cells that have been sent on this LCD, the total number of bytes that have been sent on this LCD, or the total number of frames that have been sent on this LCD. This field should zeroed when the connection is initialized. An event will be generated when this count wraps. This 32-bit field contains a count of one of three things: the total number of user cells that have been sent on this LCD, the total number of bytes that have been sent on this LCD, or the total number of frames that have been sent on this LCD. This field should be zeroed when the connection is initialized. An event will be generated when this count wraps. These fields are compared to the upper 24 bits of the bytes_queued field to determine when a threshold is crossed and the POOL ID for the received LCD should be changed. xmt_cmp_evt_mod seg_prc_Entry_point # ATM_header # segmentation_pointer current_CRC Current_Blocking_Count Fixed_Blocking_size # Current_transport_stream_packet Packets_per_AAL5_frame # explicit_rate current_rate minimum_rate backward_ptr xmit_stat1 xmit_stat2 threshold_1&2 Packet Header Page 76 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources ABR Code Variables Definitions (Page 4 of 4) Field Name pool_id1&2 bytes_queued Field Description These fields are used to change the POOL ID when a threshold is crossed. This field is used to keep track of the number of bytes queued for transmission on this LCD. These encoded bits determine the time of timer: 00 = Relative non-periodic timer The expiration time will be in one timer period. The timer will not be scheduled again automatically. 01 = Relative periodic timer timer_type # The expiration time will be in one timer period. The timer will be automatically scheduled again. 10 = Absolute non-periodic timer The timer will expire at the time specified by the timestamp field. The timer will not be automatically scheduled again. 11 = Absolute periodic timer The timer will expire at the time specified by the timestamp field. The timer will be scheduled again, automatically, using the time specified in the timer_period field. timer_period # dma_desc_addr # This field specifies the number of timeslots before the timer expires. The DMA descriptor pointed to by this field will be queued for execution when the timer expires. Missing RM cell count. CRM limits the number of forward RM cells that may be sent in the absence of received backward RM cells. CDF is written to the NCRM field whenever a backward RM cell is detected. Cutoff Decrease Factor (CDF) controls the decrease in ACR associated with CRM. CDF is zero or a power of 2 value in the range of 1/64 to 1. iCDF represents the power of 2 that is in the denominator of CDF. CDF = 1/(2**iCDF) so iCDF = log (base 2) of 1/CDF. Range = 1 to 6. A zero value for CDF should be represented as 0xFF for iCDF. This is the reciprocal of the Minimum Cell Rate (MCR). MCR is represented in the ABR Rate format. iMCR needs to be an integer representing the interval between cells, in units of timeslots per cell. The following formula illustrates the conversion from MCR to iMCR. iMCR = 1/(MCR) * 53 * 8 * (TSP/CI*(2**23)). The Timeslot Prescalar (TSP) is defined by the CSKED Timeslot Prescalar Register. The clock interval (CI) is determined by the CRSET Clock Control Register. With the TSP set to one timeslot per cell transmission time, iMCR =1 for a full bandwidth, 2 for a half bandwidth, etc. The Peak Cell Rate (PCR) is the cell rate that the source may never exceed. PCR should be in the ABR Rate format. Rate Decrease Factor (RDF) controls the decrease in the cell transmission rate. RDF is a power of 2 value in the range of 1/32,768 to 1. iRDF represents the power of 2 that is in the denominator of RDF. RDF = 1/(2**iRDF) so iRDF = log (base 2) of 1/RDF. Range = 1 to 15. Rate Increase Factor (RIF) controls the increase in the cell transmission rate. RIF is a power of 2 value in the range of 1/32,768 to 1. iRIF represents the power of 2 that is in the denominator of RIF. RIF = 1/(2**iRIF) so iRIF = log (base 2) of 1/RIF. Range = 1 to 15. The Initial Cell Rate is the rate at which a source should send initially and after an idle period. ICR should be in the ABR Rate format. CRM iCDF iMCR PCR iRDF iRIF ICR pnr25.chapt03.01 August 14, 2000 Packet Header Page 77 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Transmit Data Structure Linkage LC CB LC CB Next LCD@ Next LCD@ Head Pointer Head Pointer Tail Pointer LC CB Packet Buffer Packet Header Next LCD@ LC CB Next LCD@ Tail Pointer Packet Data Head Pointer Tail Pointer Head Pointer Tail Pointer Packet Buffer Packet Header Packet Data Packet Buffer Packet Buffer Packet Header Packet Data Packet Header Packet Data Packet Buffer Packet Header Packet Data Packet Buffer Packet Header Packet Data Receive LCD Data Structure and Modes The format of the receive LCD structure depends on which AAL is being configured and which options are used. It is also dependent on if TCP/IP checksum verification has been enabled. When TCP/IP checksum verification is enabled, 16 additional bytes are added to the LCD format. TCP/IP checksum is enabled in the REASM Mode Register. The following are the basic layouts of the receive LCD: Packet Header Page 78 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Basic Receive LCD Layout struct BasicRxLcd { bit32 packedInfo; bit32 crcState; bit32 misc; bit32 buffPtr; bit32 stat0; bit32 stat1; bit32 hostData; bit32 misc2; bit32 reserved; bit32 reserved; bit32 reserved; bit32 reserved; }; struct ipWrd0 {; bit32 ipWrd0; bit4 frameType; bit6 skipCount; bit6 reserved; bit16 reserved; }; }; bit32 stat0; bit32 stat1; bit32 hostData; bit32 misc2; struct BasicRxLcdIP { bit32 packedInfo; bit32 crcState; bit32 bit32 bit32 bit32 ipWrd0; ipWrd1; ipWrd2; ipWrd3; bit32 misc; bit32 buffPtr; The basic layout is the same for all LCD types. Only the packed Info and misc fields vary between the different LCD types. The following sections detail the receive LCD and the differences from the basic layout for each major option. pnr25.chapt03.01 August 14, 2000 Packet Header Page 79 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Raw LCD Raw LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit1 bit3 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; reserved; reserved; size; storeCrc10; reserved; rxqNum; rxPoolId; rxOffset; // 0000 - raw // 00 - normal // 00->down 01->idle/enabled // // // // set to zero set to zero set to zero 1->52 byte cell 0->48 byte cell struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 reserved; }; A raw LCD allows raw ATM cells to be received with no reassembly. The user can select to receive 52- or 48-byte cells. The packet header may or may not contain the ATM header. The cell data is then placed after the packet header at the configured receive offset. The 52-byte mode stores the entire cell minus the HEC, and the 48-byte mode stores only the ATM cell payload. Optional CRC-10 checking is available in raw modes. Packet Header Page 80 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Raw Routed LCD Raw Routed LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit1 bit3 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; reserved; reserved; size; reserved; reserved; rxqNum; rxPoolId; rxOffset; // 0000 - raw // 01 - routed // 00->down 01->idle/enabled // // // // set to zero set to zero set to zero 1->52 byte cell 0->48 byte cell struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 routedLcd; }; A raw routed LCD receives data in the same way that a raw LCD does. Once received, the cell buffer is routed internally to the scheduler and rescheduled for transmission. Normally, when a cell is received, the receive LCD address is written into the packet header and the buffer is surfaced to the user. When a cell is routed, the routedLcd field is used to fill in the LCD address in the packet header. This allows cells to be routed out the transmit interface with the same or different VPI/VCI. The low order bits in the routedLcd field should be set correctly to free the buffer on transmission. These bits correspond to the flag bits in the packet header. Raw routing is also called forwarded or fast forward mode. pnr25.chapt03.01 August 14, 2000 Packet Header Page 81 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Raw Routed Early Drop LCD Raw Routed Early Drop LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit4 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; reserved; reserved; size; finalPoolId; rxqNum; rxPoolId; rxOffset; // 0001 - raw early drop // 01 - routed // 00->down 01->idle/enabled 11->error // // // // // set to zero set to zero set to zero 1->52 byte cell 0->48 byte cell pool id struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 routedLcd; }; A raw routed early drop LCD receives data in the same way that a raw LCD does. Once received, the cell buffer is then routed internally to the scheduler and rescheduled for transmission. Normally when a cell is received, the receive LCD address is written into the packet header and the buffer is surfaced to the user. When a cell is routed, the routedLcd field is used to fill in the LCD address in the packet header. This allows cells to be routed out the transmit interface with the same or different VP/VC. This mode should only be used when the routed cell stream is actually an AAL5 packet stream. In this mode, a cell being dropped due to resource causes the LCD to go into error mode until the cell that contains the user indicate (UIND) bit is received. All cells received in error mode are dropped, except the final cell which is forwarded. This conserves bandwidth while maintaining the AAL5 integrity. The finalPoolId provides a second poolid for the final cells to use to be sure that these final cells are always forwarded even when resources are low. The finalPoolId is only used if no buffers are available in the normal pool. The low order bits in the routedLcd field should be set correctly to free the buffer on transmit. These bits correspond to the flag bits in the packet header. This is also called forwarded or fast forward mode. Packet Header Page 82 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Raw Scatter/Cut-Through LCD Raw Scatter/Cut-Through LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit1 bit1 bit2 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; reserved; reserved; size; storeCrc10; reserved; cutThruSel; rxqNum; rxPoolId; rxOffset; // 0000 - raw // 10 - scatter/cut through // 00->down 01->idle/enabled // // // // set to zero set to zero set to zero 1->52 byte cell 0->48 byte cell struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 reserved; }; A raw scatter/cut-through LCD receives data in the same way that a raw LCD does. Once received, the cutThruSel field is used to select one of four configurations. Each configuration specifies a receive queue and a DMA queue. The cut-through selector is used to select a cut-through/scatter configuration. The DMA descriptor is then built using the cell buffer address and the data length and the flags specified in the cut-through configuration. After being built, it is enqueued to the DMA queue specified. If there is no DMA descriptor available, then a no descriptor event is enqueued. pnr25.chapt03.01 August 14, 2000 Packet Header Page 83 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary AAL5 LCD AAL5 LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit1 bit3 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; rtoTest; rtoEnable; tmpCLP; tmpCongestion; reserved; rxqNum; rxPoolId; rxOffset; // 0101 - aal5 // 00 - normal // 00->down 01->idle/enabled 10->reasm 11->error // set to zero // set to zero struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 reserved; }; An AAL5 LCD allows AAL5 packets to be received with no special processing. Packet Header Page 84 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources AAL5 Routed LCD AAL5 Routed LCD Layout struct bit4 bit2 bit2 bit1 bit1 bit1 bit1 bit1 bit3 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; rtoTest; rtoEnable; tmpCLP; tmpCongestion; reserved; rxqNum; rxPoolId; rxOffset; // 0101 - aal5 // 01 - routed // 00->down 01->idle/enabled 10->reasm 11->error // set to zero // set to zero struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit32 routedLcd; }; An AAL5 Routed LCD allows AAL5 packets to be received. Once received, the packet buffer is then routed internally to the scheduler and rescheduled for transmission. Normally when a packet is received, the receive LCD address is written into the packet header and the buffer is surfaced to the user. When a packet is routed, the routedLcd field is used to fill in the LCD address in the packet header. This allows packets to be routed out the transmit interface with the same or different VP/VC. The low order bits in the routedLcd field should be set correctly to free the buffer on transmission. These bits correspond to the flag bits in the packet header. AAL5 routing is also called forwarded or fast forward mode. Note: Non-user data cells are terminated. pnr25.chapt03.01 August 14, 2000 Packet Header Page 85 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary AAL5 Cut-Through/Scatter Mode LCD AAL5 Cut-Through/Scatter Mode LCD Packed and Miscellaneous Field Layouts struct Packed { bit4 aalType; bit2 ppMode; bit2 state; bit1 bit1 bit1 bit1 bit1 bit1 bit2 bit4 bit4 bit8 }; struct Misc { bit6 numDesc; bit2 packHeadSel; bit8 reserved; bit16 oamMask; }; struct Misc2 { bit5 reserved; bit1 useCrcNumHead; bit10 numHeadBytes; bit16 reserved; }; // 0101 - aal 5 // 10 - scatter // 00->down 01->idle/enabled 10->reasm 11->error reserved; // set to zero rtoTest; // set to zero rtoEnable; tmpCLP; tmpCongestion; reserved; cutThruSel; rxqNum; rxPoolId; rxOffset; Packet Header Page 86 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Packet LCD Packet LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit5 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; rtoTest; rtoEnable; reserved; rxqNum; rxPoolId; rxOffset; // 0111 - packet // 00 - normal // 00->down 01->idle/enabled 10->reasm 11->error // set to zero // set to zero struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 reserved; }; struct Misc2 { bit5 dropNBytes; bit11 reserved; bit16 reserved; }; A packet LCD allows packets from the POS-PHY to be received with no special processing. The headerThresh can be used to allow packet header thresholding events to be surfaced. pnr25.chapt03.01 August 14, 2000 Packet Header Page 87 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Packet Routed LCD Packet Routed LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit5 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; rtoTest; rtoEnable; reserved; rxqNum; rxPoolId; rxOffset; // 0111 - packet // 01 - routed // 00->down 01->idle/enabled 10->reasm 11->error // set to zero // set to zero struct Misc { bit6 reserved; bit2 packHeadSel; bit8 reserved; bit16 reserved; }; struct Misc2 { bit32 routedLcd; }; A packet routed LCD allows packets to be received from the POS-PHY. Once received, the packet buffer is then routed internally to the scheduler and rescheduled for transmission. Normally, when a packet is received, the receive LCD address is written into the packet header and the buffer is surfaced to the user. When a packet is routed, the routedLcd field is used to fill in the LCD address in the packet header. This allows packets to be routed out the transmit interface with the same or different LCD. The low order bits in the routedLcd field should be set correctly to free the buffer on transmit. These bits correspond to the flag bits in the packet header. This is also called forwarded or fast forward mode. Packet Header Page 88 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Packet Cut-Through Scatter Mode LCD Packet Scatter Mode LCD Packed and Miscellaneous Field Layouts struct bit4 bit2 bit2 bit1 bit1 bit1 bit3 bit2 bit4 bit4 bit8 }; Packed { aalType; ppMode; state; reserved; rtoTest; rtoEnable; reserved; cutThruSel; rxqNum; rxPoolId; rxOffset; // 0111 - aal5 // 10 - scatter // 00->down 01->idle/enabled 10->reasm 11->error // set to zero // set to zero struct Misc { bit6 numDesc; bit2 packHeadSel; bit8 reserved; bit16 reserved; }; struct Misc2 { bit5 dropNBytes; bit1 useCrcNumHead; bit10 numHeadBytes; bit16 reserved; }; pnr25.chapt03.01 August 14, 2000 Packet Header Page 89 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Field Definitions The following are the definitions of the LCD fields, grouped by major function. All reserved fields should be set to zero. Common Field Definitions Field Name Field Description Specifies the AAL for this LCD. The following are the valid values: 0000 = Raw Mode aalType 0001 = Raw Mode - Early Drop 0101 = AAL5 0110 = AAL5 - 54-Byte Mode 0111 = Packet Specifies the post processing mode for this LCD. The following are the valid values: 00 = Normal ppMode 01 = Routed 10 = Scatter/Cut-Through 11 = Reserved This specifies the reassembly state for this LCD. This field is used by the IBM3206K0424, but in order to receive cells, an LCD must be initialized to idle state. The following are the valid values: state 00 = Down State 01 = Idle State 10 = Reassembling State 11 = Error State cutThruSel rxqNum rxPoolId rxOffset stat0 stat1 hostData Specifies a cut-through configuration. The cut-through configuration specifies a receive queue to get a descriptor from, a DMA queue to enqueue the descriptor to, and a set of cut-through flags. Specifies to which receive queue normal events should be posted. Note: some events may be routed to the error queue based on your RXQUE setup. Specifies which POOL ID should be used when getting buffers for received packets. Specifies the offset into the IBM3206K0424 buffer where the received packet should be placed. A value of `0' is equivalent to 256 bytes. LC statistic word zero. Default counts the total users cells with CLP=0 received on this LC. For accurate counts, this should be initialized to zero. LC statistic word one. Default counts the total users cells received on this LC. For accurate counts, this should be initialized to `0'. If enabled, the contents of this field are placed in packet of each received packet for this LCD. One use of this is to place a correlator to a host-specific data structure for this LCD. When TCP/IP Verification is enabled, these words are used by the IBM3206K0424 to store state between cells for the TCP/IP verification process. The frameType field specifies an offset for the checksum nanoprogram. This field is used to jump to a specific algorithm to find the IP header. The skipCount field allows the user to specify a fixed amount that is always skipped before looking for the IP header using the specified algorithm. The remainder of the words should be initialized to `0'. 1 1 1 1 1 1 1 1 1 1 Note ipWrd0-3 1 1. Software should set up this field. Packet Header Page 90 of 676 pnr25.chapt03.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Raw Mode Field Definitions Field Name Field Description This field specifies how many bytes are stored when cell is received: size 01 = 52-Byte cell (no HEC) 00 = 48-Byte cell storeCrc10 When set, the CRC-10 state bit is written into the packet header. A `1' is written in the error status bit in word 0 if a bad CRC-10 is detected. When routing cells, this field is used to fill in the LCD field of the packet header. This allows the user to dynamically route cells back out the interface using a different LCD. The user should be sure to set the free on transmit bit in this field as if it were in a packet header. 1 1 Note routedLcd 1 1. Software should set up this field. pnr25.chapt03.01 August 14, 2000 Packet Header Page 91 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Packet/AAL5 Field Definitions Field Name rtoTest rtoEnable tmpCLP Field Description This is the reassembly timeout processing test-and-set bit. It is used by the IBM3206K0424 but should be initialized to `0'. If set, reassembly processing is enabled for this LC, if the LC is running AAL5. Used by the IBM3206K0424 to track the current state of the ORed CLP bit for the current AAL5 packet. This field should be set to `0' at initialization. After initialization, the IBM3206K0424 maintains this field. Used by the IBM3206K0424 to track the current state of the ORed congestion bit for the current AAL5 packet. This field should be set to `0' at initialization time. Specifies how much data should be received before poping a packet start event. If it is set to `0', only complete packet events will be popped. This field is used by the IBM3206K0424, but should be initialized to zero by software. This field is used to track the current packet under reassembly. This field is used by the IBM3206K0424 to maintain the CRC residue as the current packet is reassembled. It should be initialized to `0'. When routing cells, this field is used to fill in the LCD field of the packet header. This allows the user to dynamically route cells back out the interface using a different LCD. The user should be sure to set the free on transmit bit in this field as if it were in a packet header. Used to determine how much cut-through data is DMAed. This is used by the IBM3206K0424 for cut-through Mode 7 processing. This should be initialized to `0'. This is used by theIBM3206K0424 for scatter processing, and should be initialized to `0'. Specifies which packet header should be used for this connection. See RXAAL Packet Header Configuration on page 352 for more information. Specifies how OAM traffic should be filtered. See ATM OAM Cell Processing on page 322 for more information. When set, specifies that receive CRC will determine how many bytes to use for numHeadBytes. This is useful when a connection is carrying IP traffic, and the TCP/IP header lengths can be determined. Specifies how many bytes of data should be kept with the packet header when DMAing the final DMA list for a completed scatter packet. Must be less than the page size. Allows 0 - 31 bytes of packet data to be dropped from the beginning of the packet on POS-PHY networks. 1 1 1 1 1 1 1 1 Note 1 1 1 tmpCongestion headerThresh buffPtr crcState 1 1 1 routedLcd cutThruThresh dmaedHeader numDesc packHeadSel oamMask useCrcNumHead numHeadBytes dropNBytes 1. Software should set up this field. Packet Header Page 92 of 676 pnr25.chapt03.01 August 14, 2000 . IBM3206K0424 Preliminary IBM Processor for Network Resources Internal Organization: Entity Descriptions This part contains detailed descriptions of the entities which, working together, make up the IBM3206K0424. The data flows through the chip have already been described; now the details of the registers and algorithms will be revealed. The entity descriptions are numbered for easy reference. Note on Set/Clear Type Registers There are many registers in IBM3206K0424 that operate as a set/clear type. These registers have two addresses. The base address is for clearing bits in the register, and base address +4 bytes is for setting bits in the register. The setting or clearing operations occur only for those bits that have the value of'1' on the write of the register. Either of the addresses can be used for reading the register. Control Processor Bus Interface Entities Entity 1: The IOP Bus Specific Interface Controller (PCINT) This entity provides PCI specific interfacing between the external connection and the internal entities. It will support the following functions: * PCI memory target * PCI master * Address and data latching * Provide parity error detection and generation * Provide configuration space registers * 64-bit data path for master and slave operation * 64-bit addressing support for master and slave operation * Auto 64-bit slot detection supported * 66MHz PCI bus clock operation supported PCI Options Taken * Medium address decode design point * Locking as a memory target supported * Interrupt A will be supported, with interrupt 2 as a the sideband signal * Registers will not burst, but cause retries when a burst is attempted * BIST defaults set at the PCI 2 second maximum PCI Target Response * A Target Retry is issued if a burst crosses the end of the IBM3206K0424's memory space. * A Target Abort will be issued if AD and command bus have bad parity (address phase parity error). Optionally, if SERR is enabled, it will also be returned. * If enabled, the PERR signal will be driven on bad parity during data write cycles (data phase parity error) when the IBM3206K0424 is the target of the command. * A Target Retry will be issued by the IBM3206K0424 if internal contention will cause a large bus access delay. PCI Master Response * A Master Abort will be issued if DEVSEL is not asserted after five clocks. * If enabled, the PERR signal will be driven on bad parity during data read cycles (data phase parity error) when the IBM3206K0424 is the initiator of the command. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 93 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary PCI Master Retry * IBM3206K0424 will retry when requested by the slave. 1.1: PCINT Config Word 0 Identifies this device and vendor type, allocated by PCI SIG. Length Type Address Restrictions 32 bits Read Only XXXX 0000 Can be read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'00A11014', but alterable at power-up/reset time with Crisco code. See Entity 15: on page 428 for details. X'1410A100' Power on Reset value (Big Endian) Power on Reset value (Little Endian) Device ID Vendor ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-0 PCI Spec 15-0 15-0 Device ID Vendor ID Name 9 8 7 6 5 4 3 2 1 0 Description This is a unique two-byte device ID assigned to this adapter. This is a unique two-byte vendor ID. The IOP Bus Specific Interface Controller (PCINT) Page 94 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.2: PCINT Config Word 1 The Status register is used to record status information for the PCI bus related events. Writing '1' to a bit in this register will reset that bit. The Command register provides coarse control over a device's ability to generate and respond to PCI cycles. Access type of the Command register is read/write. See bit definitions. Length Type Address Restrictions 32 bits Read/Write and Read/Reset XXXX 0004 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'02B00000' X'0000B002' Power on Reset value (Big Endian) Power on Reset value (Little Endian) Memory Write and Invalidate Enable Fast Back-to-Back Capable Fast Back-to-Back Enable Received Master Abort Memory Space Enable 1 Received Target Abort Signaled System Error Parity Error Response Signaled Target Abort Detected Parity Error Data Parity Detected VGA Palette Snoop Bus Master Enable Wait Cycle Control Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26-25 PCI Spec 15 14 13 12 11 10-9 Name Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort DEVSEL Timing 9 8 7 6 5 4 3 2 Description This bit is set by the device whenever it detects a parity error, even if parity error handling is disabled (as controlled by bit 6 of PCINT Configuration Word 1). This bit is set whenever the device asserts SERR. This bit is set by a master device whenever its transaction is terminated with master-abort, except for Special Cycle. This bit is set by a master device whenever its transaction is terminated with target-abort. This bit is set by a target device whenever its transaction is terminated with target-abort. These bits are hard-wired to '01', assuming medium address decode. This bit is implemented by this bus master. It is set when this agent asserts PERR or observeS PERR asserted, AND this agent setting the bit acted as the bus master for the operation in which the error occurred, AND bit 6 of PCINT Configuration Word 1 is set. 24 8 Data Parity Detected pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 95 of 676 I/O Space Enable 0 DEVSEL Timing 66MHz Capable UDF Supported Special Cycles SERR Enable IBM3206K0424 IBM Processor for Network Resources Bit(s) 23 22 21 PCI Spec 7 6 5 Name Fast Back-to-Back Capable Reserved 66MHz Capable Description Defaults to '1' unless by Crisco code. See Entity 15: on page 428 for details. Defaults to '0' unless set by Crisco. See Entity 15: on page 428 for details. Defaults to '1' unless set by Crisco. See Entity 15: on page 428 for details. This bit on indicates that this device implements the pointer for a New Capabilities linked list at the offset 34th. See the PCI spec revision 2.2 for more details on New Capabilities. Defaults to '1' unless set by Crisco code. See Entity 15: on page 428 for details for more on Crisco. Reserved Reserved This bit can be set to a value, but is ignored by this DMA master since it never drives these types of cycles. This slave, as indicated by bit 23, however, can handle fast back-to- back addresses to it. Initialization software will set this bit if all targets are fast back-to-back capable. If this bit is '1', the SERR driver is enabled. This bit is hard-wired to '0' because stepping is not supported by this master. When this bit is '1', normal action is taken when a parity error is detected. When it is '0', any parity errors detected are ignored and normal operation is continued. This bit is not implemented. Preliminary 20 4 Capabilities List 19-16 15-10 3-0 15-10 Reserved Reserved 9 9 Fast Back-to-Back Enable 8 7 8 7 SERR Enable Wait Cycle Control 6 5 4 3 2 1 0 6 5 4 3 2 1 0 Parity Error Response VGA Palette Snoop Memory Write and Invalidate This bit is not implemented. Enable Special Cycles Bus Master Enable Memory Space Enable I/O Space Enable This bit is set to '0', and will not monitor Special Cycle operations. If this bit is '1', this device will be allowed to act as a bus master. If this bit is '1', this device will respond to memory space accesses. If this bit is '1', this device will respond to I/O space accesses. The IOP Bus Specific Interface Controller (PCINT) Page 96 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.3: PCINT Config Word 2 The Class Code is used to identify the generic function for this device. The Revision ID is used to identify the level of function for this device. See bit definitions. Length Type Address Restrictions 32 bits Read Only XXXX 0008 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'02030025' X'25000302' Power on Reset value (Big Endian) Power on Reset value (Little Endian) Upper Byte Middle Byte Lower Byte Revision ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 PCI Spec 23-16 Upper Byte Name 9 8 7 6 5 4 3 2 1 0 Description The upper byte of the Class Code is a base code that broadly classifies the type of function this device performs. Code chosen is: X'02' - Network controller The middle byte of the Class Code is a sub-class code that identifies more specifically the function of this device. Code chosen is: X'03' - ATM controller The lower byte of the Class Code identifies a specific register-level programming interface so that device independent software can interact with this device. There are two secret functions here. By writing bit 15 to '1', the class code of `03' (ATM) changes to `00 (Ethernet). The read value of bit 15 remains '0'. By writing bit 14 to '1', bit 23 of Config Word 3 (also known as bit 7 of the Header Type byte) will reflect a value of '1', indicating that it is a multi-function device. The read value of bit 14 remains '0'. Bits 13 down to eight are still available to be set to indicate a register-level programming interface. This is the revision level of this chip. 23-16 15-8 Middle Byte 15-8 7-0 Lower Byte 7-0 7-0 Revision ID pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 97 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.4: PCINT Config Word 3 This word specifies the system cache size in units of 32-bit words, the value of the Latency Timer for this PCI bus master, the Header Type which identifies the layout of bytes in configuration space, and the register for the control and status of BIST (Built-in self-test). See bit definitions. Length Type Address Restrictions 32 bits Read/Write XXXX 000C Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'80000000' X'00000080' Power on Reset value (Big Endian) Power on Reset value (Little Endian) BIST Capable Start BIST Reserved Completion Code Header Type (Read Only) Latency Timer Cache Line Size 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29-28 27-24 23-16 15-8 7-0 PCI Spec 7 6 5-4 3-0 7-0 7-0 7-0 Name BIST Capable Start BIST Reserved Completion Code Header Type (Read Only) Latency Timer Cache Line Size 9 8 7 6 5 4 3 2 1 0 Description This bit is a '1' because this device supports BIST. Writing this bit '1' invokes BIST. This bit is reset to '0' after BIST is complete. This bit has two seconds to reset after a start BIST action. Reserved A value of '0' means this device has passed BIST. If bit 27 is on, the PRPG value failed. If bit 26 is on, the MISR value failed. Bits 25 and 24 are always '0'. The encoding chosen is X'00'. This register specifies a value of latency in units of PCI bus clocks. This register is used to best determine what read command should be used by this master. Any cache line size is supported. The IOP Bus Specific Interface Controller (PCINT) Page 98 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.5: PCINT Base Address 1 (I/O for Register) This register specifies the base address of where in PCI I/O or memory space the IBM3206K0424 registers will be mapped. When written with '1's and read back, the least significant bits read back as '0' will indicate the amount of I/O space required for this device to operate. For example, when a value of 'FFFFFFFF' is written, a value read of 'FFFFFF00' indicates that 256 bytes of address space is required. See bit definitions. The programming of this bit depends on whether the IBM3206K0424 is in 64-bit addressing mode or not. When in 64-bit addressing mode, bit 4 of the PCINT 64-bit Controller Register is set to '1', and this register specifies a memory address. When the IBM3206K0424 is not in 64-bit addressing mode because bit 4 of the PCINT 64-bit Control Register is set to '0', this register specifies an I/O address. See bit definitions and PCINT 64-bit Control Register on page 116. Length Type Address Restrictions 32 bits Read/Write XXXX 0010 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Bit 17 in the PCINT Base Address Control Register must be set to allow the IBM3206K0424 to decode addresses for this range. X'00000001' X'01000000' Power on Reset value (Big Endian) Power on Reset value (Little Endian) When in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '1'): Memory space 2 1 0 Prefetchable 9 8 7 6 5 4 3 Description This register is used to hold the address where the target device will decode for memory accesses. The size is 32K of addressing, naturally aligned. This means that only bits 31-15 are writable. Reserved and set to `0'. This base address can be mapped anywhere in 32-bit address space. The value of these bits is 00b. Memory space This is memory space, so the bit is set to '0'. Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-4 3 2-1 0 PCI Spec 31-4 3 2-1 0 Name Base Address Prefetchable pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 99 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary When not in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '0'): I/O Space 0 Reserved 9 8 7 6 5 4 3 2 1 Description This register is used to hold the address where the target device will decode for I/O accesses. The size is 16K of addressing, naturally aligned. This means that only bits 31-14 are writable. The PCI specification only allows 256 bytes of I/O Base Address, so this address is only for special applications. Using the feature of non-postable writes for I/O cycles must accompany enough I/O space in the system memory map. Reserved and set to `0'. This is I/O space, so this bit is set to a `1'. Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) PCI Spec Name 31-2 31-2 Base Address. 1 0 1 0 Reserved. I/O Space. The IOP Bus Specific Interface Controller (PCINT) Page 100 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.6: PCINT Base Address 2 (Mem for Register) This register specifies the base address of where in PCI memory space the IBM3206K0424 registers will be mapped. When written with '1's and read back, the least significant bits read back as '0' will indicate the amount of memory space required for this device to operate. For example, when a value of 'FFFFFFFF' is written, a value read of 'FFFFFF00' indicates that 256 bytes of address space this required. See bit definitions. The programming of this bit depends on whether the IBM3206K0424 is in 64-bit addressing mode or not. When in 64-bit addressing mode, bit 4 of the PCINT 64 bit Controller Register is set to '1', and this register specifies a memory address. When the the IBM3206K0424 is not in 64-bit addressing mode because bit 4 of the PCINT 64-bit Control Register is set to `0', this register specifies an I/O address. See bit definitions and PCINT 64-bit Control Register on page 116. Length Type Address Restrictions 32 bits Read/Write XXXX 0014 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Bit 16 in the PCINT Base Address Control Register must be set to allow the IBM3206K0424 to decode addresses for this range. X'00000000' X'00000000' Power on Reset value (Big Endian) Power on Reset value (Little Endian) When in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '1'): Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 PCI Spec 31-0 Name Upper part of Base Address 9 8 7 6 5 4 3 2 1 0 Description This register is used to hold the upper 32 bits of address during a 64 bit addressing dual cycle access. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 101 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary When not in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '0'): Memory Space 1 0 Prefetchable 9 8 7 6 5 4 3 2 Description This register is used to hold the address where the target device will decode for memory accesses. The size is 32K of addressing, naturally aligned. This means that only bits 31-15 are writable. This memory space is non-prefetchable, so this bit is set to `0'. This means that there are side effects on reads. This base address can be mapped anywhere in 32 bit address space. The value of these bits is `00'. Memory Space This is memory space, so this bit is set to '0'. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-4 PCI Spec 31-4 Name Base Address 3 2-1 0 3 2-1 0 Prefetchable The IOP Bus Specific Interface Controller (PCINT) Page 102 of 676 pnr25.chapt04.01 August 14, 2000 00 Base Address IBM3206K0424 Preliminary IBM Processor for Network Resources 1.7: PCINT Base Addresses 3-6 (Memory) This register specifies the base address of where in PCI memory space the IBM3206K0424 memory will be mapped. When written with '1's and read back, the least significant bits read back as '0' will indicate the amount of memory space required for this device to operate. For example, when a value of 'FFFFFFFF' is written, a value read of 'FFFFFF00' indicates that 256 bytes of address space this required. See bit definitions. The mapping for the base address of registers into IBM3206K0424 memory is one-to-one, assuming a memory windowing option is not set in the PCINT Base Addr Control Register for that base address register (BAR). Multiple BARs are only used to use a given system memory map more efficiently. As required by the BAR, the addresses are size-aligned. For example, that means a 16MB size could be represented with one BAR as one 16MB size aligned on a 16MB boundary. However, four-4MB BARs could represent the same 16MB size but be aligned on any 4MB boundary. The value in any of the BARs does not map directly to any particular IBM3206K0424 memory structure, such as Control Memory. The addresses are mapped using the Virtual, Packet, and Control base address registers in VIMEN. Length Type Address 32 bits Read/Write Reg 3 Reg 4 Reg 5 Reg 6 Power on Reset value (Big Endian) Power on Reset value (Little Endian) Restrictions X'00000008' X'08000000' Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. If one of these registers is not enabled (see PCINT Base Address Control Register), then a read of that register will return all '0's. The power on value stated below assumes that the register is enabled. Normally, configuration code will just read these registers to find out what is there. To enable more that the default of registers 3 and 4, the use of Crisco code could be used. See Entity 15: on page 428 for details. When in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '1'): Base Address XXXX 0018 XXXX 001C XXXX 0020 XXXX 0024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 PCI Spec 31-0 Name Upper part of Base Address 9 8 7 6 5 4 3 2 1 0 Description This register is used to hold the upper 32 bits of address during a 64 bit addressing dual cycle access. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 103 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary When not in 64-bit Addressing Mode (that is, bit 64 of PCINT 64-bit Control Register is set to '0'): Memory Space 1 0 Prefetchable 9 8 7 6 5 4 3 2 Description This register is used to hold the address where the target device will decode for memory accesses. The size of addressing is naturally aligned and determined by what is set in the PCINT Base Address Control Register. This memory space is prefetchable, so this bit is set to a `1'. This means that there are no side effects on reads, all bytes are returned on reads regardless of byte enables, and host bridges can merge processor writes into this range without causing errors. This base address can be mapped anywhere in 32-bit address space. The value of these bits is 00b. This is memory space, so this bit is set to a `0'. Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) PCI Spec Name 31-4 31-4 Base Address 3 3 Prefetchable 2-1 0 2-1 0 Type Memory Space Note: These registers power up to X'08000000' if accessed little endian. The IOP Bus Specific Interface Controller (PCINT) Page 104 of 676 pnr25.chapt04.01 August 14, 2000 Type IBM3206K0424 Preliminary IBM Processor for Network Resources 1.8: PCINT CardBus CIS Pointer This register contains the offset to where the Card Information Structure (CIS) is located. See bit definitions. Length Type Address Restrictions Power on Reset value Reserved 32 bits Read/Write XXXX 0028 Cannot be written unless by Crisco, or the PCI configuration space override write bit is on. See Entity 15: on page 428 for details. X'00000000' Address Space Indicator Address Space Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30-27 26-0 Reserved Address Space Indicator Address Space Offset Name Reserved 9 8 7 6 5 4 3 2 1 0 Description Can be set by Crisco code, likely to be in expansion ROM space. See Entity 15: on page 428 for details. This field has the offset into expansion ROM that is the location of the CIS. See the PCMCIA v2.10 specification for details of the CIS. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 105 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.9: PCINT Subsystem ID/Vendor ID This register contains the Subsystem ID and Subsystem Vendor ID. See bit definitions. Other possible codes that could be returned for the Subsystem ID are listed below. The correctness of their value is superseded by higher (IOA card) levels of documentation. Length Type Address Restrictions Power on Reset value (Big Endian) 32 bits Read/Write XXXX 002C Cannot be written unless by Crisco, or the PCI configuration space override write bit is on. X'xxxx1014' Power on Reset Value X'1410xxxx (Little Endian) Reserved Subsystem ID Subsystem Vendor ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 31-16 15-0 Reserved Subsystem ID Subsystem Vendor ID Name Reserved 9 8 7 6 5 4 3 2 1 0 Description Generally will be set by crisco code. If not set by CRISCO, this value defaults to zero. See Entity 15: on page 428 for details. Default value is the IBM vendor ID. The IOP Bus Specific Interface Controller (PCINT) Page 106 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.10: PCINT ROM Base Address This register specifies the base address of where in PCI memory space the IBM3206K0424 ROM will be mapped. When written with ones and read back, the least significant bits read back as '0' will indicate the amount of memory space required for this device to operate. For example, when a value of 'FFFFFFFF' is written, a value read of 'FFFFFF00' indicates that 256 bytes of address space is required. See bit definitions. Length Type Address Restrictions 32 bits Read/Write XXXX 0030 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as Big Endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'00000000' Address Decode Enable 3 2 1 0 Power on Reset value Base Address Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-10 9-1 0 PCI Spec 31-11 10-1 0 Name Base Address Reserved Address Decode Enable 9 8 7 6 5 4 Description This register is used to hold the address where the target device will decode for expansion ROM. The size is fixed at 2K of addressing, naturally aligned. Reserved and set to '0'. This bit set to '1' will enable accesses to expansion ROM only if Memory Space Enable bit (bit 1 in PCINT Configuration Word 1) is also set. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 107 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.11: Capabilities Pointer This register contains the Capabilities Pointer. See bit definitions. Length Type Address Restrictions Power on Reset value (Big Endian) Power on Reset value (Little Endian) Capabilities Pointer 8 bits Read only XXXX 0034 Cannot be written by Crisco or when the PCI configuration space override write bit is on. X'000000C0' X'C0000000' 8 7 6 5 4 3 2 1 0 Description Used to point to a linked list of new capabilities implemented by this device. The register is valid only if bit 4 of PCINT Config Word 1 is set. Bits 0 and 1 are always '0'. Bit(s) 7-0 Name Capabilities Pointer The IOP Bus Specific Interface Controller (PCINT) Page 108 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.12: PCINT Config Word 15 This register is used to communicate interrupt line routing information, tell which interrupt pin this device uses, and specify the desired setting for Latency Timer values. See bit definitions. Length Type Address Restrictions 32 bits Read/Write XXXX 003C Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as Big Endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'00010100' X'00010100' Power on Reset value (Big Endian) Power on Reset value (Little Endian) Max_Lat (Read Only) Min_Gnt (Read Only) Interrupt Pin (Read Only) Interrupt Line 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 PCI Spec 7-0 Name Max_Lat (Read Only). 9 8 7 6 5 4 3 2 1 0 Description This value specifies a period of time in units of 1/4 microsecond. Max_Lat is used for specifying how often this device needs to gain access to the PCI bus. This value specifies a period of time in units of 1/4 microsecond. Min_Gnt is used for specifying how long a burst period this device needs, assuming a 33MHz clock rate. This device used INTA for its PCI bus interrupt. Value of this field is `01'. Software will write the routing information into this register as it initializes and configures the system. 23-16 15-8 7-0 7-0 7-0 7-0 Min_Gnt (Read Only). Interrupt Pin (Read Only). Interrupt Line. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 109 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.13: PCINT Endian Control Register This register allows control and status to the big/little endian address selection. It controls the byte order across the PCI bus. See bit definitions. Length Type Address Restrictions Power on Reset value 32 bits Read/Write XXXX 0058 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. X'00000000' Byte Swap for Register Accesses (Memory or I/O Space) 1 Reverse the byte order for the VPD Data Register Byte Swap for Expansion ROM (on-card flash) Byte Swap for Configuration Registers Reserved See bits 4 - 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-29 28-24 23-5 4 3 2 1 0 Reserved Same as the definitions for bits 4-0 Reserved Byte Swap For Expansion ROM (on-card flash) Reverse the byte order for the VPD Data Register Byte Swap for Configuration Registers Byte Swap for Register Access (Memory or I/O space) Byte Sway for Memory Reserved. Name Reserved. 9 8 7 6 5 4 3 2 Description When this bit is set to '1', the bytes of an internal Expansion ROM access (big endian view) will be swapped to and from the PCI interface. When this bit is set to '1', the bytes of the Vital Product Data Interface - Word 2 register access will be swapped in reverse order to which bits 2 or 1 are set. When this bit is set to '1', the bytes of an internal Configuration register access (big endian view) will be swapped to and from the PCI interface. When this bit is set to '1', the bytes of an internal register access (big endian view) will be swapped to and from the PCI interface. When this bit is set to '1', the bytes of an internal Packet Memory access (big endian view) will be swapped to which bits 2 or 1 are set. The IOP Bus Specific Interface Controller (PCINT) Page 110 of 676 pnr25.chapt04.01 August 14, 2000 Byte Swap for Memory 0 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.14: PCINT Base Address Control Register This register controls all the base address registers that map to memory. See bit definitions. Length Type Address Restrictions 32 bits Read/Write XXXX 005C Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. X'0001000F' X'0F001100' Power on Reset value (Big Endian) Power on Reset value (Little Endian) Encoded Control for PCINT Base Address 6 (Memory) Encoded Control for PCINT Base Address 5 (Memory) Encoded Control for PCINT Base Address 4 (Memory) Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 23 Reserved Allow decoding for zero Base Address values Enforce sequential PCI register writes Enforce sequential PCI register reads Function Reserved 9 8 7 6 5 4 3 2 Encoded Control for PCINT Base Address 3 (Memory) 1 0 Disable retrying on the 1st cycle of a memory access Enable PCINT Base Address 2 (Mem for regs) Allow decoding for zero Base Address values Enable PCINT Base Address 1 (I/O for regs) Disable Incremental Latency time-out retries Enable writing to special config registers Enforce sequential PCI register writes Enforce sequential PCI register reads Description Setting this bit to '1' will enables decoding of a BAR address that is set to '0'. Normally, the PCI specification does not allow for a zero address to be a valid decode. Setting this bit to '1' ensures that PCI register writes will occur in sequential order of prior memory accesses or register reads. The cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete. Setting this bit to '1' ensures that PCI register reads will occur in sequential order of prior memory accesses or register writes. The cost for doing this is possible extra retry cycles for accesses not dependent on other posted accesses to complete. 22 21 pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 111 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description Preliminary 20 Setting this bit to `1' disables the retrying of a memory access to IBM3206K0424. This Disable retrying on the 1st cycle of causes a PCI spec violation, but not a data integrity problem. It solves the rare problem a memory access. in which two masters are accessing Control Memory at the same time and retries happen to both endlessly. Enable writing to special config registers Setting this bit to '1' enables writing to certain registers that are normally read-only. An example of this is the vendor and function ID register (PCINT Configuration Word 0). 19 18 Disable Incremental Latency time- Setting this bit to '1' disables PCI retries due to cycles taking more than eight cycles on out retries burst accesses after the first access. Setting this bit to '1' enables PCINT Base Address 1 (I/O for registers). This does the same function as bit 0 in the PCINT Configuration Word 1 register, but also makes the PCINT Base Address 1 (I/O for regs) read back '0's even when written to with values. It guards against anything that BIOS code may do to PCINT Configuration Word 1 register bit 0 if I/O accesses are not desired. Setting this bit to '1' enables PCINT Base Address 2 (Mem for regs) so IBM3206K0424 registers can be accessed by PCI memory cycles. 17 Enable PCINT Base Address 1 (I/O for regs) 16 15-12 11-8 7-4 Enable PCINT Base Address 2 (Mem for regs) Encoded Control for PCINT Base Address 6 (Memory) Encoded Control for PCINT Base Address 5 (Memory) Encoded Control for PCINT Base Address 4 (Memory) Same as bits 3-0. 3-0 Encoded Control for PCINT Base Address 3 (Memory). Encoding of bits: X'0': Disable this Base Address. X'1': Configured to respond to a 2 GB address size. X'2': Configured to respond to a 1 GB address size. X'3': Configured to respond to a 512 MB address size. X'4': Configured to respond to a 256 MB address size. X'5': Configured to respond to a 128 MB address size. X'6': Configured to respond to a 64 MB address size. X'7': Configured to respond to a 32 MB address size. X'8': Configured to respond to a 16 MB address size. X'9': Configured to respond to a 8 MB address size. X'A': Configured to respond to a 4 MB address size. X'B': Configured to respond to a 2 MB address size. X'C': Configured to respond to a 1 MB address size. X'D': Configured to respond to a 64K address size, and enables internal windowing of memory. X'E': Configured to respond to a 32K address size, and enables internal windowing of memory. X'F': Configured to respond to a 16K address size, and enables internal window The IOP Bus Specific Interface Controller (PCINT) Page 112 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.15: PCINT Window Offsets for Base Addresses 3-6 These registers specify the amount of memory space required for this device to operate. See bit definitions. Length Type Address 32 bits Read/Write Reg 3 Reg 4 Reg 5 Reg 6 Power on Value Restrictions X'00000000' Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Windowing Offset Range Reserved XXXX 0060 XXXX 0064 XXXX 0068 XXXX 006C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function 9 8 7 6 5 4 3 2 1 0 Description This register is used to hold the address offset, which is added to the PCI address (when windowing is enabled) to form the internal memory address. Bits 15 and 14 may or may not be used, depending on how bits are set in the PCINT Base Address Control Register. When bit 20 of PCINT Count Timeout Register is set, Window Offset register three can be updated with the address returned from a good get buffer from POOLS. This will save a write from code to this register. When bit 20 of PCINT Count Timeout Register is set, Window Offset register four can be updated with the address returned from a dequeue from the receive queue. This will save a write from code to this register. Reserved 31-14 Windowing Offset Range. 13-0 Reserved. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 113 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.16: PCINT Count Timeout Register This register holds the count limit of PCI slave retry cycles. See bit definitions. Length Type Address Restrictions 32 bits Read/Write XXXX 0070 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as Big Endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'0200FFFF' (Big Endian) Power on Reset Value X'FFFF0003' (Little Endian) Enable Dynamic Window Offset Updates Disable Register Retry Accesses Register read retry timeout value Disable PCI Locking Function Disable Slave Machine Reserved Reserved Crisco retry active Slave Transaction Timeout Retry Timeout Count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-27 26-24 23-21 20 19 18 17 16 Reserved Register read retry timeout value Reserved Enable Dynamic Window Offset Updates Disable Register Retry Accesses Disable PCI Locking Function Disable Slave Machine Reserved Function Reserved 9 8 7 6 5 4 3 2 1 0 Description The bits can be set to determine how many PCI cycles a register access will wait for an internal cycle to complete for a read access. It can be programmed to wait for up to seven cycles. A value of `0' will not timeout this access with a retry. Reserved Setting this bit to '1' enables the values of PCINT Window Offsets for Base Addresses 3-6 so that it updated with a good get primitive or certain receive queue dequeues. Setting this bit to '1' disables PCI retry signaling during a register or primitive access. Setting this bit to '1' disables this PCI locking function when set to '1' This bit is for Crisco code use. When set to '1', it disables all responses to the PCI bus in slave mode. In general, never turn this bit on. Bit 19 of the PCINT Base Address Control Register must be set before this bit can be changed. Reserved The IOP Bus Specific Interface Controller (PCINT) Page 114 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Function IBM Processor for Network Resources Description These bits hold a value that is used to count the number of PCI clocks times 256 when a PCI slave cycle is in progress. If the count is reached, due to some internal chip hang condition, a target abort is issued. A value of '0' disables target aborts from this function. These bits hold a value that is used to count the number of PCI retries. The maximum count is 256 times 16 retries. If the count is reached, a target abort is issued. A value of `0' will disable target aborts from this function. 15-8 Slave Transaction Timeout 7-0 Retry Timeout Count pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 115 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.17: PCINT 64-bit Control Register This register contains miscellaneous control bits. Length Type Address Restrictions 9 bits Read/Write XXXX 0078 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'00000XXX', where the 'X' values depend on whether bit 0 is set and values of the (Big Endian) enable bits in PCINT 64-bit Enable Register. Power on Reset Value X'XX0X0000', where the 'X' values depend on whether bit 0 is set and values of the (Little Endian) enable bits in PCINT 64-bit Enable Register. Enable Slave Register Swap Word mode Enable Slave Memory Swap Word mode Enable 64bit data phase parity checking 1 Enable Master 64-bit Addressing Enable Slave 64-bit Addressing Enable Master 64-bit Data path Enable Slave 64-bit Data Path PCI AD(63-32) Driver Control 8 7 6 5 4 3 2 Bit(s) 8 7 6 5 Name Enable Master 64-bit Data path Enable Master 64-bit Addressing 64-bit slot detected 0 Description This bit set to `1' will enable master 64-bit data path for dma transfers. This bit set to `1' will enable master 64-bit addressing. Enable Slave Register Swap Word This bit set to `1' will enable word swapping of the each of the four groups of data mode bytes in an eight-byte register transfer. 2 Enable Slave 64-bit Data Path This bit set to `1' will enable the slave 64-bit data path for registers and Packet Memory. This bit set to `1' will enable slave 64-bit addressing, making base addresses 1 and 2 available for register accesses (memory cycles only) and base addresses 3 and 4 available for Packet Memory. This bit set to `1' will cause the AD(63-32) PCI drivers to force to tri-state unless a 64-bit access is occurring. Otherwise, when set to `0', the drivers will always drive active. 4 Enable Slave 64-bit Addressing 3 PCI AD(63-32) Driver Control 2 Enable Slave Memory Swap Word This bit set to `1' will enable word swapping of the each of the four groups of data mode bytes in an eight-byte slave memory transfer through BCACH. 2 The IOP Bus Specific Interface Controller (PCINT) Page 116 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 1 Name Enable 64bit data phase parity checking IBM Processor for Network Resources Description This bit set to `1' will enable the data phase parity checking on bits 32 to 63 of the AD PCI bus. This bit will set when the REQ64# I/O pin was low bus when RST# went inactive. This bit is a read-only status bit. This bit on, combined with the status of the corresponding bit in the PCINT 64-bit Enable Register will determine the value of other bits in this register. 0 64-bit slot detected pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 117 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.18: PCINT 64-bit Enable Register See the PCINT 64-bit Control Register on page 116 for the bitwise description that the corresponding bit in this register will enable (a value of '1' means enabled). Any bit in this register ANDed with bit 0 of PCINT 64-bit Control Register will determine if the other bits in PCINT 64-bit Control Register are set. Length Type Address Restrictions 9 bits Read/Write XXXX 0088 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'0000012A' (Big Endian) Power on Reset Value X'2A010000 (Little Endian) The IOP Bus Specific Interface Controller (PCINT) Page 118 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.19: PCINT Perf Counters Control Register This register contains control bits for the PCINT performance Counter 1 and PCINT Performance Counter 2. Length Type Address Restrictions 32 bits Read/Write XXXX 007C Can be written or read during configuration cycle, memory cycle when enabled (see the PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Data Transfer Width Control - Counter 2 Master/Slave Types - Counter 2 Master/Slave Types - Counter 1 Data Direction - Counter 2 Data Direction - Counter 1 Cycles Types - Counter 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 28 27 26 Function Inject Target Abort Inject Inverted Par64 Inject Inverted Par 9 8 7 6 5 4 3 2 Cycles Types - Counter 1 1 0 Inject Inverted Par64 Data Transfer Width Control - Counter 1 Inject Target Abort Inject Inverted Par Counter Modes Inject Serr Inject Perr Reserved Description This bit on will make the target respond with a target abort sequence, provided all the other conditions are set correctly in this register. This bit on will invert the value of PCI PAR64, provided all the other conditions are set correctly in this register. This bit on will invert the value of PCI PAR, provided all the other conditions are set correctly in this register. This bit on will flow a PCI Serr#, provided all the other conditions are set correctly in this register. Bit 8 of the PCINT Config Word 1 does not need to be set to cause this condition. This bit on will flow a PCI Perr#, provided all the other conditions are set correctly in this register. Bit 6 of the PCINT Config Word 1 does not need to be set to cause this condition. These bits will determine which kind of cycle to count based on the transfer size for counter 2. The defines are the same as bits 21-20. 25 Inject Serr 24 Inject Perr Data Transfer Width Control Counter 2 23-22 pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 119 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description These bits will determine which kind of cycle to count based on the transfer size for counter 1. X'0': All transfers X'1': 32 bit transfers only X'2': 64 bit transfers only X'3': Enable Data Direction (bits 18 or 19) These bits will determine which kind of cycle to count based on the data direction - in or out of the IBM3206K0424 for counter 2. These bits will determine which kind of cycle to count based on the data direction - in or out of the IBM3206K0424 for counter 1. X'0': Data In X'1': Data Out These bits will determine which kind of mode both counters will operate in. X'0' Stop on overflow X'1' Interrupt on wrap X'2' Event on wrap X'3' Inject active errors on overflow These bits determine which kind of PCI cycle owners to be counted for counter 2. The definitions are the same as bits 7-4. These bits determine what kind of PCI events are to be counted for counter 2. The definitions are the same as bits 3-0. Preliminary 21-20 Data Transfer Width Control - Counter 1 19 Data Direction - Counter 2 18 Data Direction - Counter 1 17-16 Counter Modes 15-12 11-8 Master/Slave Types - Counter 2 Cycles Types - Counter 2 7-4 These bits determine which kind of PCI cycle owners to be counted for counter 1. X'0' All Devices on the PCI bus X'1' All Devices but IBM3206K0424 X'2' IBM3206K0424 only (master or slave) Master/Slave Types - Counter 1 X'3' IBM3206K0424 master X'4' IBM3206K0424 slave (all types) X'5' IBM3206K0424 slave register accesses X'6' IBM3206K0424 slave memory accesses These bits will determine what kind of PCI events are to be counted for counter 1. X'0' Off X'1' All PCI clock cycles X'2' Active PCI bus cycles (frame + irdy + trdy) X'3' PCI Data Xfer Opportunities ((irdy + trdy) & devsel) X'4' PCI Data Xfers (irdy & trdy) X'5' PCI Retries (irdy & no trdy & devsel & stop) X'6' PCI Address Phase (frame & not frame delayed) X'7' PCI Disconnects (irdy & trdy & devsel & stop) 3-0 Cycles Types - Counter 1 The IOP Bus Specific Interface Controller (PCINT) Page 120 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.20: PCINT Perf Counter 1 This register contains PCI performance counter 1. Length Type Address Restrictions 32 bits Read/Write XXXX 0080 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Counter 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Name Counter 1 9 8 7 6 5 4 3 2 1 0 Description See PCINT Perf Counters Control Register on page 119 for information on how this counter will increment. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 121 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.21: PCINT Perf Counter 2 This register contains PCI performance counter 2. Length Type Address Restrictions 32 bits Read/Write XXXX 0084 Can be written or read during configuration cycle, memory cycle when enabled (see PCINT Base Address Control Register on page 111), or an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Counter 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Name Counter 2 9 8 7 6 5 4 3 2 1 0 Description See PCINT Perf Counters Control Register on page 119 for information on how this counter will increment. The IOP Bus Specific Interface Controller (PCINT) Page 122 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.22: PCI Master Options Control This register contains the control register when the IBM3206K0424 is the PCI master. Length Type Address Restrictions 32 bits Read/Write XXXX 008C None Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Disable master detected target abort errors to GPDMA Disable master detected parity errors to GPDMA Disable master detected perr errors to GPDMA Encoded Control for DMA reads Disable devto errors to GPDMA A32SwapWords 1 RqHurryUp VsHurryUp Reserved Arbitration priority 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 Name 9 8 7 6 5 4 3 2 Description Disable devto errors to GPDMA Setting this bit to `1' will disable device timeout errors from stopping a GPDMA transfer. Disable master detected target abort errors to GPDMA Disable master detected perr errors to GPDMA Reserved Disable master detected parity errors to GPDMA Reserved Setting this bit to `1' will disable master detected target abort errors from stopping a GPDMA transfer. Setting this bit to `1' will disable master detected perr errors from stopping a GPDMA transfer. Reserved Setting this bit to `1' will disable master detected parity errors from stopping a GPDMA transfer Reserved pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 123 of 676 Assume32 0 PrHurryUp Rd8Bytes Reserved Reserved 4Byte32 Unused IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description Preliminary 25-24 Encoding of bits: X'0': Let the IBM3206K0424 pick the best memory read command based on the cacheline size bits and the DMA count. Encoded Control for DMA reads X'1': Fix the read DMA command to Memory Read Multiple. X'2': Fix the read DMA command to Memory Read Line. X'3': Fix the read DMA command to Memory Read. Reserved Reserved PCI master will cease using a default round-robin scheme for internal requestor arbitration if these bits are not all '0'. Bits 15-14 are the priority level for GPDMA. Bits 13-12 are the priority level for PCORE. Bits 11-10 are the priority level for RXQUE. Bits 9 - 8 are the priority level for INTST. Valid levels are 3,2,1, and 0. Only 4 levels must be used. PCI master will inform GPDMA to HurryUp if VSTAT is waiting. PCI master will inform GPDMA to HurryUp if RXQUE is waiting. PCI master will inform GPDMA to HurryUp if PCORE is waiting. PCI master will force all byte enables active for reads. PCI master does not use this bit. PCI master will transfer a four-byte DMA as a 32-bit transfer. PCI master will always swap words for any Assume32 transfer. PCI master will not request a 64-bit transfer. 23-16 15-8 Arbitration priority 7 6 5 4 3 2 1 0 VsHurryUp RqHurryUp PrHurryUp Rd8Bytes Unused 4Byte32 A32SwapWords Assume32 The IOP Bus Specific Interface Controller (PCINT) Page 124 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.23: Power Management Program Control This register contains the control register for power management signalling. Length Type Address Restrictions 32 bits Read/Write XXXX 0090 Can be written or read during configuration cycle or memory cycle when enabled (see PCINT Base Address Control Register on page 111), or as an I/O cycle. This register is documented as big endian, but how data is presented on the PCI bus depends on how the controls are set in the PCINT Endian Control Register. Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Turn on Power Management Event (PCI PME#) 0 Set External PME# Input Receiver Polarity Enable PowerState Change Interrupt 3 2 Deasserted Ext_PME# PowerStates Asserted Ext_PME# PowerStates Enable External PME# Input Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-14 Reserved Asserted Ext_PME# PowerStates Deasserted Ext_PME# PowerStates Reserved Set External PME# Input Receiver Polarity Enable External PME# Input Reserved Enable PowerState Change Interrupt Name Reserved 9 8 7 6 5 4 Description These bits reflect what power state the Ext_PME# pin will indicate that it is in when the Ext_PME# is asserted. These bits reflect what power state the Ext_PME# pin will indicate that it is in when the Ext_PME# is de-asserted. Also, these are the default bits read back for the pmi2 powerstates bits 1-0 when Ext_PME# is not enabled. Reserved Setting this bit to '1' will make the chip input called Ext_PME# to be used as a positive active signal. Otherwise it is negative active. Setting this bit to '1' will enable the chip input called Ext_PME# to be used as a source to driver the PM# state. Reserved Setting this bit to '1' will enable a change of power states to cause an interrupt bit to turn on in INTST. 13-12 11-10 9 8 7-3 2 pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 125 of 676 Set PME# Driver Behavior 1 Reserved IBM3206K0424 IBM Processor for Network Resources Bit(s) 1 0 Name Set PME# Driver Behavior Turn on Power Management Event (PCI PME#) Description Setting this bit to '1' will make the PME# driver behave like a push-pull driver. Setting this bit to '0' will make the PME# driver behave like an open-drain. Setting this bit will assert the PCI bus signal PME#. Preliminary The IOP Bus Specific Interface Controller (PCINT) Page 126 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.24: Message Signaled Interrupts-Word 1 This register contains the part of the Message Signaled Interrupts structure. See bit definitions. Length Type Address Restrictions 32 bits Read Only/Read/Write XXXX 00C0 Cannot be written unless by Crisco, or the PCI config space override write bit is on. Power on Reset Value X'0082D005' (Big Endian) Power on Reset Value X'05D08200' (Little Endian) Message Control Next Pointer Capability ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-8 7-0 Name Message Control Next Pointer Capability ID 9 8 7 6 5 4 3 2 1 0 Description See PCI spec revision 2.2 for more details. Bits 31-24 are 0, and bit 23 is 1. Bits 22-20 are the Multiple Message Enable field, and bits 19-17 are the Multiple Message Capable field. Bit 16 is MSI Enable. Only bits 16, 20, 21, and 22 are writable. Pointer to the next item in the capabilities list. Set to 05h to identify this function as Message Signaled Interrupt capable. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 127 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.25: Message Signaled Interrupts-Word 2 This register contains the part of the Message Signaled Interrupts structure. See bit definitions. Length Type Address Restrictions Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Message Address 32 bits Read/Write XXXX 00C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Name Message Address 9 8 7 6 5 4 3 2 1 0 Description See PCI spec revision 2.2 for more details. Bits 31-24 are `0', and bit 23 is `1'. Bits 22-20 are the Multiple Message Enable field, and bits 19-17 are the Multiple Message Capable field. Bit 16 is MSI Enable. Only bits 16, 20, 21, and 22 are writable. The IOP Bus Specific Interface Controller (PCINT) Page 128 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.26: Message Signaled Interrupts-Word 3 This register contains the part of the Message Signaled Interrupts structure. See bit definitions. Length Type Address Restrictions Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Message Upper Address 32 bits Read/Write XXXX 00C3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Name Message Upper Address 9 8 7 6 5 4 3 2 1 0 Description See PCI spec revision 2.2 for more details. Bits 31-0 hold the upper 32 bits of system address for the MSI memory write DMA transaction. pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 129 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.27: Message Signaled Interrupts-Word 4 This register contains the part of the Message Signaled Interrupts structure. See bit definitions. Length Type Address Restrictions Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Message Data 16 bits Read/Write XXXX 00CC 15 14 13 12 11 10 Bit(s) 15-0 9 Name 8 7 6 5 4 3 2 1 0 Description Message Data See PCI spec revision 2.2 for more details. Bits 15-0 hold the data for the MSI memory write DMA transaction. The IOP Bus Specific Interface Controller (PCINT) Page 130 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.28: Power Management Interface-Word 1 This register contains the part of the Power Management Interface structure. See bit definitions. Length Type Address Restrictions 32 bits Read Only XXXX 00D0 Cannot be written unless by Crisco, or the PCI config space override write bit is on. Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Power Management Capabilites Next Pointer Capability ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 0 Description 31-16 See PCI Bus Power Management Interface Spec, Version 1.0 for more details. Bits 31-27 are for PME_Support. Bit 26 is for D2_Support. Bit 25 is for D1_Support. Bits 24-22 are Power Management Capabilities reserved. Bit 21 is the Device Specific Initialization bit. Bit 20 is reserved. Bit 19 is for PME Clock. Bits 18-16 are version compliance level. Next Pointer Capability ID Pointer to the next item in the capabilities list. Set to 01h to identify this function as PCI Bus Power Management Interface. 15-8 7-0 pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 131 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.29: Power Management Interface-Word 2 This register contains the part of the Power Management Interface structure. See bit definitions. Length Type Address Restrictions Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Power Management Capabilities 16 bits Read Only/Read Clear/Read Write XXXX 00D4 15 14 13 12 11 10 Bit(s) 15-0 9 Name 8 7 6 5 4 3 2 1 0 Description See PCI Bus Power Management Interface Spec Version 1.0 for more details. Bit 15 is for Power Management Capabilities PME_Status. Bit 14-13 are not used. Bits 12-9 are not used. Bit 8 is PME_En. Bits 7-2 are reserved. Bit 1-0 are the PowerState. The IOP Bus Specific Interface Controller (PCINT) Page 132 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 1.30: Vital Product Data Interface-Word 1 This register contains the part of the Vital Product Data Interface structure. See bit definitions. Length Type Address Restrictions 32 bits Read Only/Read Write XXXX 00D8 Cannot be written unless by Crisco, or if the PCI config space override write bit is on. Power on Reset Value X'00000003' (Big Endian) Power on Reset Value X'00000000' (Little Endian) Flag Bit VDP Address Next Pointer Capability ID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 0 Description See PCI Spec Revision 2.2, Appendix 1 for more details. Read/Write Flag bit. For VPD reads, this bit is set to '0' and the VPD Address is set. When the hardware sets the bit to '1', valid VPD data can be read. For VPD writes, the VPD Data is written first. Then this bit is set to '1', along with the VPD Address. The write is active until the hardware resets this bit. See PCI Spec Revision 2.2, Appendix 1 for more details. VPD Address. Pointer to the next item in the capabilities list. Set to 03h to identify this function as Vital Product Data Interface. 31 Flag Bit 30-16 15-8 7-0 VDP Address Next Pointer Capability ID pnr25.chapt04.01 August 14, 2000 The IOP Bus Specific Interface Controller (PCINT) Page 133 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 1.31: Vital Product Data Interface-Word 2 This register contains the part of the Vital Product Data Interface structure. See bit definitions. Length Type Address Restrictions Power on Reset Value X'00000000' (Big Endian) Power on Reset Value X'00000000' (Little Endian) VPD Data 32 bits Read/Write XXXX 00DC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 VPD Data Name 9 8 7 6 5 4 3 2 1 0 Description See PCI Spec Revision 2.2, Appendix 1 for more details. Four bytes of data are always read or written through this data field. The IOP Bus Specific Interface Controller (PCINT) Page 134 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 2: Interrupt and Status/Control (INTST) This entity contains the masking registers that choose which interrupt/status source will be gated onto one of the two available interrupt I/O pins. A new delayed interrupt function has been added. This function allows IBM3206K0424 status registers to be read and placed in system memory before the interrupt signal is raised. For details, see DMA QUEUES (DMAQS) on page 154. A bus timer function is provided in this entity that times a single bus access to make sure that the cycle is terminated before the system timer times out. This allows the user code an opportunity to recover from the error as opposed to the subsystem common code. Below is a summary of this entity's functions: * Interrupt Prioritized Status Registers * Interrupt Source Register * Interrupt Enable Registers * Bus timer function * Control Processor error register with enable register 2.1: INTST Interrupt 1 Prioritized Status Used to help quickly parse which interrupting entity of the IBM3206K0424 is active. Length Type Address Restrictions Power on Reset value 32 bits Read Only XXXX 0400 None X'00000000' Prioritized Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function 9 8 7 6 5 4 3 2 1 0 Description Reading this register will give a prioritized value of the bits in the INTST Interrupt Source and INTST Enable for Interrupt 1 (MINTA) registers ANDed together, returning a value that will be a hex number equal to bit number n + 1. For example, if bit 31 is on, X'20' will be read back. 31-0 Prioritized Status pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 135 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.2: INTST Interrupt 2 Prioritized Status Used to help quickly parse which interrupting entity of the IBM3206K0424 is active. Length Type Address Restrictions Power on Reset value 32 bits Read Only XXXX 0404 None X'00000000' Prioritized Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function 9 8 7 6 5 4 3 2 1 0 Description Reading this register will give a prioritized value of the bits in the INTST Interrupt Source and INTST Enable for Interrupt 1 (MINT2) registers ANDed together, returning a value that will be a hex number equal to bit number n + 1. For example, if bit 31 is on, X'20' will be read back. 31-0 Prioritized Status Interrupt and Status/Control (INTST) Page 136 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.3: INTST Control Register This register is used to control various IBM3206K0424 functions. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value Delayed Interrupts - Route interrupt 2 to interrupt 1 18 bits Clear/Set XXXX 0408 and 0C None X'0010200' Delayed Interrupts - Assume a 64bit PCI target Delayed Interrupts - Assume a 32bit PCI target Delayed Interrupts - returned status word type Enable the PLL output (hardware test only) 1 18 17 16 15 14 13 12 11 10 Bit(s) 18 17 16 15 14 13 Name 9 8 7 6 5 4 3 2 Disable the ENSTATE clocks output pins 0 Description Delayed Interrupts - Swap words control Delayed Interrupts - Enable interrupt 1 Delayed Interrupts - Enable interrupt 2 Master Chip Enable for Transmitting Disable the ENSTATE output pins Master Chip Enable for Receiving Delayed Interrupts - Endian Bit Delayed Interrupts - Assume a 64bit PCI target Delayed Interrupts - Assume a 32bit PCI target Delayed Interrupts - Swap words control Delayed Interrupts - Enable interrupt 1 Delayed Interrupts - Enable interrupt 2 Delayed Interrupts - Endian Bit Delayed Interrupts - Route interrupt 2 to interrupt 1 Delayed Interrupts - returned status word type This bit set will help the mastering logic determine how to best move data to a 64-bit PCI target. This bit is set when software has system knowledge of its targets. This bit set will help the mastering logic determine how to best move data to a 32-bit PCI target. This bit is set when software has system knowledge of its targets. This bit determines the word order of the status word dma transfer for delayed ints. The default value of '1' is to swap the words. A value of '0' will not swap them. When set, the delayed int mechanism for int 1 is enabled. When set, the delayed int mechanism for int 2 is enabled. This bit determines the endian of the status word DMA transfer for delayed ints. When this bit is set, the endian is little. The default of `0' is big endian. When set, the int 2 signal is routed and raised as int 1. This bit allows both sets of int masks in intst to be used, while still using only a single hardware int. When set, both delayed int's should be enabled if they are being used. When this bit is set, the INTST Interrupt Source word will be anded with the corresponding enable register. Otherwise, the INTST Interrupt Source register alone will be returned. 12 11 pnr25.chapt04.01 August 14, 2000 Treat MINT2 as push-pull Zeros on Data Parity Master Chip Enable Reserved PI Bytes Interrupt and Status/Control (INTST) Page 137 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description These bits are encoded to tell how many bytes long the AAL 5 CPI field is. The following are the encodings: '00' CPI field is zero bytes long. In this case, the two bytes containing the CPI field and the AAL5 user-to-user byte are copied into the packet header. See the definition of the packet header for the locations. '01' CPI field is one byte long and is always '0'. In this case, the one byte AAL5 user-to-user byte is copied into the packet header. '10' CPI field is two bytes long and is always '0'. '11' Treated the same as B'00' Reserved When this bit is set to '0', the chip i/o ENSTATES will be driven with the output of the internally muxed debug states. When set to '1', these outputs will be quiet. When this bit is set to '1', various state machines in the receive part of the chip will be enabled. When this bit is set to '1', various state machines in the transmit part of the chip will be enabled. When this bit is set to '1', various state machines in the chip will be enabled. This must be set to '1' transmit or receive anything. When this bit is set to '1', zeros will be forced on the data bus parity line(s) during a slave read data phase or a master address phase or a master write data phase. When this bit is set to '1', the chip I/O MINT2 will be driven active high as well as low, like a push-pull driver. This is for use as a specific sideband application, not as a general shared open-drain interrupt line. When this bit is set to '1', the chip i/o PPLLOUT will be driven with the output of the internal PLL. When set to '0', this output will be quiet. Preliminary 10-9 PI Bytes 8 7 6 5 4 3 Reserved Disable the ENSTATE output pins Master Chip Enable for Receiving Master Chip Enable for Transmitting Master Chip Enable Zeros on Data Parity 2 Treat MINT2 as push-pull Enable the PLL output (hardware test only) 1 0 Disable the ENSTATE clocks out- When this bit is set to '0', the chip i/o PINTCLK and PDBLCLK will be driven with the put pins output of the internal clock tree. When set to '1', these outputs will be quiet. Interrupt and Status/Control (INTST) Page 138 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.4: INTST Interrupt Source This register indicates the source(s) of the interrupt(s) pending. It can also be used as a status register when the bits are enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Note that bits in this register always reflect the state of the source register bit: Writing a value will have no effect. Reserved bits will not take on the written value. The delay of running through a latch has been removed. For the delayed interrupts feature, writing this register at the end of an interrupt handling routine will guarantee that interrupt1 and interrupt2 (if enabled) will pulse off, allowing the logic to get ready for the next interrupt DMA. Length Type Address Restrictions Power on Reset value COMET or PAKIT 32 bits Read Only XXXX 0410 and 14 None X'00000000' Spurious Interrupt 0 INTST GP Timer INTST GP Timer External INTA RXQUE 2 RXQUE 4 RXQUE 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2 GPDMA DMAQS CHKSM REASM PCORE PCORE BCACH POOLS CSKED SEGBF VIMEM LINKC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 INTST PCORE COMET or PAKIT INTST GP Timer BCACH RXQUE 2 Reserved RXQUE 4 GPDMA DMAQS REASM Reserved RXQUE 1 Reserved Reserved Name 9 8 7 6 5 4 3 Description A Control Processor related condition has occurred. A read of the INTST CPB Status and INTST CPB Status Enable must be done for more information. See INTST CPB Status on page 142 and INTST CPB Status Enable on page 144. The PCORE entity has hardware interrupts that need handling. The COMET or PAKIT entities have interrupts that need handling. The INTST General Purpose Timer Counter has reach the INTST General Purpose Timer Compare value and caused an interrupt. The BCACH entity has interrupts that need handling. The RXQUE entity has interrupts that need handling. Reserved The RXQUE entity has interrupts that need handling. The GPDMA entity has interrupts that need handling. The DMAQS entity has interrupts that need handling. The REASM entity has interrupts that need handling. Reserved The RXQUE entity has interrupts that need handling. Reserved Reserved pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 139 of 676 PBIST 1 INTST IBM3206K0424 IBM Processor for Network Resources Bit(s) 16 15 14 13 Reserved. POOLS PCORE CHKSM Name Reserved. The POOLS entity has interrupts that need handling. The PCORE entity has User Defined interrupts that need handling. The CHKSM entity has interrupts that need handling. This bit will be set when the IBM3206K0424 detects that MINTA is low and, conditionally, when the same bit in INTST Enable for PCORE Normal Interrupt or INTST Enable for PCORE Critical Interrupt is set. This bit is for use by the PCORE entity, and it is recommended that interrupts directed out which drive output (MINTA) be disabled. The CSKED entity has interrupts that need handling. Reserved The SEGBF entity has interrupts that need handling. Reserved The LINKC entity has interrupts that need handling. Reserved The INTST General Purpose Timer Counter has reached the INTST General Purpose Timer Compare value and caused an interrupt. Reserved The VIMEM entity has interrupts that need handling. Reserved This bit is set when the PBIST entity did not indicate that it was done. It is also not clearable. Under normal conditions, this bit should never be set. However, if one of the other bits in this register turns on, then off, a spurious interrupt condition will occur. The manual vector passed to the processor will point to this bit being on. Description Preliminary 12 External INTA 11 10 9 8 7 6 5 4 3 2 1 CSKED Reserved SEGBF Reserved LINKC Reserved INTST GP Timer Reserved VIMEM Reserved PBIST 0 Spurious Interrupt 2.5: INTST Enable for Interrupt 1 (MINTA) This register serves as an enable for interrupt 1. See the INTST Interrupt Source register on page 139 for the bitwise description that the corresponding bit in this register will enable. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 32 bits Clear/Set XXXX 0418 and 1C None X'00000000' Interrupt and Status/Control (INTST) Page 140 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.6: INTST Enable for Interrupt 2 (MINT2) This register serves as a enable for interrupt 2. See the INTST Interrupt Source Register on page 139 for the bitwise description that the corresponding bit in this register will enable. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 32 bits Clear/Set XXXX 0420 and 24 None X'00000000' 2.7: INTST Interrupt Source without Enables This register is used to help quickly parse which interrupting bit of INTST Interrupt Source is active. It does not matter what state the Enable registers are set to because the value returned does not depend on them. Length Type: Address Restrictions Power on Reset value 32 bits Read Only XXXX 0428 None X'00000000' Prioritized Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Function Prioritized Status 9 8 7 6 5 4 3 2 1 0 Description Reading this register gives a prioritized value of the bits in the INTST Interrupt Source, returning a value that is a hex number equal to bit number n + 1. For example, if bit 31 is on, X'20' will be read back. pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 141 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.8: INTST CPB Status This register holds the status bits for errors on the Control Processor bus. These bits, when disabled, will set a bit in the INTST Interrupt Source register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value Internal DMA Masters signaled error indication 24 bits Clear/Set XXXX 0430 and 34 None X'00000' Target Abort: Register Access Retry Timeout Target Abort: Memory Access Retry Timeout Target Detected PCI 64 bit Data Parity Error Target Disconnect or Retry: End of Memory Master Termination: Target Abort Received Master Termination: Master-initiated Abort Target Disconnect: Memory Addressing Target Detected PCI Data Parity Error Target Abort: Slave Access Timeout Target Abort: Address Parity Error Master PCI Parity Error Detected ARBIT Detected Memory Errors Master Detected Perr Active Power Mgmt State Change Performance Counter 2 Performance Counter 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 23-20 Function Internal DMA Masters signaled error indication Power Mgmt State Change Target Abort: Register Access Retry Timeout 9 8 7 6 5 4 3 2 Description The PCINT entity will set these bits when it signals a DMA error indication to one of the internal requesting masters. Bit 23 is GPDMA, bit 22 is PCORE, bit 21 is RXQUE, and bit 20 is INTST. This bit is set when the conditions in PCINT are met to trigger a Power Management State change. This bit is set when this slave does more retry cycles than the specified amount in the PCINT Count Timeout Register during a register access. 19 18 17 16 Target Abort: Slave Access Tim- This bit is set when this slave does not access the IBM3206K0424 in the specified amount eout in the PCINT Count Timeout Register. PCI timing changed The PCI bus clock has changed range. The IBM3206K0424 should be reset and re-initialized. 15 14 13 12 This bit is set when error conditions detected by ARBIT are enabled. Note: This bit is a ARBIT Detected Memory Errors reflection of the arbitrator status bits and does not need to be reset if the arbitrator condition has been reset. Reserved Reserved Master PCI Parity Error Detected Reserved Reserved This bit is set when a PCI bus data parity error is detected in master mode. Interrupt and Status/Control (INTST) Illegal Register Access 0 PCI timing changed Reserved Reserved Page 142 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 11 10 9 8 7 6 5 4 Function Master Detected Perr Active Master Termination: Target Abort Received IBM Processor for Network Resources Description This bit is set when a target has driven PERR. This bit is set when in master mode and the transfer is aborted by the target. Master Termination: Master-initiThis bit is set when in master mode and the transfer is aborted by this master. ated Abort Target Detected PCI 64 Bit Data This bit is set when a PCI data parity error is detected in 64 bit target mode (the upper Parity Error DWORD has the data parity error). Target Disconnect: Memory Addressing This is set when a memory access is occurring and bits 0 and 1 of the address are not '0'. Target Detected PCI Data Parity This bit is set when a PCI data parity error is detected in target mode. Error Target Abort: Memory Access Retry Timeout Target Abort: Address Parity Error Target Disconnect or Retry: Wrap of 2 GB internal address slave counter Performance Counter 2 Performance Counter 1 Illegal Register Access This bit is set when this slave does more retry cycles than the specified amount in the PCINT Count Timeout Register during a memory access. This bit is set when an address parity error is detected. This bit is set when the slave address counter is its maximum counter value will indicate a termination condition on the PCI bus. This is primarily a debug bit and can turn on during normal operation. It most likely will be useful when the IBM3206K0424 slave mode is configured in 64-bit addressing mode. The PCINT Performance Counter 2 has overflowed. The PCINT Performance Counter 1 has overflowed. This bit is set when an IBM3206K0424 register is being accessed by fewer than four bytes at a time. This is not true for configuration registers during a configuration cycle. 3 2 1 0 pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 143 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.9: INTST CPB Status Enable This register serves as an enable for the INTST CPB Status register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See the INTST CPB Status on page 142 for the bitwise description that corresponding bit in this register will enable. This enable will initialize to the disabled state. Length Type Address Restrictions Power on Reset value 19 bits Clear/Set XXXX 0438 and 3C None X'00000' 2.10: INTST IBM3206K0424 Halt Enable This register serves as an enable for the INTST CPB Status register and gates which errors will reset bit 4 (Master chip enable), bit 5 (Master chip enable for Transmitting), and bit 6 (Master chip enable for Receiving), all in the INTST Control Register register. This allows selected bits to disable the IBM3206K0424, especially in the case of severe hardware detected errors. See the INTST CPB Status on page 142 for the bitwise description that corresponding bit in this register will enable. This enable will initialize to the disabled state. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 19 bits Clear/Set XXXX 0440 and 44 None X'0009F71' 2.11: INTST CPB Capture Enable This register serves as an enable for the INTST CPB Status that will determine on which error type the INTST CPB Captured Address register will be updated. See the INTST CPB Status on page 142 for the bitwise description that corresponding bit in this register will enable. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 19 bits Clear/Set XXXX 0450 and 54 None X'00069F71' Interrupt and Status/Control (INTST) Page 144 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.12: INTST CPB Captured Address This information can be used to attempt a retry in the exception handling microcode. This register holds the value of the IBM3206K0424 register address on the PCI during a bus error condition. This only latches values from sources that are enabled in the INTST CPB Capture Enable register. Length Type Address Restrictions Power on Reset value 32 bits Read/Write XXXX 0458 None X'00000001' Invalid Capture 0 Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-2 1 0 Function Register Address Reserved Invalid Capture 9 8 7 6 5 4 3 2 Description Captured IBM3206K0424 register address. Reserved. When this bit is reset to `0', a valid capture has been made. 2.13: INTST General Purpose Timer Pre-scaler This is the pre-scaler for the INTST General Purpose Timer Compare.This register will hold the value of the pre-scale count. The default value is 1 tick every 10.02uS, assuming a 33MHz or 66MHz PCI Bus clock, producing a 66MHz system clock (count is system clock). The pre-scale count value is n-1, where n is the desired increment count. Owing to a physical design problem, the function of this register was lost. It should be set to a non-zero value, so that the INTST General Purpose Timer Counter can be used with a prescale of only the default clock (one tick every 30ns, assuming a 33-MHz system clock). Length Type Address Restrictions Power on Reset value 32 bits Read/Write XXXX 0464 None X'0000029B' pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 145 of 676 Reserved 1 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.14: INTST General Purpose Timer Compare This is the compare value for the general purpose timer. This register holds the value of the data that is compared to the count value in the INTST General Purpose Timer Counter, setting the INTST General Purpose Timer Status bits. See INTST General Purpose Timer Mode Control on page 148 for details on the operation of this register. Length Type Address Restrictions Power on Reset value 32 bits Read/Write XXXX 0468 None X'0800 0000' 2.15: INTST General Purpose Timer Counter This is the general purpose timer counter. This register holds the value of the counter. It always counts up. See INTST General Purpose Timer Mode Control on page 148 for details on operation of this register. Length Type Address Restrictions Power on Reset value 32 bits Read/Write XXXX 046C None X'0000 0000' Interrupt and Status/Control (INTST) Page 146 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.16: INTST General Purpose Timer Status This is the status of the general purpose timer counter. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value Timer Wrapped Timer Interrupt 2 bits Clear/Set XXXX 0470 and 74 None X'0' 1 0 Bit(s) 1 Function Timer Wrapped Description This bit is set when the INTST General Purpose Timer Counter wraps around to a '0' count value. See INTST General Purpose Timer Mode Control on page 148 for details on how this bit is set. For mode 0: This bit is set when the INTST General Purpose Timer Counter matches the value in the INTST General Purpose Timer Compare register. The comparing condition must be changed (write INTST General Purpose Timer Counter or INTST General Purpose Timer Compare) before resetting this bit, or the bit will set again. 0 Timer Interrupt pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 147 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.17: INTST General Purpose Timer Mode Control This register controls the operating modes of the general purpose timer counter. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value Timer Modes 3 bits Clear/Set XXXX 0478 and 7C None X'4' 2 1 0 Description These bits are encoded to provide eight different timer operation modes. Encoding is as follows: Mode 0 The INTST General Purpose Timer Counter is a free-running up-counter and sets bit 0 of INTST General Purpose Timer Status when equal to INTST General Purpose Timer Compare. Mode 1 The INTST General Purpose Timer Counter is a free-running up-counter and sets bit 0 of INTST General Purpose Timer Status when equal to INTST General Purpose Timer Compare. A write to INTST General Purpose Timer Compare will reset bit 0 of INTST General Purpose Timer Status. Mode 2 The INTST General Purpose Timer Counter is a free-running up-counter and sets bit 0 of INTST General Purpose Timer Status when equal to or greater than INTST General Purpose Timer Compare. A write to INTST General Purpose Timer Compare will reset bit 0 of INTST General Purpose Timer Status. Mode 3 The INTST General Purpose Timer Counter is a up-counter and sets bit 0 of INTST General Purpose Timer Status when equal to or greater than the INTST General Purpose Timer Compare. The INTST General Purpose Timer Counter is also reset when a comparison is made. A write to INTST General Purpose Timer Compare will reset bit 0 of INTST General Purpose Timer Status and INTST General Purpose Timer Counter. Mode 4 The INTST General Purpose Timer Counter is disabled and no status bits will be set. Modes 5-7 Reserved Bit(s) 2-0 Interrupt and Status/Control (INTST) Page 148 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.18: INTST Enable for PCORE Normal Interrupt This register serves as an enable for the PCORE normal interrupt input. See INTST Interrupt Source on page 139 for the bitwise description that the corresponding bit in this register will enable. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 32 bits Clear/Set XXXX 0480 and 84 None X'00000000' 2.19: INTST Enable for PCORE Critical Interrupt This register serves as an enable for the PCORE critical interrupt input. See INTST Interrupt Source on page 139 for the bitwise description that the corresponding bit in this register will enable. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Reset value 32 bits Clear/Set XXXX 0488 and 8C None X'00000000' pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 149 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.20: INTST Debug States Control This register serves as the control for external debug states. Length Type Address Restrictions Power on Reset value Entity State Mux Control 4 (Hardware debug) 32 bits Read/Write XXXX 0490 None X'38030201' Entity State Mux Control 3 (Hardware debug) Entity State Mux Control 2 (Hardware debug) Entity State Mux Control 1 (Hardware debug) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 23-16 15-8 Function Entity State Mux Control 4 (Hardware debug) Entity State Mux Control 3 (Hardware debug) Entity State Mux Control 2 (Hardware debug) 9 8 7 6 5 4 3 2 1 0 Description Selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (63-48). Selection encoding is the same as multiplexer 1 control. Selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (7 -32). Selection encoding is the same as multiplexer 1 control. Selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (31-16). Interrupt and Status/Control (INTST) Page 150 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 7-0 Function Entity State Mux Control 1 (Hardware debug) IBM Processor for Network Resources Description Selection of these bits allows internal state machines, counters, etc. to show up on chip outputs enstate (15-0) which are multiplexed over ad64 (15-0). X'00' Disabled (no transition on outputs). X'20' Select POOLS 95-80 states. X'01' Select CRSET 15-0 states. X'21' Select POOLS 111-96 states. X'02' Select NPBUS 15-0 states. X'22' Select POOLS 127-112 states. X'03' Select PCINT 15-0 states. X'23' Select VIMEM 15-0 states. X'04' Select PCINT 31-16 states. X'24' Select VIMEM 31-16 states. X'05' Select COMET 15-0 states. X'25' Select VIMEM 47-32 states. X'06' Select COMET 31-16 states. X'26' Select ARBIT 15-0 states. X'07' Select PAKIT 15-0 states. X'27' Select ARBIT 31-16 states. X'08' Select PAKIT 31-16 states. X'28' Select ARBIT 47-32 states. X'09' Select RXQUE 15-0 states. X'29' Select ARBIT 63-48 states. X'0A' Select RXQUE 31-16 states. X'2A' Select PCORE 15-0 states. X'0B' Select RAALL 15-0 states. X'2B' Select PCORE 31-16 states. X'0C' Select RAALL 31-16 states. X'2C' Select PCORE 47-32 states. X'0D' Select RAALL 47-32 states. X'2D' Select PCORE 63-48 states. X'0E' Select RAALL 63-48 states. X'2E' Select PCORE 79-64 states. X'0F' Select REASM 15-0 states. X'2F' Select PCORE 95-80 states. X'10' Select LINKC 15-0 states. X'30' Select PCORE 111-96 states. X'11' Select SEGBF 15-0 states. X'31' Select PCORE 127-112 states. X'12' Select SEGBF 31-16 states. X'32' Select DMAQS 15-0 states. X'13' Select SEGBF 47-32 states. X'33' Select DMAQS 31-16 states. X'14' Select SEGBF 63-48 states. X'34' Select DMAQS 47-32 states. X'15' Select CSKED 15-0 states. X'35' Select DMAQS 63-48 states. X'16' Select CHKSM 15-0 states. X'36' Select SCLCK 15-0 states. X'17' Select CHKSM 31-16 states. X'37' Select SCLCK 31-16 states. X'18' Select GPDMA 15-0 states. X'38' Select SCLCK 39-32 states. X'19' Select BCACH 15-0 states. X'39'-X'FF'Reserved (do not toggle as well) X'1A' Select BCACH 31-16 states. X'1B' Select POOLS 15-0 states. X'1C' Select POOLS 31-16 states. X'1D' Select POOLS 47-32 states. X'1E' Select POOLS 63-48 states. X'1F' Select POOLS 79-64 states. pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 151 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 2.21: INTST Delayed Interrupts DMA System Address 1 This register serves as the Delayed Interrupts DMA System Address. This register holds the value of the system DMA address to which the delay interrupt status data will be moved. Length Type Address Restrictions 64 bits Read/Write XXXX 0498 and 9C None Power on Reset Value X'00000000' 2.22: INTST Delayed Interrupts DMA System Address 2 This register serves as the Delayed Interrupts DMA System Address. This register holds the value of the system DMA address to which the delay interrupt status data will be moved. Length Type Address Restrictions 64 bits Read/Write XXXX 04a0 and a4 None Power on Reset Value X'00000000' 2.23: Current PCI Master Address Counter for Debug This register holds the current PCI Master address counter value. This register holds the value of the PCI Master DMA address. The function of this register is primarily for debug when a severe error occurs that stops the DMA engine from running. Length Type Address Restrictions 64 bits Read Only XXXX 04a8 and ac None Power on Reset Value X'00000000' Interrupt and Status/Control (INTST) Page 152 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 2.24: External Entity States Read This register will get a snapshot value of the enstates pin I/O. This register will return whatever is on the output of the enstates mux output. It is strictly for debug and a convenient way to look at the current state of IBM3206K0424 internal logic. It is controlled by INTST Debug States Control. Length Type Address Restrictions 64 bits Read Only XXXX 04b0 and b4 None Power on Reset Value X'xxxxxxxx' pnr25.chapt04.01 August 14, 2000 Interrupt and Status/Control (INTST) Page 153 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 3: DMA QUEUES (DMAQS) DMAQS provides the interface to the IBM3206K0424's DMA master capability (described in General Purpose DMA (GPDMA) on page 175). It provides three DMA queues that hold DMA descriptor chains that are executed in a multiplexed fashion. Together with GPDMA, a very powerful interface is provided to software to complete complex tasks including TCP/IP checksumming for transmit and receive packets. The following sections describe the features of DMAQS, how to set up DMAQS, and some troubleshooting tips. DMA Descriptors DMA descriptors can reside in either PCI/system memory space or the IBM3206K0424 memory space. Certain types of descriptors, called cut-through DMA descriptors, must be located in the IBM3206K0424 memory space. DMA descriptors that are located in the IBM3206K0424 memory space are more efficient to process because they do not need to be moved across the PCI bus. However, it is more costly for software to update across the bus. The best option is to mix descriptors in both locations. DMA descriptors that are infrequently changed should reside in the IBM3206K0424 memory, while dynamic descriptors should be placed in system memory. Descriptors located in the IBM3206K0424 memory space must fall in a definable address range. See DMAQS Local Descriptor Range Registers on page 173. DMA Descriptor Layout Flags/Byte Count One Descriptor Source Address Destination Address Blocks of up to 63 descriptors can be queued with one enqueue primitive. High Order System Address Flags/Byte Count Source Address Note: The High Order System Address field (word 4) is not present when the chip is in 32-bit addressing mode. Destination Address High Order System Address 32 bits DMA QUEUES (DMAQS) Page 154 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources DMA Types and Options The DMA descriptor is very versatile and can perform many actions. The following list shows some examples and possible flags to use. Other combinations are possible: see GPDMA Transfer Count and Flag Register on page 179. DMA Types and Flags Hex Flags 3000 1000 0800 0400 0100 0080 0001 0010 0012 0013 0017 0002 0020 0021 0031 0050 0062 0008 0004 000C 0040 2200 1200 DMA Operation Clear the current TCP checksum and include this DMA in the TCP checksum. Include this DMA in the TCP checksum and use previous checksum as seed. This DMA transfer is done in Little Endian mode. Upon completion of this DMA descriptor, the destination address from this descriptor is used as a packet address to be enqueued to transmit. Queue a DMA complete event when DMA is complete. Status in the status register is inhibited for this descriptor. This can be useful if ints/polling are being used to track when a particular DMA is complete. Move system memory to the IBM3206K0424 memory. Move the IBM3206K0424 memory to system memory. Move a single IBM3206K0424 register to system memory. Move IBM3206K0424 memory to system memory and free buffer. Upon DMA completion, the source address is used to free the IBM3206K0424 buffer. Auto-increment source address and move IBM3206K0424 memory to system memory and free buffer. Upon DMA completion, the source address is used to free the IBM3206K0424 buffer. Move single IBM3206K0424 register to IBM3206K0424 memory. Move IBM3206K0424 Memory to single IBM3206K0424 register. Move system Memory to single IBM3206K0424 register. Move system memory to a new IBM3206K0424 buffer. A get buffer operation will be done to fill in the destination address using the low four bits of the destination address as a get pool ID. Move something to source address of next descriptor. Allows indirection. Move single IBM3206K0424 register to destination address of the next descriptor. Allows a get buffer operation in descriptor chain. See the get buff flag for a better option. Use source address as immediate data. Allows up to four bytes of immediate data in the DMA descriptor. Auto-increment the source address. The source address picks up where it left off from the previous DMA descriptor. Auto-increment the source address and use as immediate data. One use is to free a packet after DMAing data. See the free buff flags for better option. Auto-increment the destination address. The destination address picks up where it left off from the previous DMA descriptor. One use is transmit scatter into an IBM3206K0424 virtual buffer. Hold the destination address. Useful for freeing a scatter DMA list, or doing a repetitive write to an IBM3206K0424 register. Hold the source address. Useful for doing a repetitive read from an IBM3206K0424 register. Note: These are not the only options. Some of the above can be ORed together also. Using the above, you can efficiently do TCP checksumming, place user events in receive queues, do register reads/writes, free buffers, and get buffers. pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 155 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Descriptor Based DMAs This is the recommended approach to processing DMAs. A single descriptor or a descriptor chain is built that describes the actions to take. The descriptor is then enqueued to the proper DMA Queue. The number of the descriptor in the DMA chain is placed in the lower six bits of the descriptor address as it is enqueued. Register Based DMAs While register based DMAs can be enabled and used, they are not recommended because they are not as efficient and they do not leave a debug trail as the descriptors do in the DMA queue. These should not be used concurrently with descriptor-based DMAs for a particular queue, but register-based and descriptor-based DMAs can be used on different queues. One possible use for register-based DMAs is doing DMAs from the core. Polling, Interrupts, or Events There are several choices for handling DMA completion. First, the status register can be polled. While not very efficient, it is the easiest option. Second, you can use interrupts to tell when a DMA is done. Again, not very efficient. However, interrupts should be used to tell when a DMA error has occurred. One way to deal with DMA completes is to use the RXQUE event mechanism. By generating events, the user can dump in DMA descriptor and clean up at a later time when it is convenient. The user can use the automatic DMA events using the queue on DMA complete flag, or the user can place a user event on an arbitrary queue by writing a DMA descriptor that does an explicit RXQUE enqueue with user data. Error Detection and Recovery Ideally, there should not be any errors. Errors are usually user errors in the DMA descriptor which need to be fixed and are not recoverable. Errors on the PCI bus (that is, parity) should not occur in a normal working system, and typically you do not want to recover them. However, if recovery is desired, the current DMA must be recovered in GPDMA. Upon successful completion of the recovered DMA, DMAQS will resume operation. DMA/Queue Scheduling Options There are three DMA queues. Queue 0 is higher priority than the other two. This high priority queue is always scheduled to go if the current descriptor is ready. The other two queues (Q1 and Q2) are of equal priority and are scheduled in a round robin fashion when the descriptor is ready. This is meant to provide a transmit DMA queue, receive DMA queue, and a high priority DMA queue. However, these queues can be used for any purpose by setting the routing registers properly. The queues can be arbitrated after each DMA request length operation, after complete DMA descriptor chains complete, or after a single DMA descriptor in a chain completes. The queues can also be placed in true round robin mode, where all three queues have equal priority. Address Size DMAQS can be operated with either 32- or 64-bit System Addresses. See PCINT 64-bit Control Register. All DMAQS address registers are 64 bits wide. In 32-bit addressing mode, the high order portion of address registers are initialized at reset to `0', and cannot be modified. In 32 bit addressing mode, word four of the DMA Buffer Descriptor is ignored. DMA QUEUES (DMAQS) pnr25.chapt04.01 August 14, 2000 Page 156 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources Data Width DMAQS recognizes 64 bit writes to 64 bit internal registers. DMAQS internal 64-bit registers may be written either as a 64-bit entity, or by two 32-bit writes. All DMAQS registers are memory mapped on a 64-bit boundary (address bits 2:0 = 0). When in 64-bit addressing mode, an address register is updated with 32 bit writes (atomicity of update cannot be guaranteed). The user should use semaphores to assure the integrity of the operation. Initialization of DMAQS DMAQS is very simple to set up by following these steps: 1. Set up each of the three DMA queues. To do this, you need to know the size of each queue (see DMAQS Upper Bound Registers on page 159 for choices). Given this information, the DMA queue is set up with two register writes in diagnostic mode (see DMAQS Control Register on page 164). dmaqs->lowerBound[q] = baseAddress // should be aligned with size of queue dmaqs->upperBound[q] = encodedSize; // et encoded size of dma queue or dmags->bounds[q] = baseAddress + encodedSize; // if 64 bit data is enabled The data structure for the DMA queue is now set up. 2. Set up the queue thresholds if they are being used: dmaqs->threshold[q]=threshold //setthresholdsizetobeinterrupted on //may also need to set int mask 3. Set up the local DMA descriptor range if local descriptors are being used: dmaqs->localDescriptorLowerBound = localDescriptorBase // set base addr of local desc in IBM3206K0424 memory dmaqs->localDescriptorUpperBound = localDescriptorEnd; // set ending addr of local desc in IBM3206K0424 memory 4. Set up any options that are being used in the DMAQS Control Register: dmaqs->control[set] = ENABLE_DMA_QUEUES | CLR_CHECKSUM_TO_FOXES; // set options/modes 5. Finally, clear the diagnostic bit: dmaqs->control[clr] = DIAG_MODE // clear the diag mode bit 6. Need to set up memory bank selection if necessary, but normally Control Memory is used. pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 157 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.1: DMAQS Lower Bound Registers These registers specify the lower bound of the corresponding DMA queue data structure. These registers specify the lower bound of the corresponding DMA queue data structure. The head, tail, and length of the DMA queue are initialized when this register is written. When the DMA queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the DMA queue as a circular buffer. When this register is written, the corresponding DMA queue is essentially reset. This is because the head, tail, and length of the queue are all reset. . Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 604 684 704 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. These registers can only be written when the diagnostic bit has been set in the DMAQS Control Register. The alignment should correspond to the size specified in the upper bound register. For example, it should be 4K aligned if the upper bound specifies 4K size. The low order nine bits are not writable and read back '0'. DMA QUEUES (DMAQS) Page 158 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 3.2: DMAQS Upper Bound Registers These registers specify the encoded size/upper bound of the corresponding DMA queue data structure. The actual upper bound is calculated by adding the decoded queue size to the lower bound. When the DMA queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the DMA queue as a circular buffer. Length Type Address 3 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. These registers can only be written when the diagnostic bit has been set in the DMAQS Control Register. XXXX 0604 XXXX 0644 XXXX 0684 Bit(s) Encoding is as follows: 000 59512 bytes of memory 001 611K bytes of memory 010 632K bytes of memory 011 654K bytes of memory 100 678K bytes of memory 101 6916K bytes of memory 110 7132K bytes of memory 111 7364K bytes of memory Description 2-0 pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 159 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.3: DMAQS Head Pointer Registers These registers point to the head element of the corresponding DMA queue. During normal operations, these registers do not need to be read or written; they are used by the IBM3206K0424 to implement the DMA queues. These registers are initialized when the DMAQS Lower Bound Registers for the corresponding DMA queue is written. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. They can only be written when the diagnostic bit has been set in the DMAQS Control Register. The head pointer registers are 4-byte aligned (low order two bits are always '0'). Bits 31-17 are calculated internally and are not writable. 608 688 708 3.4: DMAQS Tail Pointer Registers These registers point to the next free element of the corresponding DMA queue. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. They can only be written when the diagnostic bit has been set in the DMAQS Control Register. The head pointer registers are four-byte aligned (low order two bits are always '0'). Bits 31-17 are calculated internally and are not writable. 60C 68C 70C DMA QUEUES (DMAQS) Page 160 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 3.5: DMAQS Length Registers These registers specify the length in bytes of the corresponding DMA queue. This register is cleared when the corresponding DMAQS Lower Bound Registers is written. Length Type Address 17 bits Read Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'00000000' The lengths are calculated and cannot be written. 614 694 714 3.6: DMAQS Threshold Registers These registers specify a queue length threshold at which the corresponding status bit is generated. These registers should be set equal to the queue length that should cause status to be generated. For example, if the value was set to five, then no interrupt would be generated until the queue was length five or more for the corresponding DMA queue. The threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. When this register is set to `0', no thresholding occurs. Length Type Address 17 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'0000' Must be a multiple of four. 61C 69C 71C pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 161 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.7: DMAQS Interrupt Status This register indicates the source(s) of the interrupt(s) pending. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Value 26 bits Read/Write XXXX 6F0 and 6F4 None X'00009200' DMA Descriptor Queue 2 Threshold Exceeded DMA Descriptor Queue 1 Threshold Exceeded DMA Descriptor Queue 0 Threshold Exceeded Error Occurred During Descriptor Transfer Error Occurred During DMA Transfer Q2 Error Occurred During DMA Transfer Q1 Error Occurred During DMA Transfer Q0 Error Enqueuing CSKED Descriptor Zero Address in Source/Destination Error Enqueuing RAALL Descriptor DMA Descriptor Queue 2 Not Full DMA Descriptor Queue 1 Not Full DMA Descriptor Queue 0 Not Full Error During Delayed Int Transfer DMA Descriptor Queue 2 Full DMA Descriptor Queue 1 Full DMA Descriptor Queue 0 Full Enq FIFO Thresh Exceeded DMA Transfer Complete Q2 DMA Transfer Complete Q1 1 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function 9 8 7 6 5 4 3 2 Description When set, a zero address was detected in the source or destination field of a DMA descriptor. The remainder of the descriptor chain was skipped and an event was enqueued to the DMA complete queue. This may or may not be an error condition. It is not an error if the get buffer mode is being used and no buffer was available. In this case, the descriptor can be retried or discarded by software. When set, the DMA enqueue FIFO length threshold has been exceeded. When set, the DMA enqueue FIFO is full and further enqueues will be held off. This bit is hot and cannot be reset. This bit is set when an improper sequence is detected for loading the DMAQS Enqueue DMA Descriptor Primitive in 64 bit addressing mode. A descriptor was loaded that had a DMA length equal to zero. This will not stop the DMA engine, but it is technically a user error. A descriptor was enqueued from PCORE with a chain length of zero. A descriptor was enqueued from CSKED with a chain length of zero. A descriptor was enqueued from REAALL with a chain length of zero. 25 Zero Address in Source/Destination 24 23 22 21 20 19 18 Enq FIFO Thresh Exceeded Enq FIFO Full Enqueue Primitive Sequence Error Zero Length DMA Loaded Error Enqueuing PCORE Descriptor Error Enqueuing CSKED Descriptor Error Enqueuing REALL Descriptor DMA QUEUES (DMAQS) DMA Transfer Complete Q0 0 Error Enqueuing Descriptor Zero Length DMA Loaded Zero Address in Src/Dst DMA Descriptor Error Enq FIFO Full Page 162 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 17 16 15 14 13 12 11 10 9 8 7 Function Error Enqueuing Descriptor DMA Descriptor Error DMA Descriptor Queue 2 Not Full DMA Descriptor Queue 2 Threshold Exceeded DMA Descriptor Queue 2 Full DMA Descriptor Queue 1 Not Full DMA Descriptor Queue 1 Threshold Exceeded DMA Descriptor Queue 1 Full DMA Descriptor Queue 0 Not Full DMA Descriptor Queue 0 Threshold Exceeded DMA Descriptor Queue 0 Full IBM Processor for Network Resources Description A descriptor was enqueued with a chain length of zero. An invalid transfer was described by the value loaded into the Transfer Count and Flag register. The DMA descriptor Queue 2 is not full. This bit always contains the status of the queue and is therefore is not writable. The threshold for DMA descriptor Queue 2 has been exceeded. The DMA descriptor Queue 2 is full. This bit always contains the status of the queue and is therefore is not writable. The DMA descriptor Queue 1 is not full. This bit always contains the status of the queue and is therefore is not writable. The threshold for DMA descriptor Queue 1 has been exceeded. The DMA descriptor Queue 1 is full. This bit always contains the status of the queue and is therefore is not writable. The DMA descriptor Queue 0 is not full. This bit always contains the status of the queue and is therefore is not writable. The threshold for DMA descriptor Queue 0 has been exceeded. The DMA descriptor Queue 0 is full. This bit always contains the status of the queue and is therefore is not writable. Hardware errors occurred transferring the DMA descriptor. The transfer stopped after detecting the error. If the descriptor transfer is finished or is to be terminated, the byte count register must be written to clean up the failed descriptor transfer. Before this bit is reset, the DMA descriptor queue must contain the valid descriptor data or the ®dmtdqcn. must be written to the value it contained prior to the descriptor enqueue. Hardware errors occurred during the last transfer on Queue 2. The transfer stopped after detecting the error. Inspect GPDMA registers for actual location of error. Hardware errors occurred during the last transfer on Queue 1. The transfer stopped after detecting the error. Inspect GPDMA registers for actual location of error. Hardware errors occurred during the last transfer on Queue 0. The transfer stopped after detecting the error. Inspect GPDMA registers for actual location of error. The DMA transfer has completed for Queue 2. The DMA transfer has completed for Queue 1. The DMA transfer has completed for Queue 0. 6 Error Occurred During Descriptor Transfer 5 4 3 2 1 0 Error Occurred During DMA Transfer Q2 Error Occurred During DMA Transfer Q1 Error Occurred During DMA Transfer Q0 DMA Transfer Complete Q2 DMA Transfer Complete Q1 DMA Transfer Complete Q0 pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 163 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.8: DMAQS Interrupt Enable This register serves as a mask for DMAQS Interrupt Status. See DMAQS Interrupt Status on page 162 for the bitwise description that the corresponding bit in this register will mask. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Value 26 bits Read/Write XXXX 670 and 674 None X'00260078' 3.9: DMAQS Control Register Used to set options for DMAQS. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power on Value 32 bits Read/Write XXXX 0770 and 774 See bit descriptions. X'000C0001' Memory select for IBM3206K0424 DMA Descriptor Rearbitrate on Descriptor Chain Completion Enable Cache Flushes of Local Descriptor Rearbitrate on Descriptor Completion Enable Full Round Robin Scheduling Memory select for DMA Queues Enable Register based DMAs Clear Checksum to All Ones Disable Descriptor snooping Endian of DMA Descriptors Disable Descriptor prefetch FIFO Length Threshold Enable Queue 2 DMAs Enable Queue 1 DMAs Enable Queue 0 DMAs 1 Delayed Int Endian bit Enable Delayed Int 1 Enable Delayed Int 2 Route Int 2 to Int 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s0 31 Reset FIFO Function 9 8 7 6 5 4 3 2 Description When this bit is set, the internal DMA enqueue FIFO is flushed, and this bit is reset. The result is this bit will always be read as a '0'. This bit can only be set in diagnostic mode. DMA QUEUES (DMAQS) Page 164 of 676 pnr25.chapt04.01 August 14, 2000 Diagnostic Mode 0 Queue on Error Restart DMA Reset FIFO Reserved IBM3206K0424 Preliminary Bit(s0 30 29-23 22 21 Function Restart DMA Reserved Disable Descriptor snooping Disable Descriptor prefetch Enable Cache Flushes of Local Descriptor FIFO Length Threshold Enable Full Round Robin Scheduling Rearbitrate on Descriptor Completion IBM Processor for Network Resources Description When this bit is set, the internal DMA state machine restarts the current DMA that is stopped, and this bit is reset. The result is this bit will always be read as a '0'. This bit should only be used at the specific recommendation of an IBM3206K0424 developer. Reserved. When set, this bit is the DMA descriptor snooping logic is disabled. When this bit is enabled, IBM3206K0424 performance may be enhanced. When set, this bit is the next descriptor prefetch logic is disabled. Otherwise Performance may be enhanced by enabling this function. When set, this bit is all local DMA descriptors are flushed out of BCACH before being used. This only needs to be used if local DMA descriptors are in Packet Memory and are updated via the slave interface. Cut-through descriptors do not fall in this category. This value is used to set the FIFO length threshold. When this threshold is exceeded, bit 23 of the Interrupt Status Register is set. When set, this bit is all three DMA queues are of equal priority. When cleared, Queue 0 is higher priority than queues 1 and 2. When set, this bit is the DMA queues are rearbitrated after each individual DMA descriptor completes. 20 19-17 16 15 14 When set, this bit is the DMA queues are rearbitrated after full DMA descriptor chains comRearbitrate on Descriptor Chain plete. This bit takes precedence over bit 15. When both bits 14 and 15 are cleared, the Completion queues are rearbitrated after each DMA request length operation. Bit 13 is provided to ensure compatibility with previous chips. In version 2.1 and before, Queue 0 would not be scheduled immediately after itself if queue 1 or queue 2 were ready when a queue 0 DMA completed. This was because it took at least one cycle to reload the queue registers. In IBM3206K0424, the queue registers are loaded while the arbitration for the next DMA is being done, if preloading or snooping is enabled. In this case, with bit 17 set, a Queue 0 DMA may be immediately followed by another Queue 0 DMA. With bit 17 reset, the scheduling (with all queues ready) is q0q1q0q2q0q1.... This mode is provided to give Queue 0 scheduling preference without permitting it to lock out the other two queues. This bit directs queue 2 to fetch all DMA descriptors from the On-Chip SRAM. Bits 63-18 of the system descriptor address will be ignored. This bit directs queue 1 to fetch all DMA descriptors from the On-Chip SRAM. Bits 63-18 of the system descriptor address will be ignored. This bit directs queue 0 to fetch all DMA descriptors from the On-Chip SRAM. Bits 63-18 of the system descriptor address will be ignored. 13 True Queue Zero Preference Scheduling Mode 12 11 10 9 8 7 Queue 2 uses on chip SRAM Queue 1 uses on chip SRAM Queue 0 uses on chip SRAM Memory select for When this bit is set, the DMA descriptors that are located in the IBM3206K0424 are located IBM3206K0424 DMA Descriptor in Packet Memory. Otherwise they are located in Control Memory. Memory select for DMA Queues Enable Register based DMAs When this bit is set, the DMA Queues are located in Packet Memory. Otherwise they are located in Control Memory. When set, this bit is source, destination, count, and system descriptor address (SDA) registers can be written to start a DMA. When this bit is set and the DMAQS Checksum Register is cleared, the DMAQS Checksum Register is set to 0xffff. When this bit is cleared and the DMAQS Checksum Register is cleared, the DMAQS Checksum Register is set to '0'. This option should be used if the TCP/IP checksum should never be set to '0' (0xffff is `0' also). When set, this bit causes any DMA error to log an error event. When set, this bit indicates that DMA descriptors in system memory are in little endian format. The default is big endian. This bit enables DMA Queue 2. This bit enables DMA Queue 1. This bit enables DMA Queue 0. When this bit is set, DMAQS is in diagnostic mode. 6 Clear Checksum to All Ones 5 4 3 2 1 0 Queue on Error Endian of DMA Descriptors Enable Queue 2 DMAs Enable Queue 1 DMAs Enable Queue 0 DMAs Diagnostic Mode pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 165 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.10: DMAQS Enqueue DMA Descriptor Primitive This register enqueues a DMA descriptor chain to the corresponding DMA queue. The write data is the address of the descriptor chain that describes the DMA transfers. The low six bits contain a count of the number of DMA descriptors in this chain. After the DMA descriptors are enqueued by writing to this register, the chain of descriptors is fetched from system memory and the DMA transfers described by the chain of descriptors are performed. In 32 bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. Length Type Address 64 bits Write Queue 0 Queue 1 Queue 2 Power on Value Queue 0 Queue 1 Queue 2 Restrictions None XXXX 0620 XXXX 06A0 XXXX 0720 X'00000000000000000' X'00000000' X'00000000' 3.11: DMAQS Source Address Register This register is used to set and keep track of the Source Address during a DMA transfer. This is the source for the current DMA transfer. A bit in the Transfer Count and Flag Register determines whether the source address is internal to the IBM3206K0424 or is a system address. In 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. Length Type Address 64 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'0000000000000000' None XXXX 0638 XXXX 06B8 XXXX 0738 DMA QUEUES (DMAQS) Page 166 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 3.12: DMAQS Destination Address Register This register is used to set and keep track of the destination address during a DMA transfer. This is the Destination address for the current DMA transfer. In 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. A bit in the Transfer Count and Flag Register determines whether the destination address is internal to the IBM3206K0424 or is a system address. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'0000000000000000' None XXXX 0628 XXXX 06A8 XXXX 0728 3.13: DMAQS Buffer Address Register This register is used to set and keep track of the POOLS Buffer address during a DMA transfer. When the DMA Descriptor directs that a new buffer address be obtained from POOLS, this is Buffer Address for the current DMA transfer. A bit in the Transfer Count and Flag Register determines whether a buffer address has been obtained for this descriptor. This register can be written to an RXQUE queue. The low-order seven bits should be set to 0x2a, the event code for Assign Pool Buffer events. This is the Destination address for the current DMA transfer. In 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. A bit in the Transfer Count and Flag Register determines whether the destination address is internal to the IBM3206K0424 or is a system address. . Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 XXXX 0630 XXXX 06B0 XXXX 0730 Power on Value Restrictions X'0000002a' These registers should not be written during normal system operation. The low-order 7 bits are set to 0x2a and should not be modified. This is the event code for BFA events in RXQUE. pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 167 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.14: DMAQS Transfer Count and Flag Register This register specifies the type and number of bytes transferred during a DMA transfer. The lower 16 bits are a counter of the number of bytes transferred during a DMA transfer. The upper 16 bits specify the type of transfer. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions X'00000000' None Inhibit Status Update when DMA Complete XXXX 644 XXXX 06C4 XXXX 0744 Register Destination is 64 bits wide Register Source is 64 bits wide Compute Checksum/Hold Src Destination Address Specifier Clear Checksum/Hold Dest Queue on DMA Complete Tx on DMA Complete Little Endian Mode Hold Mode Source Address Specifier Byte Transfer Count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 Function Register Destination is 64 bits wide Register Source is 64 bits wide Clear Checksum/Hold Dest Compute Checksum/Hold Src Little Endian Mode 9 8 7 6 5 4 3 2 1 0 Description These bits must be used with bits 25 and 29 (see below). When this bit is set, the checksum and the alignment state are cleared. When this bit is set, a checksum will be computed over this DMA segment. When this bit is written to '0', this DMA channel operates in big endian mode. When set to '1', the channels operate in little endian mode. In little endian mode, both the source and destination must be aligned on four-byte boundaries. When set, the destination address is used as the packet address that is to be enqueued to CSKED to be transmitted. The lower bits are set to '0' so the buffer base is used for the CSKED enqueue operation. 26 Tx on DMA Complete DMA QUEUES (DMAQS) Page 168 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Function IBM Processor for Network Resources Description When set, bits 31-28 are redefined to allow the source or destination address to be held instead of incremented. Bit 29 becomes hold destination address and bit 28 becomes hold source address. This allows a single DMA descriptor to do an N-to-1 or 1-to-N transfer. For example, an entire scatter DMA list can be freed to a receive queue enqueue register. The address being held must be a register address. When holding, the maximum length is 252 bytes. When holding, the source or destination is incremented by four when the DMA completes (for auto-increment mode). Bit 31 becomes destination address 64 bits wide. Bit 30 becomes source address 64 bits wide. This destination is required to properly update 64 bit wide registers when hold mode is asserted. When this bit is set, the upper 26 bits of the DMAQS System Descriptor Address register will be queued to the DMA event queue when the DMA completes. If descriptors are not being used to set up the DMA, then before starting the DMA, the DMAQS System Descriptor Address register should be loaded before starting the DMA with a value to identify this transfer. If descriptors are being used, the DMAQS System Descriptor Address register will be loaded automatically with the system address of the descriptor block at the time it is processed. 25 Hold Mode 24 Queue on DMA Complete 23 Normally a bit will be set in the status register when the DMA completes without error. Inhibit Status Update when DMA If this bit is set, this update will not be done. This bit is useful when multiple DMAs are Complete to be done and an interrupt is only desired on the last transfer. The DMA error status bits are not affected by this bit. These bits specify how the destination address should be used for this DMA descriptor. The following are the valid patterns: 000 IBM3206K0424 memory address: The destination address specifies an IBM3206K0424 internal memory address. 001 PCI Bus Address: The destination address specifies a PCI bus address. 010 IBM3206K0424 Register Address: The destination address specifies an IBM3206K0424 register address. Only the low 16 bits must be specified. 011 Get IBM3206K0424 Buffer: The low four bits of the destination address specify a pool ID from which to get a buffer. If a buffer is not available, a zero destination address event or appropriate status is raised. Otherwise the buffer address is used as an IBM3206K0424 memory address. 100 Auto Increment Destination Address: The destination address is sourced from the previous DMA instead of the destination address specified in the descriptor. 101 Next Source Address: The destination address is the address of the source address field of the next descriptor in the current DMA chain. Using this feature allows indirection. 110 Next Destination Address: The destination address is the address of the destination address field of the next descriptor in the current DMA chain. Using this feature allows operations like doing a get buffer in the DMA descriptor chain. 111 Offset Destination Address: The Destination Address is a positive offset from the DMAQS Buffer Address Register. Using this feature allows, for example, storing the checksum value in the header of the packet. Others Reserved: Reserved and flagged as errors. 22-20 Destination Address Specifier pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 169 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description These bits specify how the source address should be used for this DMA descriptor. The following are the valid patterns: 0000 IBM3206K0424 Memory Address: The source address specifies an IBM3206K0424 internal memory address. 0001 PCI bus address: The source address specifies a PCI bus address. 0010 IBM3206K0424 Register Address: The source address specifies an IBM3206K0424 register address. Only the low 16 bits must be specified. 0011 IBM3206K0424 Memory Address and Free Buffer when DMA Complete: The source address specifies an IBM3206K0424 internal memory address, and this address will be freed to POOLS when the DMA is complete. -100 Auto Increment Source Address: The source address is sourced from the previous DMA instead of the source address specified in the descriptor. -111 Auto Increment Source Address and Free Buffer when DMA Complete: The source address is sourced from the previous DMA instead of the source address specified in the descriptor. The source address specifies an IBM3206K0424 internal memory address, and this address will be freed to POOLS when the DMA is complete. 1000 Immediate Data: Use the Source Address Field as immediate data. The data is 4 bytes in 32-bit addressing mode or eight bytes when in 64 bit addressing mode. If the count is greater than the data size, the data is repeated. 1-11 Immediate Data and Free Buffer when DMA Complete: Use the Source Address Field as immediate data. The data is 4 bytes in 32 bit addressing mode or eight bytes when in 64-bit addressing mode. If the count is greater than the data size, the data is repeated. The source address will be freed to POOLS when the DMA is complete. Others Reserved: Reserved and flagged as errors. These bits indicate the number of bytes to transfer. A non-zero value in this field will start the DMA transfer. Preliminary 19-16 Source Address Specifier 15-0 Byte Transfer Count DMA QUEUES (DMAQS) Page 170 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 3.15: DMAQS System Descriptor Address The upper 57 bits contain the address of the current descriptor block and the lower seven bits contain the number of descriptors in the chain that remain to be processed. When doing register-based DMAs, the low six bits are set to "000001" when the DMAQS Transfer Count and Flag Register is written. If DMA descriptors are used for DMA transfers, this register will contain the system address of the current descriptor block and the number of descriptors that remain to be processed. This address may be queued on DMA completion to correlate DMA transfers with system control blocks. In 32-bit addressing mode, the low-order 32 bits of the register are written, and the high-order 32 bits are reset when the register is loaded. Length Type Address 64 bits Read/Write Queue 0 Queue 1 Queue 2 Power on Value Restrictions XXXX 0648 XXXX 06C8 XXXX 0748 X'0000000000000000' This register should not be written if descriptors are going to be used to set up DMA transfers. If it is used, it must be written to 0 before descriptors are enqueued. 3.16: DMAQS Checksum Register This register contains the accumulated checksum. This register contains the accumulated checksum value. It can also be used to initialize the checksum with a seed value. The most significant bit contains the alignment state (1 = odd, 0 = even alignment). The alignment state is significant between subsequent checksummed DMAs. This register can be read at four different addresses. The base address returns the unmodified accumulated checksum. The base address +4 returns the inverted accumulated checksum. The base address + 8 returns the byte-swapped accumulated checksum. The base address + 12 returns the inverted byte-swapped accumulated checksum. Length Type Address 17 bits Read/Write Q0 Sum Q0 Inv Sum Q0 Swapped Sum Q0 Inv Swapped Q1 Sum Q1 Inv Sum Q1 Swapped Sum Q1 Inv Swapped Q2 Sum Q2 Inv Sum XXXX 0654 XXXX 065C XXXX 0664 XXXX 066C XXXX 06D4 XXXX 06DC XXXX 06E4 XXXX 06EC XXXX 0754 XXXX 075C pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 171 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Q2 Swapped Sum Q2 Inv Swapped Power on Value Q0 Sum Q0 Inv Sum Q0 Swapped Sum Q0 Inv Swapped Q1 Sum Q1 Inv Sum Q1 Swapped Sum Q1 Inv Swapped Q2 Sum Q2 Inv Sum Q2 Swapped Sum Q2 Inv Swapped Restrictions XXXX 0764 XXXX 076C X'00000000' X'0000ffff' X'00000000' X'ffff0000' X'00000000 X'0000ffff' X'00000000' X'ffff0000' X'00000000' X'0000ffff' X'00000000' X'ffff0000' Only the base address accepts write data. All four addresses return read data. DMA QUEUES (DMAQS) Page 172 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 3.17: DMAQS Local Descriptor Range Registers These registers specify the lower and upper bounds respectively of the memory range for local DMA descriptors. These registers contain the address of the lower and upper bound of the memory range of descriptors that are in the IBM3206K0424. If a descriptor block is enqueued, it is compared to these registers. If it falls within this range, only the descriptor address is placed on the queue. When the descriptor is to be loaded into the DMA registers, and it falls within this range, it will not be taken from the queue but loaded directly from the descriptor address. These registers are 4K aligned. The upper bound register contains the address of the last 4K block in the local descriptor address range. Length Lower Bound Upper Bound Type Address Read/Write Lower Bound Upper Bound Power on Value Lower Bound Upper Bound Restrictions XXXX 0798 XXXX 07A4 X'0000000000000000' X'00000000' 64 bits 32 bits Can be written in diagnostic mode only. Upper bound is 32 bits. The upper 32 bits are internally generated, and are not different from the upper 32 bits of the lower bound register. The last four addresses in this range are reserved, and should not be used to hold descriptors. 3.18: DMAQS Event Queue Number Register This register specifies which DMAQS queue should be used when DMA descriptors are enqueued from CSKED (DMA on transmit comp). This register also indicates the RXQUE Event Queue to which events should be enqueued for each DMAQS queue register. Length Type Address Power on Value Restrictions 20 bits Read/Write XXXX 07CC X'00002210' Can be written in diagnostic mode only. Invalid values (that is, 3), force queue number 2. pnr25.chapt04.01 August 14, 2000 DMA QUEUES (DMAQS) Page 173 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 3.19: DMAQS DMA Request Size Register This register specifies the maximum request size for DMA descriptor scheduling. This is the amount of data that DMAQS will request GPDMA to move in a single request. For example, if a descriptor wants to move 2K of data and the request size is set to 512 bytes, then DMAQS will request 512 bytes to be moved and then rearbitrate the DMA queues. A value of `0' is the same as 0xffff. Length Type Address Power on Value Restrictions 16 bits Read/Write XXXX 07C0 X'00000000' None 3.20: DMAQS Enq FIFO Register This register is for diagnostic use only. It holds DMA descriptor waiting to be placed on a DMA queue. Reading this register is destructive. The oldest entry is read on each read. If it is desired to re-dispatch the dequeued entries, they will have to be re-enqueued. DMA Descriptors which reside in System Storage are not immediately copied into the queue, but space is reserved in the queue for the descriptors, and a descriptor is built which will copy the descriptor into the queue when needed. Length Type Address Power on Value Restrictions 64 bits Read Only XXXX 07F8 X'0000000000000000' Can not be written. DMA QUEUES (DMAQS) Page 174 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 4: General Purpose DMA (GPDMA) This entity provides DMA control between System Memory and IBM3206K0424 Packet Memory. DMA transfers must be enabled in the GPDMA control registers for transmit and/or receive. There are two ways to initiate DMA transfers. The first is by directly writing the Source Address, Destination Address, and Transfer Count and Flag Registers. The second is by using DMA descriptors and enqueueing them using DMAQS. These two methods should not be used simultaneously. If using descriptors, refer to the DMAQS section beginning on DMA QUEUES (DMAQS) on page 154 for more information. DMA transfers to system I/O space are not allowed. 4.1: GPDMA Interrupt Status This register indicates the source(s) of the interrupt(s) pending, or is used as a status register when the bits are enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions Error Occurred During Transmit Transfer Error Occurred During Receive Transfer Zero length DMA request from DMAQS 9 bits Read/Write XXXX 0108 and 0C X'000' None 8 7 6 5 4 3 2 1 Bit(s) 8 7 6 5 4 Function DMA Transaction Timeout DMA Command Error Reserved Reserved Transmit Transfer Complete 0 Description The DMA Transaction Timeout specified in the GPDMA Interrupt Enable timed out. An invalid transfer was described by the value loaded into the Transfer Count and Flag Register. Reserved Reserved Zero length DMA request from DMAQS has requested a DMA with a length of zero. This bit is for information use only. This bit DMAQS is not an error that will prevent GPDMA from processing additional DMA requests. pnr25.chapt04.01 August 14, 2000 Receive Transfer Complete DMA Transaction Timeout DMA Command Error Reserved Reserved General Purpose DMA (GPDMA) Page 175 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 3 2 1 0 Function Error Occurred During Receive Transfer Error Occurred During Transmit Transfer Receive Transfer Complete Transmit Transfer Complete Description Hardware errors occurred during the last transfer. The transfer stopped after detecting the error. Hardware errors occurred during the last transfer. The transfer stopped after detecting the error. The receive transfer is complete. The transmit transfer is complete. Preliminary 4.2: GPDMA Interrupt Enable This register serves as a mask for GPDMA Interrupt Status. See GPDMA Interrupt Status on page 175 for the bitwise description that the corresponding bit in this register will mask. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 9 bits Read/Write XXXX 0110 and 14 X'9C' None General Purpose DMA (GPDMA) Page 176 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 4.3: GPDMA Control Register Used to set options for DMA operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Value Restrictions 32 bits Read/Write XXXX 0118 and 1C X'008800c7' None Enable limiting DMA burst to cache line size Disable access to internal array Memory Transfer Threshold DMA Transaction Timeout Data Transfer Break Type PCI target cache line size PCI Transfer Threshold 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 25 24 Assume 64 Assume 32 Assume 64 Assume 32 Assume 64 Assume 32 Assume 64 Assume 32 Function 9 8 7 6 5 4 3 2 1 Description Assume 64-bit PCI Interface for Descriptor Transfers Assume 32-bit PCI Interface for Descriptor Transfers Assume 64-bit PCI Interface for Queue 2 Transfers Assume 32-bit PCI Interface for Queue 2 Transfers Assume 64-bit PCI Interface for Queue 1 Transfers Assume 32-bit PCI Interface for Queue 1 Transfers Assume 64-bit PCI Interface for Queue 0 Transfers Assume 32-bit PCI Interface for Queue 0 Transfers 2 The value of these bits multiplied by eight determines the number of bytes that must be ready to transfer before a DMA transfer is initiated on the PCI bus. This can be used to tune the performance of the PCI bus. If the number of bytes left to transfer is less than the threshold, the transfer will start when all remaining bytes are ready to be transferred. The value of these bits multiplied by eight determine the number of bytes that must be ready to transfer before a transfer is initiated on the internal memory bus. This can be used to tune the performance of the memory subsystem. These bits hold a value that is used to count the number of cycles that an unacknowledged DMA cycle is in progress. If the count is reached, due to an internal chip hang condition, the DMA is terminated. A value of '0' disables this function. 23-20 PCI Transfer Threshold 19-16 Memory Transfer Threshold 15-9 DMA Transaction Timeout pnr25.chapt04.01 August 14, 2000 General Purpose DMA (GPDMA) Page 177 of 676 Enable Transmit DMAs 0 Enable Receive DMAs Word Swap Mode Assume 64 Assume 32 Assume 64 Assume 32 Assume 64 Assume 32 Assume 64 Assume 32 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description This field controls word swapping for data being transferred to PCINT. The word swapping is done as part of endian alignment. The bits are defined as follows: 00 No Swap: The 32-bit words being transferred will not be swapped by PCINT 01 Swap: The 32-bit words being transferred will always be swapped by PCINT 10 Endian Swap: The words will be swapped if byte swapping is being done. 11 Anti-endian Swap: The words will be swapped if byte swapping is not being done. Preliminary 8-7 Word Swap Mode 6 When this bit is set, the internal array cannot be read or written. This can be used to Disable access to internal array ensure that the array is not inadvertently read or written while DMAs are in progress, causing unpredictable results. Enable limiting DMA burst to cache line size This bit on causes a DMA burst to terminate upon crossing a cache line boundary of the PCI target. This field indicates the cache line size if aligning DMAs to the cache line size of the PCI target (see bit 5). 00 32 bytes 01 64 bytes 10 128 bytes 11 256 bytes This bit on causes a re-arbitrate request from PCI to "immediately" stop moving data and resurface a new request to move the remainder of the data. When reset, GPDMA stops data movement at the next Cache line boundary. This bit on enables DMA transfers out of the IBM3206K0424. This bit on enables DMA transfers into the IBM3206K0424. 5 4-3 PCI target cache line size 2 1 0 Data Transfer Break Type Enable Receive DMAs Enable Transmit DMAs 4.4: GPDMA Source Address Register Used to set and keep track of the Source Address during a DMA transfer. This is the system address that increments during a DMA transfer. A bit in the Transfer Count and Flag Register determines if the source address is internal to the IBM3206K0424 or is a system address. Length Type Address Power on Value Restrictions 64 bits Read/Write XXXX 0128 X'0000000000000000' None General Purpose DMA (GPDMA) Page 178 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 4.5: GPDMA Destination Address Register Used to set and keep track of the Destination address during a DMA transfer. This is the Destination address that increments during a DMA transfer. A bit in the Transfer Count and Flag Register determines if the destination address is internal to the IBM3206K0424 or is a system address. Length Type Address Power on Value Restrictions 64 bits Read/Write XXXX 0130 X'0000000000000000' None 4.6: GPDMA Transfer Count and Flag Register Specifies the type and number of bytes transferred during a DMA transfer. The lower 16 bits are a counter of the number of bytes transferred during a DMA transfer. It is a count down counter; when zero is reached, the transfer ends. Writing a non-zero value to the lower 16 bits starts the DMA transfer. The upper 16 bits specify the type of transfer as follows. Length Type Address Power on Value Restrictions 32 bits Read/Write XXXX 0138 X'000000' None System/IBM3206K0424 Destination Address System/IBM3206K0424 Source Address Register/Memory Destination Address Register/Memory Source Address Data/Address Source Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-30 29 28 Reserved Reserved Reserved Function These bits must be `0'. 9 8 Byte Transfer Count 7 6 Little Endian Mode Assume 64 Assume 32 Hold Mode Reserved Reserved Reserved Reserved Reserved Reserved 5 4 3 2 1 0 Description pnr25.chapt04.01 August 14, 2000 General Purpose DMA (GPDMA) Page 179 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 27 26 Function Little Endian Mode Reserved Description When this bit is written to '0', this DMA channel operates in big endian mode. When '1', it operates in little endian mode. When in little endian mode, both the source and destination must be aligned on four-byte boundaries. Reserved. When set, bits 28-29 are redefined to allow the source or destination address to be held instead of incremented. Bit 29 becomes the hold destination address and bit 28 becomes the hold source address. The address being held must be a register address. When holding, the maximum length is 240 bytes. Reserved. Assume the PCI Interface is 64-bits wide. Assume the PCI Interface is 32-bits wide. If this bit is set, the destination address is a register address. If this bit is not set, the destination address is a memory address. If the destination address is a system address, this bit should cleared. I/O DMA cycles on the PCI bus are not implemented. If this bit is set, the destination address is a PCI bus address. If this bit is not set, the destination address is internal to the chip. If this bit is set, the Source Address Register contains the source data. If this bit is not set, the Source Address Register contains the source address. Reserved. If this bit is set, the source address is a register address. If this bit is not set, the source address is a memory address. If the source address is a system address, this bit should cleared. I/O DMA cycles on the PCI bus are not implemented. If this bit is set, the source address is a PCI bus address. If this bit is not set, the source address is internal to the chip. These bits indicate the number of bytes to transfer. A non-zero value in this field starts the DMA transfer. Preliminary 25 Hold Mode 24 23 22 21 Reserved Assume 64 Assume 32 Register/Memory Destination Address System/IBM3206K0424 Destination Address Data/Address Source Address Reserved Register/Memory Source Address System/IBM3206K0424 Source Address Byte Transfer Count 20 19 18 17 16 15-0 General Purpose DMA (GPDMA) Page 180 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 4.7: GPDMA DMA Max Burst Time Used to limit the number of cycles a master can burst on the PCI bus. When a DMA burst is started, a counter is loaded with the value in this register. When the counter expires and the current access completes, the PCI bus is released for use by another bus master. Writing a non-zero value to this register enables this function. Length Type Address Power on Value Restrictions 24 bits Read/Write XXXX 0158 X'000' None 4.8: GPDMA Maximum Memory Transfer Count Used to limit the size of data requests to the Control/Packet Memories. This register defines the maximum number of bytes to be transferred in a single storage request to IBM3206K0424 Storage. Length Type Address Power on Value Restrictions 7 bits Read/Write XXXX 0150 X'40' None 4.9: GPDMA Checksum Register This register contains the accumulated checksum value. It can also be used to initialize the checksum with a seed value. The most significant bit contains the alignment state (1 = odd, 0 = even alignment). This register can be read at four different addresses. The base address returns the unmodified accumulated checksum. The base address +4 returns the inverted accumulated checksum. The base address + 8 returns the byte-swapped accumulated checksum. The base address + 12 returns the inverted byte-swapped accumulated checksum. Length Type Address Power on Value Restrictions 17 bits Read/Write XXXX 0160 X'00000' None pnr25.chapt04.01 August 14, 2000 General Purpose DMA (GPDMA) Page 181 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 4.10: GPDMA Read DMA Byte Count This register counts the bytes transferred into the IBM3206K0424 by the DMA controller. Descriptor bytes can optionally be included. (See the GPDMA Control Register on page 177 for details.) Length Type Address Power on Value Restrictions 32 bits Read/Write XXXX 0178 X'00000000' None 4.11: GPDMA Write DMA Byte Count This register counts the bytes transferred out of the IBM3206K0424 by the DMA controller. Length Type Address Power on Value Restrictions 32 bits Read/Write XXXX 017C X'00000000' None 4.12: GPDMA Array Read Address This register is used to read the GPDMA internal array. The internal array is used to hold data for the DMA. The array is organized as 64 32-bit words. The GPDMA Array Read Address is written with the address of the word that is to be read. The GPDMA Array Data Register is read to obtain the contents of the addressed word. The GPDMA Array Read Address is incremented each time the GPDMA Array Data Register is read, causing repeated reads of the GPDMA Array Data Register to obtain sequential words from the array. Length Type Address Power on Value Restrictions 8 bits Read/Write XXXX 0140 X'00' This address space is for diagnostic use only. It should not be read or written during normal operation. The low order two bits of GPDMA Array Read Address are place holders and are ignored. They should be set to `0'. General Purpose DMA (GPDMA) Page 182 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 4.13: GPDMA Array Write Address This register is used to write the GPDMA internal array. The internal array is used to hold data for the DMA. The array is organized as 64 32-bit words. The GPDMA Array Write Address is written with the address of the word that is to be written. The GPDMA Array Data Register is written to write the addressed word. The GPDMA Array Write Address is incremented each time the GPDMA Array Data Register is written, causing repeated writes of the GPDMA Array Data Register to write sequential words in the array. Length Type Address Power on Value Restrictions 8 bits Read/Write XXXX 0144 X'00' This address space is for diagnostic use only. It should not be read or written during normal operation. The low order two bits of GPDMA Array Read Address are place holders and are ignored. They should be set to `0'. 4.14: GPDMA Array Reads the contents of the internal array. The internal array is used to hold data for the DMA. Length Type Address Power on Value Restrictions 64 words x 32 bits Read/Write XXXX 0148 X'00000000' This address space is for diagnostic use only. It should not be read or written during normal operation. The array is read/written at the location indicated by the GPDMA Array Read Address or GPDMA Array Write Address. pnr25.chapt04.01 August 14, 2000 General Purpose DMA (GPDMA) Page 183 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Memory Controlling Entities Entity 5: The DRAM Controllers (COMET/PAKIT) This section describes the function of the COMET/PAKIT entities. COMET is the memory controller for Control Memory, and PAKIT is the memory controller for Packet Memory. Each controller can support the following types of memory: * Synchronous DRAMs running at 133MHz (7.5 ns cycle time) with a CAS latency of two or three and a burst length of one or two. Memory sizes of 4MB, 8MB, 16MB, and 32MB are supported. Please note that the cycle time of the SDRAM clock is a constant on the IBM3206K0424. Any SDRAM part selected must be capable of running at 133MHz or faster at CAS latency 2 or 3. * Synchronous SRAM running at 133MHz (7.5 ns cycle time) with a read latency of two and a write latency of zero or two. Memory sizes of 1MB, 2MB, 4MB, and 8MB are supported. Note: For any memory configuration, modules must be selected such that the loading on any memory net (including card wiring) does not exceed 120pF. The number of column address lines is programmable, allowing both DRAMs with symmetric address (same number of row and column address lines) and asymmetric address (typically having more row than column address lines). If using SDRAM, the memory may be operated as having one or two arrays. The arrays are differentiated by their chip selects. If the memory is configured to have two arrays, the memory's address range is split equally between the two arrays. Memory checking can be enabled/disabled, and the method of checking selected can be either ECC or parity. IF ECC is selected, seven data bits are used for ECC over the 32 data bits. If parity is selected, four data bits are used to provide parity over the 32 data bits. COMET/PAKIT are designed so that memory contents are preserved over a reset. If the IBM3206K0424 is reset while a memory write cycle is in progress, the cycle is completed in an orderly fashion to ensure that valid ECC/parity is written. Memory timings are not violated when reset goes active. Refresh is maintained during the reset. The DRAM Controllers (COMET/PAKIT) Page 184 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Memory Reset Sequence After a reset, onboard ROM or external firmware must properly configure the control registers for COMET/PAKIT. If using SRAM, the reset sequence is complete. If using SDRAM, bit 3 of the memory controller's SDRAM Command and Status Register must be written to a '1' to initiate forcing the SDRAMs out of the self refresh state and performing the POR sequence. When bits five and four of this register are '00', the SDRAMs are ready for use. Note: Memory configuration errors occur if an attempt is made to use memory that is configured incorrectly or, if an attempt is made to use SDRAM before the POR sequence is completed. Accesses to the first 0x20 bytes of memory (Control or Packet) are not allowed unless bit 26 of the corresponding memory control register is set. With this restriction in place, accesses with zero-valued pointers will cause the zero address error bit in the memory controller's status register to be set. pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 185 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 5.1: COMET/PAKIT Control Register This register contains the information that controls the functions of the entity. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Before this register can be altered, writing it must be enabled in COMET/PAKIT Memory Controller Write Enable Register (described on page 197). Length Type COMET Address PAKIT Address Power On Value Restrictions Disable Controller Waiting for TRAS Being Met on Auto Precharge 32 bits Read/Write XXXX 0900 AND 04 XXXX 0980 AND 84 X'00000000' None SDRAM Column Address Size/SRAM Module Width Disable Driving Memory Data Nets When Idle Latch Error Registers on Single Bit Errors Disable Zero Address Error Detection SRAM Byte Enables for Writes Only Freeze DRAM Error Registers Disable SDRAM Overlapped Drive SRAM Output Enables Encode SRAM Chip Selects State Information Selection SRAM or SDRAM Latency SDRAM Burst Length of 2 4/2 Bank SDRAM Device 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function Disable Controller Waiting for TRAS Being Met on Auto Precharge Reserved 4/2 Bank SDRAM Device Reserved Encode SRAM Chip Selects 9 8 7 6 5 4 3 2 1 Description Some SDRAM modules don't allow sending a read or write with auto precharge to them unless TRAS has been met. If using ESDRAM (any SDRAM at burst length of two, or a part that allows sending an auto precharge before TRAS has been met), this bit should be set. This bit has no meaning for SRAM. Reserved When this bit is `1', the SDRAMs attached are four-bank devices. When a `0', the SDRAMs are two-bank devices. A `0' setting works for either type device, but four-bank devices provide slightly better performance if this bit is set to '1'. Reserved When using SRAM, this bit set to a `0' causes the chip select outputs to be direct chip selects. Set to '1', chip selects 2-0 carry an encoded value for one of eight chip selects. Chip select three indicates when chip selects 2-0 are valid. 31 30 29 28 27 The DRAM Controllers (COMET/PAKIT) Page 186 of 676 pnr25.chapt04.01 August 14, 2000 Number of DRAM Arrays 0 Memory Unpopulated Enable ECC or Parity SDRAM Split ECC Parity or ECC Memory Type Memory Size Reserved Reserved Reserved IBM3206K0424 Preliminary Bit(s) 26 25-24 23 Function Disable Zero Address Error Detection. State Information Selection. Disable Driving Memory Data Nets When Idle IBM Processor for Network Resources Description When set to `1', this bit disables the detection of zero address errors to memory. These bits control what will be visible on the enstate outputs if COMET/PAKIT are selected for observation on the enstate pins. When set to `1', this bit disables the memory controller from driving the memory data nets to '0' when the controller is idle. When set to `1', this bit indicates that the ECC/parity for multiple arrays of memory are in separate modules and a slight increase in performance is possible. If this bit is `0', the ECC/parity is in a shared module. If using neither ECC or parity, this bit should be set to '1' for a slight performance increase. This bit applies only when SDRAM is being used. When set to '1', this bit indicates that the SDRAM should be driven assuming a burst length of two. This bit set to '0' indicates a burst length of one. When set to '1', this bit allows functional output enables to be driven for SRAMs. When set to '0', the output enables are driven active continuously. When set to '1', this bit freezes the Memory Address Register and the Syndrome Register when a memory error occurs. When this bit is set to '0', the error registers are updated whenever an error is encountered. For this bit to have any meaning with single bit errors, bit 18 must also be a '1'. 22 SDRAM Split ECC 21 20 SDRAM Burst Length of 2 Drive SRAM Output Enables 19 Freeze Error Registers 18 17 16 When set to '1', this bit allows error data to be latched into the Memory Error Address Latch Error Registers on Single Register and the Syndrome Register when a single bit errors occurs. When this bit is Bit Errors set to '0', single bits errors do not latch data into the error registers. Enable ECC or Parity SRAM Byte Enables for Writes Only Disable SDRAM Overlapped Bank Accesses/Shorten SRAM Write Duration Parity or ECC Reserved This bit set to '1' enables ECC detection/correction or parity error detection. When set to '1', this bit' causes byte enables to only be driven on writes to SRAM. The enables are driven inactive for reads. If the bit is set to '0', the byte enables are valid on both reads and writes. When the memory controller is configured for SDRAM, setting this bit to '1' disables the overlapping of bank accesses. When configured for SRAM, setting this bit to '1' shortens the time the IBM3206K0424 drives data on writes. When set to '1', this bit causes parity to be generated. This bit set to '0' causes ECC to be generated. ECC is supported for DRAM only. Reserved These bits indicate the delay between performing a read and the memory returning data. The bits are encoded as follows: 00 1 Cycle (SRAM only) 01 2 Cycles 10 3 Cycles (SDRAM only) 11 Reserved These bits indicate the type of memory being used for memory. The bits are encoded as follows: 00 SRAM 01 ZBT SRAM 10 Synchronous DRAM (SDRAM) 11 Enhanced Synchronous DRAM (ESDRAM) If this bit is '1', there is no physical memory connected to this controller. 15 14 13-12 11-10 SRAM or SDRAM Latency 9-8 Memory Type 7 Memory Unpopulated. pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 187 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description These bits indicate the number of column address lines. The bits are encoded for SDRAM as follows: '000' 8 column address lines (256 words/row) '001' 9 column address lines (512 words/row) '010' 10 column address lines (1K words/row) '011' Reserved '1XX' Reserved The bits are encoded for SRAM as follows: '000' 18-bit wide 4 Mb SRAM '001' 18-bit wide 8 Mb SRAM '010' 18-bit wide 16 Mb SRAM '011' 18-bit wide 32 Mb SRAM '100' 36-bit wide 4 Mb SRAM '101' 36-bit wide 8 Mb SRAM '110' 36-bit wide 16 Mb SRAM '111' 36-bit wide 32 Mb SRAM These bits indicate the total amount of memory present, that is, two 64MB SDRAM arrays would result in a value of 128MB in these bits. The bits are encoded as follows: '000' 1 MB '001' 2 MB '010' 4 MB '011' 8 MB '100' 16 MB '101' 32 MB '110' 64 MB '111' 128 MB - SDRAM Only This two bit indicates the number of arrays of DRAM present. This bit set to '0' indicates one array; the bit set to '1' indicates two arrays. Preliminary 6-4 SDRAM Column Address Size/SRAM Module Width 3-1 Memory Size 0 Number of DRAM Arrays. The DRAM Controllers (COMET/PAKIT) Page 188 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 5.2: COMET/PAKIT Status Register This register contains status information for COMET/PAKIT. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type COMET Address PAKIT Address Power On Value Restrictions Memory Address Out of Range Error 1 6 bits Read/Write XXXX 0908 AND 0C XXXX 0988 AND 8C X'00000000' Uncorrectable Error Detected Memory Configuration Error Zero Address Error Single bit Error Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5 4 3 2 1 0 Reserved Zero Address Error Memory Configuration Error Uncorrectable Error Detected Single bit Error Memory Address Out of Range Error Reserved Function Reserved 9 8 7 6 5 4 3 2 Description This bit is set if COMET/PAKIT is presented an address of zero. This bit is set if COMET/PAKIT is configured in an invalid combination. This bit is set if an uncorrectable error is detected. This bit is set if a single bit ECC error is detected. This bit is set if the address presented to the memory controller is out of the defined range. Reserved pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 189 of 676 Reserved 0 IBM3206K0424 IBM Processor for Network Resources Preliminary 5.3: COMET/PAKIT Interrupt Enable Register This register contains bits corresponding to the bits in the COMET/PAKIT Status Register. If a bit in this register is set and the corresponding bit is set in the COMET/PAKIT Status Register, an interrupt is generated. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type COMET Address PAKIT Address Power On Value Restrictions 6 bits Read/Write XXXX 0910 AND 14 XXXX 0990 AND 94 X'0000003A' 5.4: COMET/PAKIT Lock Enable Register This register contains bits corresponding to the bits in the COMET/PAKIT Status Register. If a bit in this register is set and the corresponding bit is set in the COMET/PAKIT Status Register, a signal is sent to VIMEM indicating that memory should be locked. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type COMET Address PAKIT Address Power On Value Restrictions 6 bits Read/Write XXXX 0918 AND 1C XXXX 0998 AND 9C X'0000003A' The DRAM Controllers (COMET/PAKIT) Page 190 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 5.5: COMET/PAKIT Memory Error Address Register This register holds the address at which the last memory error occurred. Length Type COMET Address PAKIT Address Power On Value Restrictions Reserved Error Address 32 bits Read Only XXXX 0920 XXXX 09A0 X'00000000' 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-27 26-0 Reserved Error Address. Function Reserved. The read address of the last memory error. 9 8 7 6 5 4 3 2 1 0 Description pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 191 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 5.6: COMET/PAKIT SDRAM Command and Status Register This register is used to issue various commands to and control the timing operation of Synchronous DRAMS when they are attached to the IBM3206K0424. If the IBM3206K0424 is not configured for SDRAMs, any writes to bits 3-0 of this register are ignored. This register is also used to reflect the status of the Synchronous DRAMs. When a command bit in this register is set (bits 3-0 only), the command executes and resets the bit upon completion. Only one bit (3-0 only) may be set during any write. Software should poll this register to make sure the previous command has completed before issuing another write to this register. If more than one bit at a time is written to this register (3-0 only), the results may be unpredictable. Length Type COMET Address PAKIT Address Restrictions 32 bits Read/Write XXXX 0924 XXXX 09A4 Power On Value: X'00003030' Start Power on Reset Sequence Enter the Self Refresh State 1 Reserved TDPL Delay TRAS Delay TRP Delay TRC Delay 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 Reserved Function Reserved. 9 8 7 6 5 4 3 2 Description 23-20 TDPL Delay The value of these four bits determine the number of cycles after writing data before a precharge command may be issued. To determine the value needed in these bits, take the TDPL3 (for CAS latency 3) or TDPL2 (for CAS latency 2) parameter from the specification of the SDRAM of the part to be used, divide by 7.5 ns, and round up if necessary. Suggested values are: X'2' 6.8 ns SDRAM X'1' 6 ns ESDRAM X'1' 7.5 ns ESDRAM The value of these four bits determine the number of cycles a bank must be active. To determine the value needed in these bits, take the TRAS parameter from the specification of the SDRAM of the part to be used, divide by 7.5 ns, and round up if necessary. Suggested values are: X'7' 6.8 ns SDRAM X'3' 6 ns ESDRAM X'3' 7.5 ns ESDRAM 19-16 TRAS Delay The DRAM Controllers (COMET/PAKIT) Page 192 of 676 pnr25.chapt04.01 August 14, 2000 Exit the Self Refresh State 0 Initialize SDRAMs Self Refresh Reserved POR IBM3206K0424 Preliminary Bit(s) Function IBM Processor for Network Resources Description The value of these four bits determines the number of cycles after a bank precharge starts before the bank may be accessed again. To determine the value needed in these bits, take the TRP parameter from the specification of the SDRAM of the part to be used, divide by 7.5 ns, and round up if necessary. If Tdpl is 2, Trp may need to be increased by one to insure correct operation. Suggested values are: X'4' 6.8 ns SDRAM X'2' 6 ns ESDRAM X'2' 7.5 ns ESDRAM The value of these four bits determine the bank cycle time. To determine the value needed in these bits, take the TRC parameter from the specification of the SDRAM of the part to be used, divide by 7.5 ns, and round up if necessary. Suggested values are: X'A' 6.8 ns SDRAM X'5' 6 ns ESDRAM X'5' 7.5 ns ESDRAM Reserved When set to '1', this bit indicates the POR sequence has not been performed on the SDRAMs. This bit automatically resets to '0' when the POR sequence has been performed. This bit reads '1' when the SDRAMs are in the self refresh state. This bit reads '0' when the SDRAMs are not in the self refresh state. This bit is '1' after a POR or reset. The exit self refresh operation must be performed before the POR sequence is initiated. This bit effectively encapsulates the functions provided by bits 2 and 0. Setting this bit to '1' causes the memory controller to take the SDRAMs out of self refresh and perform the POR sequence on them. This bit clears itself. When the initialization is complete, bits 4 and 5 should be a '0'. 15-12 TRP Delay 11-8 TRC Delay 7-6 5 Reserved POR 4 Self Refresh 3 Initialize SDRAMs 2 When set to '1', this bit causes the DRAM controller to initiate the SDRAM power on sequence. This includes an all-banks precharge, following by a command register Start Power on Reset Sequence write that sets the CAS latency to 3, the wrap type to sequential, and the burst length to 1, followed by two refresh cycles. After this sequence is initiated and completed, bit 5 resets and the SDRAMs are ready for normal use. Enter the Self Refresh State When set to '1', this bit causes the SDRAM controller to signal the SDRAMs to go into the self refresh state. All memory activity is suspended. Once the SDRAMs have entered the self refresh state, bit 4 will set. This bit will clear itself. When set to '1', this bit causes the SDRAM controller to signal the SDRAMs to exit the self refresh state. Once the SDRAMs have exited the self refresh state, bit 4 will clear. This bit will clear itself. 1 0 Exit the Self Refresh State pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 193 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 5.7: COMET/PAKIT DRAM Refresh Rate Register This register holds the value of a counter used to control the rate of refresh for the DRAM. Length Type COMET Address PAKIT Address Power On Value Restrictions 32 bits Read/Write XXXX 0928 XXXX 09A8 X'00000820' None Reserved Refresh Rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-12 11-0 Reserved Refresh Rate Function Reserved 9 8 7 6 5 4 3 2 1 0 Description The value of these bits multiplied by 7.5 ns gives the refresh rate. The POR value of X'820' yields a refresh rate of 15.6 ms. The DRAM Controllers (COMET/PAKIT) Page 194 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 5.8: COMET/PAKIT Syndrome Register This register holds the syndrome bits that can be used to isolate the data or check bit in error when ECC is used. When parity is used, this register indicates which of the four bytes of the memory bus had a parity error. Length Type COMET Address PAKIT Address Power On Value Restrictions 32 bits Read/Write XXXX 092C XXXX 09AC X'00000000' None Reserved Syndrome bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 Reserved Function Reserved 9 8 7 6 5 4 3 2 1 0 Description 6-0 Syndrome bits When using ECC, a single bit error can be identified by matching the contents of this register to the corresponding bit in the table below. When using parity, only bits 3-0 are valid and are interpreted as follows: 0000 No parity error 0001 Parity error on bits 7-0 0010 Parity error on bits 15-8 0100 Parity error on bits 23-16 1000 Parity error on bits 31-24 Other Reserved pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 195 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary ECC Syndrome Bits Bit in Error ECC(6) ECC(4) ECC(2) ECC(0) DATA(31) DATA(29) DATA(27) DATA(25) DATA(23) DATA(21) DATA(19) DATA(17) DATA(15) DATA(13) DATA(11) DATA(09) DATA(07) DATA(05) DATA(03) DATA(01) Syndromes '1000000' '0010000' '0000100' '0000001' '0111000' '0110010' '1110000' '1100100' '0100101' '0001101' '0110001' '0011001' '1010001' '1001010' '1000011' '1010100' '0100011' '0001011' '0011010' '0010110' Bit in Error ECC(5) ECC(3) ECC(1) N/A DATA(30) DATA(28) DATA(26) DATA(24) DATA(22) DATA(20) DATA(18) DATA(16) DATA(14) DATA(12) DATA(10) DATA(08) DATA(06) DATA(04) DATA(02) DATA(00) Syndromes '0100000' '0001000' '0000010' N/A '0110100' '0101100' '1101000' '1100010' '0010101' '1100001' '0101001' '1000101' '1001100' '1000110' '1011000' '1010010' '0010011' '0000111' '0100110' '0001110' The DRAM Controllers (COMET/PAKIT) Page 196 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 5.9: COMET/PAKIT Checkbit Inversion Register This register can be used for diagnostic purposes to invert the ECC/parity check bits that are written to memory. Length Type COMET Address PAKIT Address Power On Value Restrictions 32 bits Read/Write XXXX 0930 XXXX 09B0 X'00000000' None Reserved Invert Check bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-0 Reserved Invert Check bits Function Reserved 9 8 7 6 5 4 3 2 1 0 Description Setting any of these bits inverts the corresponding check bit that is written to memory. Only bits 3-0 are valid when parity is used as a checking mechanism. 5.10: COMET/PAKIT Memory Controller Write Enable Register This register must be written to a specific pattern before the Memory Control Register can be written. Length Type COMET Address PAKIT Address Power On Value Restrictions 32 bits Read/Write XXXX 0934 XXXX 09B4 X'000000B4' None Reserved Lock bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-8 7-0 Reserved Lock bits Function Reserved 9 8 7 6 5 4 3 2 1 0 Description This register must be written to a X'4' before the Memory Control Register can be written. This register will POR to X'4', but CRISCO code sets up the memory controller and clears this register back to X'0'. pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 197 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 5.11: COMET/PAKIT Memory Configuration Error Sense Register This register can be read to help determine the source of a memory configuration error. The bits in this register reset automatically once the configuration error is resolved. Length Type COMET Address PAKIT Address Power On Value Restrictions 32 bits Read Only XXXX 0938 XXXX 09B8 X'00000000' None SDRAM Not Properly Initialized SDRAM Not Properly Initialized SDRAM Not Properly Initialized SRAM with ECC Enabled 1 SRAM Invalid Amount of SDRAM Bad Latency Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6 5 4 3 Reserved SDRAM Not Properly Initialized Function Reserved 9 8 7 6 5 4 3 2 Description An SDRAM access has been attempted without the SDRAMs being taken out of self refresh and/or the POR sequence being performed. SDRAM Not Properly Initialized Bits 6-4 of the control register have an invalid value. SDRAM Not Properly Initialized Bits 3-2 of the control register indicate less than 4M of memory. SDRAM Bad Latency Bits 11-10 of the control register indicate a latency of one or a reserved value. The DRAM Controllers (COMET/PAKIT) Page 198 of 676 pnr25.chapt04.01 August 14, 2000 SRAM Bad Latency 0 IBM3206K0424 Preliminary Bit(s) Function IBM Processor for Network Resources Description Bits 27, 13-12 and 3-1 of the control register indicate an invalid SRAM memory size. Acceptable sizes are: 4Mbit x18 unmuxed chip selects of sizes 1M, 2M, 4M. 8Mbit x18 unmuxed chip selects of sizes 2M, 4M, 8M. 16Mbit x18 unmuxed chip selects of sizes 4M, 8M, 16M. 32Mbit x18 unmuxed chip selects of sizes 8M, 16M, 32M. 4Mbit x18 muxed chip selects of sizes 2M, 4M, 8M. 8Mbit x18 muxed chip selects of sizes 4M, 8M, 16M. 16Mbit x18 muxed chip selects of sizes 4M, 16M, 32M. 32Mbit x18 muxed chip selects of sizes 8M, 32M, 64M. 4Mbit x36 unmuxed chip selects of sizes 1M, 2M. 8Mbit x36 unmuxed chip selects of sizes 1M, 2M, 4M. 16Mbit x36 unmuxed chip selects of sizes 2M, 4M, 8M. 32Mbit x36 unmuxed chip selects of sizes 4M, 8M, 16M. 4Mbit x36 muxed chip selects of sizes 1M, 2M, 4M. 8Mbit x36 muxed chip selects of sizes 2M, 4M, 8M. 4Mbit x36 muxed chip selects of sizes 4M, 8M, 16M. 8Mbit x36 muxed chip selects of sizes 8M, 16M, 32M. Bits 17, 14, and 9-8 of the control register indicate ECC is enabled with an SRAM configuration. This is invalid. Bits 11-10 of the control register indicate a latency of three or a reserved value. 2 SRAM Invalid Amount of Memory 1 0 SRAM with ECC Enabled SRAM Bad Latency pnr25.chapt04.01 August 14, 2000 The DRAM Controllers (COMET/PAKIT) Page 199 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 6: ATM Virtual Memory Logic (VIMEM) This entity is responsible for adjustment of all addresses provided to the memory control entities. All addresses can be categorized into three distinct types, based entirely upon the location of the requested address with respect to the three base registers defined in this entity. The three types of addresses are referred to as control, real packet, and virtual packet addresses. All memory requests arriving on the Control Memory bus are handled as Control Memory accesses, and simply have the contents of the Control Memory Base Register subtracted from them before being passed on to the Control Memory Entity. When the processor accesses memory, the cache controller compares the requested address to the Real Packet Memory Base Register and if the address is less than the base register, the request is routed to the Control Memory bus; otherwise it is routed to the Packet Memory bus. All requests arriving on the Packet Memory bus are compared to the Virtual Memory Base Address Register. If the address of the request is less than the base register, the contents of the Real Packet Memory Base Register are subtracted from the address and this address is passed on to the Packet Memory Control Entity. If the requested address is greater than or equal to the base register, a more complex, but flexible scheme is used to determine the real address to provide to the Packet Memory Control Entity. For a detailed explanation of the virtual address generation scheme refer to Virtual Memory Overview on page 248 and the accompanying figures. 6.1: VIMEM Virtual Memory Base Address This register defines the starting address of the virtual address space used to manage incoming and outgoing frames. Any time an access is made to Virtual Memory that falls within the defined bounds of Virtual Memory, the contents of this register are subtracted from the virtual address to derive the true offset into Virtual Memory. This true offset, along with the known length of all virtual buffers, allows the index of the specific virtual buffer to be derived by the Virtual Memory access hardware. This index can then be used to access the real buffer map associated with this virtual buffer. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0D10 X'0040 0000' The start of virtual address space must begin on a 128KB boundary. For this reason, the lowest 17 bits of this register are forced to '0' and are not implemented. Writes of any value to the low 17 bits of this register are ignored, and a read always returns '0' for the low 17 bits. 128KB Boundary Restriction Base Address of Virtual Memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-17 16-0 Description These bits contain the upper 15 bits of the base address of Virtual Memory. 9 8 7 6 5 4 3 2 1 0 These bits are forced to '0' because the Virtual Memory base address must start on a 128K byte boundary. ATM Virtual Memory Logic (VIMEM) Page 200 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.2: On-Chip Memory Base Address This register is used by various entities to generate the base address of the On-Chip Memory (OCM). Length Type Address Power On Value Restrictions 17 bits Read/Write XXXX 0D9C X'0010 0000' The start of virtual address space must begin on a 128KB boundary. For this reason, the lowest 17 bits of this register are forced to '0' and are not implemented. Writes of any value to the low 17 bits of this register are ignored, and a read always returns '0' for the low 17 bits. 6.3: VIMEM Control Memory Base Address This register defines the starting address of the Control Memory address space. Any time an access is made to Control Memory, the contents of this register are subtracted from the address before an access to memory occurs. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0D14 X'0000 0000' The start of real control address space must begin on a 128KB boundary. For this reason, the lowest 17 bits of this register are forced to '0' and are not implemented. Writes of any value to the low 17 bits of this register are ignored, and a read always returns '0' for the low 17 bits. 128KB Boundary Restriction Base Address of Real Control Memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-17 16-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the upper 15 bits of the base address of real Control Memory. These bits are forced to `0' because the real Control Memory base address must start on a 128KB boundary. pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 201 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.4: VIMEM Packet Memory Base Address This register defines the starting address of the Packet Memory address space. Any time an access is made to Packet Memory, the contents of this register are subtracted from the address before an access to memory occurs. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0D18 X'0020 0000' The start of real packet address space must begin on a 128KB boundary. For this reason, the lowest 17 bits of this register are forced to '0' and are not implemented. Writes of any value to the low 17 bits of this register are ignored, and a read always returns `0' for the low 17 bits. This register must also be set up before any of the Real Buffer Base Registers, or the Virtual Buffer Map Registers are written. 128KB Boundary Restriction Base Address of Real Packet Memory 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s0 31-17 16-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the upper 15 bits of the base address of real Packet Memory. These bits will be forced to `0' because the real Packet Memory base address must start on a 128KB boundary. ATM Virtual Memory Logic (VIMEM) Page 202 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.5: VIMEM Virtual Memory Total Bytes This register defines the total number of bytes in the address space being allocated for Virtual Memory. The contents of this register, divided by the configured size of virtual buffers, yields the total number of virtual buffer indices that should be used to initialize POOLS. The value of the indices should range from this calculated value minus one, down to zero. If an address is determined to be above or equal to the Virtual Memory Base Register it is assumed to be a virtual access. If the virtual buffer index derived from the requested address indicates that the virtual buffer space being accessed is above the limit defined by this register, an error is generated. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0D0C X'0001 0000' The maximum value that should be set in this register is (65535 * virtual buffer size). For example, if 64-byte virtual buffers are configured, the maximum value that should be loaded into this register is X'3FFFC0'. Virtual Memory Address Space Not Implemented 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the upper 26 bits of the total number of bytes of address space being reserved for Virtual Memory. These bits are not implemented and are forced to `0' because the Virtual Memory block can only be allocated in increments of the current virtual buffer size (minimum size is 64 bytes). pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 203 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.6: VIMEM Virtual/Real Memory Buffer Size This register defines the total number of bytes to be occupied by each of the virtual or real buffers as well as the spacing from one buffer to the next. Length Type Address Power On Value Restrictions 4 bits Read/Write XXXX 0D04 X'2' Care must be taken to set this register to a large enough value to contain the entire frame being sent as well as certain control information that the hardware stores in the buffer header. For example, if the maximum frame being sent or received is 1024 bytes long, then this register should be set to indicate 2048-byte frames to allow sufficient room for the buffer header information added by the hardware. Virtual/Real Buffer Size 3 2 Bit(s) 1 0 Description These bits contain the encoded four-bit value that defines the virtual/real buffer size. The encoding is as follows: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 Reserved 3-0 ATM Virtual Memory Logic (VIMEM) Page 204 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.7: VIMEM Packet Memory Offset This register contains the number that will be added by the VIMEM access logic to all accesses of real Packet Memory that occur. In a high performance configuration (separate control and packet store), this register should be written to all zeros to indicate that all accesses of real Packet Memory do not require any additional offset to be added. In a medium performance configuration (combined control and packet store), this register should be loaded with a value that indicates the logical partitioning between control and packet storage. If for instance, a single bank of 2 meg was configured and this register was loaded with X'00100000' (1 meg), then all accesses to real Packet Memory would be forced into the 1-meg to 2-meg range. Length Type Address Power On Value: Restrictions 32 bits Read/Write XXXX 0D3C X'0000 0000' This register should only be loaded with a non-zero value if a medium performance configuration (combined control and packet store) exists. The value loaded must be between zero and the maximum of the total amount of memory in the single bank, and it must be on a 128KB boundary. Any time the value in this register is changed, the related base registers must be reloaded because the value loaded into them is affected by the contents of this register during the load operation. The related registers are the Virtual Buffer Map Base Address Register and all five real buffer base registers. 6.8: VIMEM Maximum Buffer Size This register is used by the Virtual Memory logic to determine if an access to a virtual buffer falls into the region of the buffer that can be accessed. If a virtual buffer read or write accesses an offset in a virtual buffer that is greater than the contents of this register, the Virtual Memory logic can be configured to halt and generate an interrupt. The power up value of all ones causes this check to be disabled. This register is intended to provide the user with a means of providing additional protection to accesses of the virtual buffers. For example, if this register is loaded with X'FF8', all memory access up to and including the byte at address X'FFF' are allowed. Any access of offset X'1000' or above will cause an exception. Length Type Address Power On Value Restrictions 17 bits Read/Write XXXX 0D34 X'1 FFF8' All address logic based on this register only recognizes eight-byte words in memory. For this reason, the low three bits of this register are not implemented and are always forced to `0'. pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 205 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.9: VIMEM Access Control Register The bits in this register control the configurable features of the Virtual Memory logic. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Ignore Virtual Buffer Map Serialize Packet Memory 16 bits Read/Write XXXX 0D80 and 84 X'0' None Control Access Priority Fetch Required Map Reserved 15 14 13 12 11 10 Bit(s) 15 9 8 7 6 5 4 3 2 1 0 Description When set, this bit forces the Virtual Memory logic to ignore the virtual buffer map validity indication, and force all maps to appear valid. When set, this bit forces the Virtual Memory logic to fetch the required map entry from storage on every new virtual access. If a Virtual Memory map is updated by the software for any reason, this bit should be toggled on and off after the map is updated and before any virtual access happens to ensure that the Virtual Memory logic is not using stale cached map segments. There is no hardware provided to make sure that the map entry required by the Virtual Memory logic is not contained in one of the BCACH lines. If is the responsibility of the software to ensure that all modified lines are flushed from the cache before the Virtual Memory logic needs them. When set, this bit forces all accesses to Packet Memory to be serialized. When set, this bit causes control accesses to always have priority over packet accesses in a single memory bank configuration. When reset, priority will toggle every time an access is initiated. Reserved 14 13 12 11-0 ATM Virtual Memory Logic (VIMEM) Page 206 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.10: VIMEM Access Status Register This register contains information regarding the current status of the Virtual Memory logic mainly with respect to detected error access conditions. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Non-Recoverable Page Fault Error During Write 17 bits Read/Write XXXX 0D60 and 64 X'0000' None Incorrect Memory Boundary in Base Register Recoverable Page Fault Error During Write Access Off Current Virtual Buffer Map Access Above Current Virtual Buffer Invalid Buffer Size in Base Register 16 15 14 13 12 11 10 Bit(s) 16 9 8 7 6 5 4 3 2 1 Description When set, this bit indicates that the required conditions for the control, packet, and virtual base registers has not been satisfied. The required conditions are: control base < packet base < virtual base When set, this bit indicates that the Virtual Memory logic has detected a page fault error when attempting to read memory. This indicates that no real buffer was available to map into the virtual address space when required. All virtual reads that fail during a page fault regardless of the requesting entity will cause this bit to be set. If the corresponding bit is reset in the lock register, the read operation will complete, but with invalid data. When set, this bit indicates that a Control Memory access was detected that was above the value contained in the Packet Memory Offset Register for single bank configurations, or in a multiple bank configuration in which the high address bits 31 27 were not '0'. When set, this bit indicates that a Packet Memory access of address zero was detected in single bank mode, or that a packet address was detected that contained an address out of range (high five bits non-zero). When set, this bit indicates that the Virtual Memory logic has detected a Virtual Memory operation that attempted to access a map that was not marked as valid. A virtual buffer map is marked valid by the POOLs entity when the buffer is originally acquired, and is marked as invalid when the buffer is freed back to POOLs. Receiving this error indication typically means that the software is trying to use a buffer that has not been acquired through the normal means, or is trying to use a buffer that has already been freed, or that memory has been corrupted. The valid indication that is checked by the hardware is the value X'?656' in the first 16 bits of the eight-byte map entry being accessed. To determine the failing address, the memory control entity can be locked on this type of failure, and the information saved by the memory controller, along with the base registers in this entity can be used to determine which map was being accessed at the time of failure. 15 14 13 12 pnr25.chapt04.01 August 14, 2000 Invalid Value in Map Base Register 0 Generated Buffer Index Too Large Control Memory Access Too High Packed Memory Address Invalid Invalid Configured Buffer Size Page Fault Error During Read `0' Detected in Base Register Required Conditions Not Met Read Caused a Page Fault Invalid Map Reserved ATM Virtual Memory Logic (VIMEM) Page 207 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 11 Description When set, this bit indicates that the Virtual Memory logic has detected a non-recoverable page fault error when attempting to write memory. This indicates that no real buffer was available to map into the virtual address space when required. All virtual writes that fail during a page fault, with the exception of BCACH and RAALL operations, cause this bit to be set. When set, this bit indicates that the Virtual Memory logic has detected a recoverable page fault error when attempting to write memory. This indicates that no real buffer was available to map into the virtual address space when required. Operations from BCACH and RAALL cause this bit to be set instead of the non-recoverable bit because the software can recover from these failures. If a BCACH write to Virtual Memory fails in this manner, the packet header of the frame being updated is updated to indicate the failure. Software can check the field in the packet header to ensure that the DMA operation completed successfully. If such a packet is enqueued to CSKED, the packet header is checked and will prevent the frame from being passed on to the segmentation logic. When CSKED encounters a frame that has had this type of failure, there are several possible ways in which it can be configured (via the CSKED control register) to handle the situation. It can be configured to ignore the error and attempt to transmit the frame anyway (probably not a good way), or the buffer can be freed back to POOLs, or an event can be generated to allow the software to deal with the situation. If a RAALL write to Virtual Memory fails in this manner, the packet currently being received is dropped; it is up to the software to perform any recovery operations that are required. When set, this bit indicates that the Virtual Memory logic has detected a read operation that caused a page fault. This is an invalid condition because the data required for a read operation should have been previously initialized by a write operation, so no page fault should ever occur on a read operation. If the corresponding bit in the lock register is reset, a page is mapped into the current virtual buffer segment and the data that previously was written in that page is returned. This bit can come on in several situations that are not really errors. In these cases, the associated interrupt and lock bits can be reset so that this error does not cause the adapter to halt normal operation. Several of these conditions are: When predictive fill is enabled, a read from the end of a buffer may cause a predictive read that crosses a virtual segment boundary and causes this bit to be set. If a small buffer (fits entirely in the cache) is copied from one IBM3206K0424 buffer to another IBM3206K0424 buffer, a subsequent read of the last bytes written causes this bit to be set if the cache hasn't been flushed between the write and the read, and the last write cycle did not write all four bytes, and the address that is being written/read is within the first 0x20 bytes of a virtual segment. When set, this bit indicates that the Virtual Memory logic has detected an access of a virtual buffer that falls above the limit set by the buffer maximum size register. When set, this bit indicates that the Virtual Memory logic has detected an access that does not fall in one of the currently mapped buffer segments based upon the currently-configured virtual buffer map size. When set, this bit indicates that a virtual access has been detected that used a base register that had an invalid associated buffer size configured in the low order bits. When set, this bit indicates that a virtual access has been detected that used a base register that was not on the correct memory boundary. For example, if a base register is set up to use 2K buffers, then the base register must be set up on a 2K boundary. When set, this bit indicates that a virtual access has been detected that used a base register that contained a value of '0'. Reserved. When set, this bit indicates that the Virtual Memory logic has detected a memory access that resulted in the generation of a buffer index that was greater than the currently configured maximum derived from the VIMEM Virtual Memory total bytes register. When set, this bit indicates that the currently configured size of buffers is invalid. When set, this bit indicates that the map base register contains an invalid value. Two possible causes are that bits 5-2 are not '0' or bits 31-6 are `0'. Preliminary 10 9 8 7 6 5 4 3 2 1 0 ATM Virtual Memory Logic (VIMEM) Page 208 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.11: VIMEM Access Status Interrupt Enable Register This register allows the user to enable interrupts for each of the conditions reported in the VIMEM Access Status Register. Each bit corresponds to the same bit in the status register and when set to '1' generates an interrupt to the processor if the condition is detected. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 17 bits Read/Write XXXX 0D68 and 6C X'1FFFF' None 6.12: VIMEM Memory Lock Enable Register This register allows the user to selectively allow each of the conditions reported in the VIMEM Access Status Register to force a memory lock condition in the memory controller. Each bit corresponds to the same bit in the status register and when set to '1' causes a memory lock if the condition is detected. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 17 bits Read/Write XXXX 0D70 and 74 X'1FFFF' None pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 209 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.13: VIMEM State Machine Current State This register provides feedback to the user regarding the current status of the state machines in VIMEM. One use of this register is to make sure that the required initialization time has expired after loading the segment size register. This is accomplished by reading this register repeatedly until the initialization state machine is in the idle state. Length Type Address Power On Value Restrictions 32 bits Read Only XXXX 0D78 X'1?0' None Current state of the VIMEM Main1 state machine Current state of the VIMEM Main0 state machine 5 4 3 2 1 Current state of the initialization state machine Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-21 20-16 15-13 12-8 7-5 4-0 Reserved Description 9 8 7 Reserved 6 0 These bits contain the current state of the initialization state machine. A value of "1----" indicates that the state machine is in the idle state. Reserved These bits contain the current state of the VIMEM Main1 state machine. A value of "00000" indicates that the state machine is in the idle state. Reserved These bits contain the current state of the VIMEM Main0 state machine. A value of "00000" indicates that the state machine is in the idle state. ATM Virtual Memory Logic (VIMEM) Page 210 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 6.14: VIMEM Last Processor Read Real Address This register provides information to the user about the last read access of virtual Packet Memory by the processor. If a virtual address was accessed, this register contains the real address generated by the Virtual Memory logic that can be used to access the same location. This register is intended mainly as an aid in debugging to make virtual address translation easier. To perform the translation, the processor must read from the desired virtual address: after the read is complete, this register contains the real address that was accessed. The address contained in this register is an offset from the beginning of physical Packet Memory. Length Type Address Power On Value Restrictions Zero bits 32 bits Read Only XXXX 0D7C X'0000 0000' None Real Address Accessed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-27 26-0 These bits always read as `0'. Description 9 8 7 6 5 4 3 2 1 0 After any read operation from the processor to Packet Memory, these bits will contain the real address that was accessed. pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 211 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.15: VIMEM Virtual Buffer Segment Size Register This register, along with the lower four bits of the real buffer base registers, defines the size of the second through 16th real buffers that are concatenated to make up a virtual buffer. Two bits of this register are associated with each real buffer segment and indicate one out of four possible associations. The associative possibilities are shown in the bit table below. Every two bits defines the connection between a particular buffer segment and the real buffer base registers. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0D00 X'0000 0000' Care must be used when setting up this register to ensure that only values that correspond to real buffer sizes that POOLs has also been set up to provide are loaded. A write to this register causes the Virtual Memory logic to calculate the different real buffer boundaries within a virtual buffer. This calculation requires information from the real buffer base registers to determine the size of the different segments making up the virtual buffer. For this reason, it is required that this register be written after the real buffer base registers have been initialized. After writing this register, the software must wait at least 2 ms before accessing Virtual Memory. 14th buffer segment 13th buffer segment 12th buffer segment 11th buffer segment 10th buffer segment 16th buffer segment 15th buffer segment 9th buffer segment 8th buffer segment 7th buffer segment 6th buffer segment 5th buffer segment 4th buffer segment 3th buffer segment 2th buffer segment 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Reserved 0 ATM Virtual Memory Logic (VIMEM) Page 212 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Bit(s) 31-30 29-28 27-26 25-24 23-22 21-20 19-18 17-16 15-14 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Description Defines the 16th buffer segment's connection. Defines the 15th buffer segment's connection. Defines the 14th buffer segment's connection. Defines the 13th buffer segment's connection. Defines the 12th buffer segment's connection. Defines the 11th buffer segment's connection. Defines the 10th buffer segment's connection. Defines the 9th buffer segment's connection. Defines the 8th buffer segment's connection. Defines the 7th buffer segment's connection. Defines the 6th buffer segment's connection. Defines the 5th buffer segment's connection. Defines the 4th buffer segment's connection. Defines the 3rd buffer segment's connection. Defines the 2nd buffer segment's connection. Reserved. The first real buffer is implicitly associated with the virtual buffer, these bits will always be read as '0'. 00 01 10 11 Bit Association Associates this real buffer segment with Real Buffer Base Register 0 Associates this real buffer segment with Real Buffer Base Register 1 Associates this real buffer segment with Real Buffer Base Register 2 Associates this real buffer segment with Real Buffer Base Register 3 pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 213 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 6.16: VIMEM Buffer Map Base Address This register contains the address in Packet Memory at which the buffer map table starts. The buffer map table consists of a variable number of eight-byte entries for each buffer that is allocated in the system. The first 16 bits of each eight-byte entry contains the POOL ID and various status flags associated with this buffer, thus this base register is used in both real and Virtual Memory modes. In Virtual Memory mode, each of the three subsequent 16 bits contains an index which is associated with a buffer size base register using the Buffer Segment Limit Register. The index and buffer size base register are used to determine a real buffer address. If the map size is set to eight bytes, only one eight-byte entry is used for each buffer. If the map size is set to 16 bytes, two eight-byte entries are used for each buffer. If the map size is set to 32 bytes, four eight-byte entries are used for each buffer. If the map size is set to 64 bytes, five eight-byte entries are used for each buffer, and the remaining 24 bytes of the map are unused by the hardware. Length Type Address Power On Value 32 bits Read/Write XXXX 0D08 X'0020 0000' (This value is actually the power up contents of the Packet Memory Real Base Register added to the power up contents of this register (X'00000000') due to the automatic address adjustment explained below.) The base address for the buffer map must begin on a 64-byte boundary. When a base register is written, the hardware performs an automatic adjustment to the address using the contents of the Packet Memory Real Base Register, and the Packet Memory Offset Register. This results in the actual value being stored, not being the value that is written by the program. This is done to make the virtual accesses that use the base register execute more quickly. The reverse adjustment is made when the read operation is performed, so that it appears to the program no different than a normal operation. Care must be taken, however, to ensure that both the Packet Memory Real Base Register and the Packet Memory Offset Register are set-up before any of the base registers are written. If the Packet Memory Base Register or the Packet Memory Offset Register are changed, Packet Memory should not be accessed until all the base registers have been written again. Map Entry Size 3 2 1 0 Restrictions Starting Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5-2 Defines the starting address of the buffer map Reserved, should be written with `0' Description 9 8 7 6 5 4 ATM Virtual Memory Logic (VIMEM) Page 214 of 676 Reserved pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Defines the size of each map entry: 00 8 bytes 01 16 bytes 10 32 bytes 11 64 bytes Description IBM Processor for Network Resources 1-0 6.17: VIMEM Real Buffer Base Addresses These registers contain the address in Packet Memory at which a block of memory begins that is used to provide a given size buffer. In general, the block allocated must be large enough to contain as many buffers as will be freed to POOLS on initialization. However, for Real Buffer Base 4, the size of the block reserved must be large enough so that one buffer is available for each of the virtual buffers freed to POOLS. These buffers must not be freed to POOLS because they are implicitly used as the first real buffer segment for each of the virtual buffers. If a given base register (and associated buffer size) is not used, the low four bits of the register should be set to X'F' to ensure that accesses of this buffer size are detected and flagged as an error. When using real memory mode (controlled in POOLS), all of these base registers are unused with the exception of base register zero, which contains the base address for all real memory buffers. In real mode, the low four bits of base register zero are of no significance. The size of the real buffers is controlled through the Buffer Size Register. Buffer Size Length Type Address 0 32 bits Read/Write XXXX 0D20 1 32 bits Read/Write XXXX 0D24 X'0020 000F' 2 32 bits Read/Write XXXX 0D28 X'0020 000F' 3 32 bits Read/Write XXXX 0D2C X'0020 000F' 4 (implicit) 32 bits Read/Write XXXX 0D30 X'0020 000F' Power on Value X'0020 000F' Restrictions The base address for any given buffer size must begin on a boundary that is equal to the buffer size. For example, the base address for 128-byte buffers must be on a 128-byte boundary, and the base address for 4096-byte buffers must be on a 4096-byte boundary. When a base register is written, the hardware performs an automatic adjustment to the address using the contents of the Packet Memory real base register and the Packet Memory offset register. This results in the actual value being stored, not being the value that is written by the program. This is done to make the memory accesses that use the base register execute quicker. The reverse adjustment is made when the read operation is performed, so that it appears to the program no different than a normal operation. Care must be taken however to ensure that the Packet Memory Real Base Register and the Packet Memory Offset Register are set-up before any of the base registers are written. If the Packet Memory Base Register or the Packet Memory Offset Register is changed, Packet Memory should not be accessed until all the base registers have been written again. The power on value of these registers is actually the power on value of the Packet Memory Real Base Register added to the contents of the Packet Memory Offset Register added to the original contents of these registers (X'0000000F'). pnr25.chapt04.01 August 14, 2000 ATM Virtual Memory Logic (VIMEM) Page 215 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Real BufferSize 4 3 2 1 0 pnr25.chapt04.01 August 14, 2000 Starting Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Bit(s) 31-6 5-4 Description 8 7 6 5 Defines the starting address in Packet Memory of the memory block used to provide real buffers of defined size Reserved (User should write zeros and ignore read value) Defines the size of the real buffers in this block of memory with the following encoding: 0000 64 bytes 0001 128 bytes 0010 256 bytes 0011 512 bytes 0100 1024 bytes 0101 2048 bytes 0110 4096 bytes 0111 8192 bytes 1000 16384 bytes 1001 32768 bytes 1010 65536 bytes 1011 131072 bytes 1100 -1111 Reserved 3-0 ATM Virtual Memory Logic (VIMEM) Page 216 of 676 Reserved IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 7: ATM Packet/Control Memory Arbitration Logic (ARBIT) This section contains descriptions of the registers used by the arbiter logic. 7.1: ARBIT Control Priority Resolution Register High The bits in this register define the priority of requesting entities to Control Memory. Length Type Address Restrictions Power On Value Priority Level D Priority Level E 28 bits Read/Write XXXX 0E00 None X'EDC BA98' Priority Level C Priority Level B Priority Level A Priority Level 9 Priority Level 8 5 4 3 2 1 0 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 9 8 7 6 Description The value loaded into these bits defines which entity will be requesting at priority level E (lowest priority). Value encoding is: F: Reserved 7: SEGBF E: CHKSM 6: TXLCD D: PCORE LO 5: RXLCD C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: RXXLT 1: BCACH HI 8: RXQUE 0: POOLS HI The value loaded into these bits defines which entity will request at priority level D. Value encoding is as listed in the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level C. Value encoding is as listed in the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level B.Value encoding is as listed in the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level A. Value encoding is as listed in the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level 9. Value encoding is as listed in the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level 8. Value encoding is as listed in the description of bits 27-24. 27-24 23-20 19-16 15-12 11-8 7-4 3-0 pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 217 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.2: ARBIT Control Priority Resolution Register Low The bits in this register define the priority of requesting entities to Control Memory. Length Type Address Restrictions Power On Value Priority Level 7 Priority Level 6 32 bits Read/Write XXXX 0E04 None X'7654 3210' Priority Level 5 Priority Level 4 Priority Level 3 Priority Level 2 Priority Level 1 Priority Level 0 5 4 3 2 1 0 pnr25.chapt04.01 August 14, 2000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Description 9 8 7 6 31-28 The value loaded into these bits defines which entity will request at priority level 7. Value encoding is: F: Reserved 7: SEGBF E: CHKSM 6: TXLCD D: PCORE LO 5: RXLCD C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: RXXLT 1: BCACH HI 8: RXQUE 0: POOLS HI The value loaded into these bits defines which entity will request at priority level 6. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 5. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 4. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 3. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 2. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 1. For value encoding, see the description of bits 31-28. The value loaded into these bits defines which entity will request at priority level 0 (highest priority). For value encoding, see the description of bits 31-28. 27-24 23-20 19-16 15-12 11-8 7-4 3-0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 218 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.3: ARBIT Control Error Mask Register The bits in this register control whether ARBIT detected error conditions on an entity's interface will lock the Control Memory subsystem. Bits in this register also control the locking of the Control Memory subsystem based on Control Memory, Packet Memory, Virtual Memory, and BCACH detected error conditions. Resetting the appropriate bit will force errors from that source to be ignored. Length Type Address Power On Value Restrictions 20 bits Clear/Set XXXX 0E08 and 0C X'FFFFF' None Bit(s) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ARBIT detected packet errors PCORE errors POOLS errors BCACH errors VIMEM errors PAKTT errors COMET errors CHKSM PCORE BCACH POOLS CSKED RXXLT RXQUE SEGBF TXLCD RXLCD GPDMA DMAQS Bit Name/Function pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 219 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.4: ARBIT Control Error Source Register The bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. Length Type Address Power On Value Restrictions 20 bits Clear/Set XXXX 0E18 and 1C X'00000' Bits 17 through 12 are driven from external entities and cannot be set or reset in this register. They must be set or reset in the entity of origin. Bit Name/Function Reserved ARBIT detected packet errors PCORE errors POOLS errors BCACH errors VIMEM errors PAKTT errors COMET errors CHKSM PCORE BCACH POOLS CSKED RXXLT RXQUE SEGBF TXLCD RXLCD GPDMA DMAQS Bit(s) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 220 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.5: ARBIT Control Winner Register The bits in this register indicate which entity currently owns Control Memory. Length Type Address Power On Value Restrictions 32 bits Read XXXX 0E2C X'F' None Control Winner B Control Winner A 5 4 3 2 1 0 Lock Set/Reset Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Description 9 8 7 6 31 For performance reasons, two sets of operational latches (bank A and bank B) exist in the arbiter for Control Memory. When set, this bit indicates that the B latches are active, and when reset indicates that the A latches are active. When this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. If this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that was accessing memory most recently. Reserved. Will read '0'. Control winner B. Control winner A. F: Reserved E: CHKSM D: PCORE LO C: BCACH LO B: POOLS LO A: CSKED 9: RXXLT 8: RXQUE 7: 6: 5: 4: 3: 2: 1: 0: SEGBF TXLCD RXLCD GPDMA DMAQS PCORE HI BCACH HI POOLS HI 30-8 7-4 3-0 pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 221 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.6: ARBIT Control Address Register A If latch bank A is active, the bits in this register indicate the last address that was used to access Control Memory. Length Type Address Power On Value Restrictions 32 bits Read XXXX 0E10 X'0000 0000' None Last Address Provided by Arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the last address provided by the arbiter to the Control Memory controller. 7.7: ARBIT Control Address Register B If latch bank B is active, the bits in this register indicate the last address that was used to access Control Memory. Length Type Address Power On Value Restrictions 32 bits Read XXXX 0E20 X'0000 0000' None Last Address Provided by Arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the last address provided by the arbiter to the Control Memory controller. ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 222 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.8: ARBIT Control Length Register The bits in this register indicate the last length that was used to access Control Memory. Length Type Address Power On Value Restrictions Latch Bank B Length 16 bits Read XXXX 0E14 X'0000 0000' None Latch Bank A Length 15 14 13 12 11 10 Bit(s) 15-8 7-0 9 8 7 6 5 4 3 2 1 0 Description These bits contain the length used to access Control Memory through latch bank B. These bits contain the length used to access Control Memory through latch bank A. pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 223 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.9: ARBIT Control Lock Entity Enable Register The value programmed in this register controls what entity, if any, has access to Packet Memory immediately after memory has locked. This register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. Length Type Address Power On Value Restrictions Bit Map Value 4 bits Read/Write XXXX 0E28 X'F' None 3 2 Bit(s) 1 0 Description The value in these bits map to the following entities: F: Reserved 7: SEGBF E: CHKSM 6: TXLCD D: PCORE LO 5: RXLCD C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: RXXLT 1: BCACH HI 8: RXQUE 0: POOLS HI 3-0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 224 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.10: ARBIT Control Config Register The bits in this register control the operation of the Control Memory arbiter. Length Type Address Power On Value Restrictions Arbit Entity State 4 bits Clear/Set XXXX 0E38 and 3C X'0' None 3 2 Bit(s) 3-2 1 1 Set/Reset 0 Description Reserved This bit controls the arbit entity state debug mux. When set, the incoming entity requests and outgoing acknowledges are routed to the entity state pins. When reset, the internal state information is routed to the entity state pins. When set, this bit forces all operations to Control Memory to be serialized. An operation from one entity must be entirely complete before an operation from another entity will be started. When reset, if the memory operation in process can be overlapped, a second operation will be started before the first operation is complete. 7.11: ARBIT Packet Priority Resolution Register High The bits in this register define the priority of requesting entities to Packet Memory. Length Type Address Power On Value Restrictions 28 bits Read/Write XXXX 0E80 X'EDC BA98' None pnr25.chapt04.01 August 14, 2000 Reserved 0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 225 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Bit(s) 27-24 Description The value loads into these bits defines which entity will request at priority level E (lowest priority). Value encoding is: F: Reserved 7: SEGBF E: CHKSM 6: Reserved D: PCORE LO 5: RXAAL C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: Reserved 1: BCACH HI 8: RXQUE 0: POOLS HI The value loaded into these bits defines which entity will request at priority level D. For value encoding, see the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level C. For value encoding, see the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level B. For value encoding, see the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level A. For value encoding, see the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level 9. For value encoding, see the description of bits 27-24. The value loaded into these bits defines which entity will request at priority level 8. For value encoding, see the description of bits 27-24. 23-20 19-16 15-12 11-8 7-4 3-0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 226 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.12: ARBIT Packet Priority Resolution Register Low The bits in this register define the priority of requesting entities to Packet Memory. Length Type Address Restrictions Power On Value 32 bits Read/Write XXXX 0E84 None X'7654 3210' Priority Level 7 Priority Level 6 Priority Level 5 Priority Level 4 Priority Level 3 Priority Level 2 Priority Level 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Description 9 8 7 6 5 4 3 2 Priority Level 0 1 0 31-28 The value loaded into these bits define which entity will be requesting at priority level 7. Value encoding is: F: Reserved 7: SEGBF E: CHKSM 6: Reserved D: PCORE LO 5: RXAAL C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: Reserved 1: BCACH HI 8: RXQUE 0: POOLS HI The value loaded into these bits defines which entity will request at priority level 6. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 5. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 4. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 3. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 2. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 1. For value encoding, see the description of bits 31-28 above. The value loaded into these bits defines which entity will request at priority level 0 (highest priority). For value encoding, see the description of bits 31-28 above. 27-24 23-20 19-16 15-12 11-8 7-4 3-0 pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 227 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.13: ARBIT Packet Entity Error Mask Register The bits in this register control whether ARBIT detected error conditions on an entity's interface will lock the Packet Memory subsystem. Bits in this register also control the locking of the Packet Memory subsystem based on Control Memory, Packet Memory, Virtual Memory, and BCACHE detected error conditions. Resetting the appropriate bit will force errors from that source to be ignored. Length Type Address Power On Value Restrictions 18 bits Clear/Set XXXX 0E88 and 8C X'FFFFF' None Bit(s) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Re-arbitration failure ARBIT detected control errors PCORE error POOLS error BCACH error VIMEM error PAKTT error COMET error CHKSM LO PCORE LO BCACH LO POOLS LO CSKED Reserved RXQUE SEGBF Reserved RXAAL GPDMA DMAQS Bit Name/Function ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 228 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.14: ARBIT Packet Error Source Register The bits in this register provide feedback to indicate the source of errors that have been detected by the memory subsystem. Length Type Address Power On Value Restrictions 20 bits Clear/Set XXXX 0E98 and 9C X'00000' Bits 17, 16, and 11 through 14 are driven from external entities and can not be set/reset in this register. They must be set/reset in the entity of origin. BCACHE Error COMET Error PCORE Error POOLS Error VIMEM Error Control Error Rearb. Error PAKIT Error CHKSM LO PCORE LO BCACH LO POOLS LO Reserved Reserved GPDMA 1 19 18 17 16 15 14 13 12 11 10 Bit(s) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 Bit Name/Function Rearbitration failure. Rearbitration detected while already handling rearbitration condition. This condition would indicate that the priorities programmed in the priority resolution logic were incorrectly programmed and POOLS HIGH was not given the highest priority. ARBIT detected control errors PCORE error POOLS error BCACH error VIMEM error PAKTT error COMET error CHKSM LO PCORE LO BCACH LO POOLS LO CSKED Reserved RXQUE SEGBF Reserved RXAAL GPDMA DMAQS pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) DMAQS 0 RXQUE CSKED SEGBF RXAAL Page 229 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.15: ARBIT Packet Winner Register The bits in this register indicate which entity currently owns Packet Memory. Length Type Address Power On Value Restrictions Active Set/Reset 32 bits Read XXXX 0EAC X'F' None Packet Winner B Packet Winner A 5 4 3 2 1 0 pnr25.chapt04.01 August 14, 2000 Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 Reserved. Description 9 8 7 6 30 For performance reasons, two sets of operational latches (bank A and bank B) exist in the arbiter for Packet Memory. When set, this bit indicates that the B latches are active, and when reset it indicates that the A latches are active. When this bit is set and memory is locked, bits 7-4 of this register contain a value that indicates the entity that most recently was accessing memory. If this bit is reset and memory is locked, bits 3-0 of this register contain a value that indicates the entity that was accessing memory most recently. Reserved. Will read '0'. Packet winner B. Packet winner A. Value encoding is: F: Reserved E: CHKSM D: PCORE LO C: BCACH LO B: POOLS LO A: CSKED 9: Reserved 8: RXQUE 29-8 7-4 3-0 7: 6: 5: 4: 3: 2: 1: 0: SEGBF Reserved RXAAL GPDMA DMAQS PCORE HI BCACH HI POOLS HI ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 230 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.16: ARBIT Packet Address Register A If latch bank A is active, the bits in this register indicate the last address that was used to access Packet Memory. Length Type Address Power On Value Restrictions 32 bits Read XXXX 0E90 X'0000 0000' None Last Address Provided by Arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the last address provided by the arbiter to the Packet Memory controller. 7.17: ARBIT Packet Address Register B If latch bank B is active, the bits in this register indicate the last address that was used to access packet memory. Length Type Address Power On Value Restrictions 32 bits Read XXXX 0EA0 X'0000 0000' None Last Address Provided by Arbiter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 These bits contain the last address provided by the arbiter to the Packet Memory controller. pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 231 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.18: ARBIT Packet Length Register The bits in this register indicate the last length that was used to access Packet Memory. Length Type Address Power On Value Restrictions Latch Bank B Length 16 bits Read XXXX 0E94 X'0000 0000' None Latch Bank A Length 15 14 13 12 11 10 Bit(s) 15-8 7-0 9 8 7 6 5 4 3 2 1 0 Description These bits contain the length used to access Packet Memory through Latch Bank B These bits contain the length used to access Packet Memory through Latch Bank A ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 232 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.19: ARBIT Packet Lock Entity Enable Register The value programmed in this register controls what entity, if any, has access to Packet Memory immediately after memory has locked. This register powers up to a value that will not allow any entity to access memory after a lock condition until the lock condition has been properly cleared. Length Type Address Power On Value Restrictions Bit Map Value 4 bits Read/Write XXXX 0EA8 X'F' None 3 2 Bit(s) 1 0 Description The value in these bits map to the following entities: Value encoding is: F: Reserved 7: SEGBF E: CHKSM 6: Reserved D: PCORE LO 5: RXAAL C: BCACH LO 4: GPDMA B: POOLS LO 3: DMAQS A: CSKED 2: PCORE HI 9: Reserved 1: BCACH HI 8: RXQUE 0: POOLS HI 3-0 pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 233 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 7.20: ARBIT Packet Config Register The bits in this register control the operation of the Packet Memory arbiter. Length Type Address Power On Value Restrictions Forces All Operations To Packet Memory To Be Serialized 4 bits Clear/Set XXXX 0EB8 and BC X'0' None 3 2 Bit(s) 3-2 1 Arbit Entity State Debug Mux 1 Reserved 0 Description Reserved This bit controls the arbit entity state debug mux. When set, the incoming entity requests and outgoing acknowledges are routed to the entity state pins. When reset, the internal state information is routed to the entity state pins. When set, this bit forces all operations to Packet Memory to be serialized. An operation from one entity must be entirely complete before an operation from another entity will be started. When reset, if the memory operation in process can be overlapped, a second operation will be started before the first operation is complete. 0 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 234 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.21: ARBIT Performance Counter Control The bits in this register determine what events are counted by the memory performance counters. This 32-bit register is divided into four 8-bit values, one value for each of the counters. The eight bits determine what memory event is counted by the associated counter. Length Type Address Power On Value Restrictions Memory event counted by performance counter 3 32 bits Read/Write XXXX 0EB8 and BC X'9F1E 8000' None Memory event counted by performance counter 2 Memory event counted by performance counter 1 Memory event counted by performance counter 1 9 8 7 6 5 4 3 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 0 pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 235 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Bit(s) Description The value loaded into these bits defines what memory event is counted by performance counter 3. These bits are defined as follows: Bit 7: When reset, Control Memory events are counted, when set, Packet Memory events are counted by the associated counter. Bit 6: Reset the associated counter to 0. This bit will be reset by the hardware, during the same cycle that the counter is being reset. Bit 5: Reserved Bits 4-0: Cycle type, encoded as: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Any Request Any Request between 0 and 4 bytes Any Request between 5 and 8 bytes Any Request between 9 and 16 bytes Any Request between 17 and 32 bytes Any Request between 33 and 64 bytes Any Request between 65 and 128 bytes Reserved Any Read Request Any Read Request between 0 and 4 bytes Any Read Request between 5 and 8 bytes Any Read Request between 9 and 16 bytes Any Read Request between 17 and 32 bytes Any Read Request between 33 and 64 bytes Any Read Request between 65 and 128 bytes Reserved Any Write Request Any Write Request between 0 and 4 bytes Any Write Request between 5 and 8 bytes Any Write Request between 9 and 16 bytes Any Write Request between 17 and 32 bytes Any Write Request between 33 and 64 bytes Any Write Request between 65 and 128 bytes Reserved Read op latency Write op latency Reserved Reserved Reserved Reserved Hold Current Count Every Cycle 31-24 23-16 15-8 7-0 The value loaded into these bits define what memory event is counted by performance counter 2. The value loaded into these bits define what memory event is counted by performance counter 1. The value loaded into these bits define what memory event is counted by performance counter 0. ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 236 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 7.22: Arbit Memory Performance Counter These registers count memory events as defined in the ARBIT performance counter control register. Length Type Address 32 bits Read/Write Counter 0 Counter 1 Counter 2 Counter 3 Power On Value Restrictions X'0000 0000' None Number of times the event selected in the performance counter control register has occurred XXXX 0EC0 XXXX 0EC4 XXXX 0EC8 XXXX 0ECC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 These bits count the number of times that the event selected in the performance counter control register has occurred. pnr25.chapt04.01 August 14, 2000 ATM Packet/Control Memory Arbitration Logic (ARBIT) Page 237 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 8: The Bus DRAM Cache Controller (BCACH) This entity provides the caching function for data transfers on the Control Processor bus. The array is organized in four logically separate cache lines, any of which can be used for processor accesses or master/slave DMA accesses. The cache is accessible on byte boundaries on the Control Processor side; access of this entity to COMET is performed on 64-bit (word) boundaries. The address tags of each of the four 32-byte cache lines are compared to the requesting address to select the bank to be used to satisfy the Control Processor bus operation. Streaming accesses of the cache use a predictive look-ahead scheme to fill the cache for read operations from Packet Memory. Under normal conditions, a single cache miss will be expected at the start of each DMA read operation. This cache miss will initiate a read operation from Packet Memory to fetch the requested data and enough additional data to fill the remainder of the cache line. If the requested data is in the last N bytes (N is programmable via the BCACH control register) of the cache line, the read operation to COMET will be extended to fill the next cache line with sequential data as well. This same programmable value is used to determine when to initiate the next sequential cache line fill operation during a DMA read operation. During non-aligned write operations to Packet Memory, BCACH will perform read/modify/write cycles to PAKIT. Processor accesses operate without predictive caching. When a cache miss occurs, a COMET read operation will be initiated to fetch the 32-byte block of data that contains the requested data. The data read from COMET will be loaded into the `Least Recently Used' cache line. This section contains descriptions of the registers used by the Bus Cache logic. The Bus DRAM Cache Controller (BCACH) Page 238 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 8.1: BCACH Control Register The bits in this register control the various functions provided by the cache logic. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Clear/Set XXXX 1000 and 004 X'2000 0000' None Force predictive fill/flush for non-streaming accesses Enable Caching Packet Memory Reads Enable Caching Packet Memory Writes Enable Ping Pong Buffer Support Disable Locking on Collisions BCACH Diagnostic Mode Ack RXQUE Immediately Retry Delayed Accesses Enable automatic flush Use RXQUE Advice Flush Cache Line 3 Flush Cache Line 2 Flush Cache Line 1 Flush Cache Line 0 Reserved Predictive Fill Threshold Timed Flush Time Out Value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 Function Enable Caching Packet Memory Reads Enable Caching Packet Memory Writes 9 8 7 6 5 4 3 2 1 0 Description When this bit is set, reads of Packet Memory will be cached. When this bit is set, writes to Packet Memory will be cached. When this bit is set, and the cache is enabled, any access of Packet Memory that cannot be satisfied within one cycle will be terminated by the cache with a retry indication. The accessing device is expected to allow competing devices a chance to gain access to the bus and then retry the same operation. When this bit is set, diagnostic mode is enabled and reads and writes of the BCACH array from the processor are enabled. When reset, reads from the processor will return X'BADDBADD' and writes will have no affect. Care must be taken when performing writes from the processor: if a cache line fill operation is in process and a write is performed from the processor that writes to the same address in the array as is being written from the fill operation, results are indeterminate. Setting this bit forces a flush of cache line 3 if it is dirty. This bit is reset by the hardware when the flush completes. Setting this bit forces a flush of cache line 2 if it is dirty. This bit is reset by the hardware when the flush completes. 29 Retry Delayed Accesses 28 BCACH Diagnostic Mode 27 26 Flush Cache Line 3 Flush Cache Line 2 pnr25.chapt04.01 August 14, 2000 The Bus DRAM Cache Controller (BCACH) Page 239 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 25 24 Function Flush Cache Line 1 Flush Cache Line 0 Description Setting this bit forces a flush of cache line 1 if it is dirty. This bit will be reset by the hardware when the flush completes. Setting this bit forces a flush of cache line 0 if it is dirty. This bit will be reset by the hardware when the flush completes. When set, advice from the receive queue entity causes the cache logic to fill a line with the data from the start of the buffer that was just dequeued by the software. This should improve performance by having the receive data available when the processor accesses the buffer after the dequeue. To make best use of this feature, the code should access the receive data shortly after the dequeue to avoid the data in the cache line from becoming stale and being invalidated due to other cache functions. When reset, advice from the receive queue entity will be ignored. When reset, advice from the receive queue entity is acknowledged immediately even if the cache is not able to perform the requested data fetch. In this case, the advice is lost, and the cache will not fetch the data until the processor requests it again. When set, the advice from the receive queue entity is not acknowledged until the cache has actually latched the advice information. This guarantees that the advice will be used, but may cause delays in the Receive Queue entity's processing. When reset, this bit disables the two-line ping pong feature associated with consistent sequential cache accesses. When set, a series of sequential accesses to Packet Memory that would normally require more than two cache lines to be satisfied is limited to only two cache lines, regardless of the length of the transfer. This feature is intended to improves cache performance by preventing cache lines that contain the most recently used processor data from being flushed due to a long streaming access. When set, this bit prevents detected collisions from locking up the memory control entity. When set, this bit enables the automatic flush feature of the cache. The auto flush feature forces a flush of a cache line to be performed if a sequential write of the last 2 locations in the cache line is detected. When set, this bit forces the predictive fill/flush logic to operate on all accesses of the cache rather than just streaming accesses. When reset, the predictive fill logic will only be activated for streaming accesses in the cache. Reserved. These bits set the threshold at which a predictive fill will be initiated. If all of these bits are set to `1', a predictive fill will be initiated on the first streaming access of a cache line, regardless of which byte in the line is accessed. If this field is set to X'3F' a predictive fill will be initiated on any streaming access of bytes at offset X'2' through X'7' in the cache line. If this field is set to X'03' a predictive fill will be initiated on any streaming access of bytes at offset X'6' or X'7' in the cache line. Setting the field to all '0's will disable predictive fills. These bits control the time-out value used to monitor dirty cache lines for inactivity. The value loaded into these eight bits is the number of 240 ns ticks that can occur without any activity in a dirty cache line before the cache logic will force a flush of the line to main memory. Setting these bits to all '0's disables the timed flush feature. Preliminary 23 Use RXQUE Advice 22 Ack RXQUE Immediately 21 Enable Ping Pong Buffer Support 20 19 Disable Locking on Collisions Enable automatic flush 18 17-16 Force predictive fill/flush for non-streaming accesses Reserved 15-8 Predictive Fill Threshold 7-0 Timed Flush Time Out Value The Bus DRAM Cache Controller (BCACH) Page 240 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 8.2: BCACH Status Register The bits in this register reflect the current status of the cache. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions POOLS invalidation of dirty lines 8 bits Clear/Set XXXX 1008 and 00C X'00' None Negative Ack from VIMEM Read Hit on Multiple Lines Write Hit on Multiple Lines Collision on Cache Line 3 Collision on Cache Line 2 Collision on Cache Line 1 1 7 6 Bit(s) 5 4 3 2 Function Collision on Cache Line 0 0 Description When this bit is set, it indicates that POOLS requested that the cache logic invalidate a line that was dirty. This is usually an indication that a buffer was freed by the software before data written out to the buffer had been flushed to memory. This may or may not be an error condition. When this bit is set, the cache logic has detected a write hit to multiple lines. This indicates an internal logic error in the cache. When this bit is set, the cache logic has detected a read hit to multiple lines. This indicates an internal logic error in the cache. When set, the cache logic has detected a negative acknowledgment from the Virtual Memory Logic entity. This indicates that a virtual buffer boundary was crossed and a new real buffer was needed to map the requested address space into, but no real buffer was available. In addition to setting this status bit, the cache logic writes the pattern X'zzzzzBAD' into the header of the packet at offset X'C' where zzzzz is the offset of the failing write into the packet. When this bit is set, the cache logic has detected a collision in cache line 3. This is a situation where another entity in IBM3206K0424 was accessing an area of memory that was contained in one of the cache lines that was dirty. Further information for problem diagnosis is latched in the memory controller logic when this condition is detected. When this bit is set, the cache logic has detected a collision in cache line 2. When this bit is set, the cache logic has detected a collision in cache line 1. When this bit is set, the cache logic has detected a collision in cache line 0. 7 POOLS invalidation of dirty lines 6 5 Write Hit on Multiple Lines Read Hit on Multiple Lines 4 Negative Ack from VIMEM 3 Collision on Cache Line 3 2 1 0 Collision on Cache Line 2 Collision on Cache Line 1 Collision on Cache Line 0 pnr25.chapt04.01 August 14, 2000 The Bus DRAM Cache Controller (BCACH) Page 241 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 8.3: BCACH Interrupt Enable Register The low eight bits in this register allow the user to selectively determine which bits in the BCACH status register will cause processor interrupts. A `0' in a bit position masks interrupts from the corresponding bit location in the BCACH status register. A `1' in a bit position allows interrupts for the corresponding bit in the BCACH status register. The high eight bits in this register allow the user to selectively determine which bits in the BCACH status register will lock the cache. A `1' in any bit position forces the cache to lock if the corresponding bit is set in the BCACH status register. If the cache locks, all status regarding the cache lines is maintained until the cache enable bits in the control register are turned off. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 16 bits Clear/Set XXXX 1010 and 014 X'FFFF' None 8.4: BCACH High Priority Timer Value This register defines the number of 15 ns cycles that will pass from the time that a valid PCI bus request is raised to BCACH until BCACH will raise its high priority request to the memory controllers. A value of `0' in this register disables this function completely. Length Type Address Power On Value Restrictions Number of 15 ns Cycles 8 bits Read/Write XXXX 1040 X'40' None 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Specifies the number of 15 ns cycles before a high priority request. For example, if bit 3 is set to `1' and all others are set to `0', then 6 cycles (120 ns) will pass between receipt of request and sending request to controllers. The Bus DRAM Cache Controller (BCACH) Page 242 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 8.5: BCACH Line Tag Registers These registers are useful only in diagnostic testing of the cache logic. Each register will contain the tag value for the data contained in that particular cache line. Length Type Address 32 bits Read Only Tag Number 0 Tag Number 1 Tag Number 2 Tag Number 3 Power on Value Restrictions X'0000 0000' None Modulo Read Fill Op. XXXX 1080 XXXX 10A0 XXXX 10C0 XXXX 10C0 32-bit Memory Line Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-5 Description 9 8 7 6 5 4 3 2 Reserved 1 0 These bits contain the address of the 32-byte line of memory contained in the cache line. In an attempt to provide the fastest possible access to data in memory, the 8 byte word in memory that contains the requested read data is accessed first and all other entries in the cache line are filled by wrapping back to the beginning of the cache line if required. These two bits contain the starting address for the modulo read fill operation. They will also contain the least significant address bits when a cache line is initially written to. Will always be returned as `0'. 4-3 2-0 pnr25.chapt04.01 August 14, 2000 The Bus DRAM Cache Controller (BCACH) Page 243 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 8.6: BCACH Line Valid Bytes Register These registers are useful only in diagnostic testing of the cache logic. Each register will contain a bit significant flag indicating which bytes in the 32-byte cache line are valid. All of these bits will be active after a cache line fill operation has occurred, but any combination of these bits can be valid after the processor has performed a write operation to memory. Length Type Address 32 bits Read Only Tag Number 0 Tag Number 1 Tag Number 2 Tag Number 3 Power on Value Restrictions X'0000 0000' None Cache Line Fill Operation Set/Reset XXXX 1084 XXXX 10A4 XXXX 10C4 XXXX 10E4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 Each bit indicates whether the associated byte in the cache line contains valid data or not. If the bit is set, the cache line contains valid data and a fetch from main storage is not required to fulfill a request for a read from this location. If the bit is reset, a read of the associated location will require a cache line fill operation before the request can complete. The Bus DRAM Cache Controller (BCACH) Page 244 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 8.7: BCACH Line Status Register These registers are useful only in diagnostic testing of the cache logic. Each register will contain a bit significant flag indicating the current status of the associated cache line. Length Type Address 32 bits Read Only Tag Number 0 Tag Number 1 Tag Number 2 Tag Number 3 Power on Value Tag Number 0 Tag Number 1 Tag Number 2 Tag Number 3 Restrictions None Loaded by RXQUE Advice XXXX 1088 XXXX 10A8 XXXX 10C8 XXXX 10E8 X'0000 0000' X'0000 0010' X'0000 0020' X'0000 0030' Loaded by Predictive Fill Loaded by PCI Read Loaded by PCI Write Reserved Valid Tag Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30-12 11 10 9 8 7-6 5-4 Valid Tag Reserved Loaded by PCI Read Loaded by Predictive Fill Loaded by RXQUE Advice Loaded by PCI Write Reserved LRU bits Function 9 8 7 6 5 4 3 2 Dirty bits 1 0 Description When set, this indicates that the associated tag register contains a valid tag. Reserved When set, this bit indicates that the associated tag register was loaded due to a read request from the PCI bus When set, this bit indicates that the associated tag register was loaded due to a predictive fill request When set, this bit indicates that the associated tag register was loaded due to advice from the receive queue entity When set, this bit indicates that the associated tag register was loaded due to a write request from the PCI bus Reserved These bits indicate the cache lines current position with respect to the least recently used algorithm. A value of `0' indicates it is the most recently used while a value of `3' indicates the least recently used. pnr25.chapt04.01 August 14, 2000 The Bus DRAM Cache Controller (BCACH) LRU bits Page 245 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Description These bits, when set, indicate that the associated eight-byte word of the cache line is dirty. This information is used on cache line flushes, to lower memory utilization, by eliminating non-dirty word flushes from the cache line flush operation. For example if these bits contain a X'1', only the eight-byte word at offset zero in the cache line is dirty, so the flush operation will only write this one word to memory, saving three memory access cycles. If these bits contain a X'C', only the two eight-byte words starting at offset X'10' in the cache line are dirty. Preliminary 3-0 Dirty bits 8.8: BCACH Cache Line Array This array is divided into four 32-byte buffers used as cache lines 0, 1, 2, and 3. Length Type Address Restrictions 16 Words x 64 bits Read/Write XXXX 1100 - 17F This array can only be accessed when the diagnostic mode bit in the control register is set. Bit(s) Description The four cache lines start at the following offsets into the array: Line 0 Offset X'00' Line 1 Offset X'20' Line 2 Offset X'40' Line 3 Offset X'60' ?? The Bus DRAM Cache Controller (BCACH) Page 246 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 9: Buffer Pool Management (POOLS) POOLS acts as a memory manager for the IBM3206K0424. Memory buffers are checked out and checked in via two operations (primitives) supported by POOLS: the get pointer primitive and the free pointer primitive. These primitives can be performed explicitly by accessing specified addresses within the POOLS entity, and they may also be done by hardware. CSKED can free a buffer upon transmission if specified by the corresponding packet header (see ECC Syndrome Bits on page 196), and RAALL gets buffers to store received data. In addition, POOLS contains mechanisms to control resource utilization and supports a Real Memory Mode and a Virtual Memory Mode. Basic Operation in Real Memory Mode If memory is viewed as a series of buffers, POOLS maintains a circular list of available buffers. There are pointers (the head and tail) to the start and the end of the list. When a get pointer primitive is executed, the buffer at the head of the list is checked out, the head pointer is advanced and the correct resource group(s) is debited. When a free pointer primitive is executed, the freed buffer is checked in at the end of the list, the tail pointer is advanced, and the correct resource group is credited. Basic Operation in Virtual Memory Mode With the addition of Virtual Memory, POOLS must maintain five sets of head and tail pointers, thresholds, and active counts: one for the virtual buffers themselves and the rest for the four regions of real buffers that constitute the virtual buffers. In this case the base virtual address is the item returned from a get pointer operation and returned during a free pointer operation. When the get buffer primitive is executed, POOLS creates an active buffer map (page table) for the virtual address. As the virtual address is used and buffer (page) boundaries are crossed, VIMEM will request buffers from POOLS when a buffer (page) fault occurs. VIMEM then places the buffer index in the buffer map. When the virtual buffer is no longer needed and a free pointer primitive is issued with the starting virtual address, POOLS takes the contents of the buffer map and frees the resources that were assigned to the buffer map. Resource Controls POOLS adds another layer of service by creating "pools" of buffers (currently a maximum of 16 pools). For each pool, a maximum number of allowable buffers can be specified. The intent is to make it possible for several applications to use an IBM3206K0424 at once without one or more applications starving the remaining applications for memory buffers. Particular pools buffers are divided into "guaranteed" and "common" buffers. All the guaranteed buffers are considered to be dedicated to their respective pool and are therefore not available for general use. The common buffers are all the memory buffers remaining after the guaranteed buffers are subtracted from the total buffers. To maintain the buffer limits on each pool, every pool has a guaranteed threshold, total threshold, and an active count. When a request is made for a buffer from a particular pool, the guaranteed threshold is first checked. If the active count of the pool is less than the guaranteed threshold, the buffer is provided. If the guaranteed threshold has been reached, then the total threshold is checked. If the active count is equal to the total threshold, no buffer is provided. If the active count is less than the total threshold, and a common buffer is available, a buffer is provided. If there are no common buffers available, a buffer cannot be provided and a null index is returned. To determine if a common buffer is available, a count is maintained for each size of buffer. pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 247 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Virtual Memory Overview Each virtual buffer consists of a number of real buffers. For each virtual buffer there is a buffer map that defines the size and number of real buffers that may be allocated to the virtual buffer. Each map is built from a common template (the VIMEM Virtual Buffer Segment Size Register) that associates 1 to n buffer indexes in the map to a real buffer in one of the four real buffer regions defined in VIMEM. In VIMEM, the Buffer Map Base Address Register defines the size of the map and therefore also the number of buffer indexes in the virtual buffer map. Each eight-byte entry of the map contains the pool ID of the pool to which the buffer is allocated plus space for three real buffer segment indexes. This implies the smallest map yields a virtual buffer of one to four real buffer segments (three real buffer segments plus the implicit real buffer that all virtual buffers are allocated). The biggest map defines a virtual buffer of 1-16 real buffer segments (15 plus the implicit one). The intention of this structure is to allow the user to customize the value in the Virtual Buffer Segment Size Register to utilize memory in an efficient manner relative to network data traffic. For example, if network traffic contained 50% packets of < 512 bytes, 35% packets of < 1K bytes, and the rest was < 5K bytes, the user could set up Virtual Memory to use three real segments of 512 bytes, 512 bytes, and 4K bytes respectively. The incoming data would neatly fit into the segments and minimize wasted memory. POOLS and VIMEM maintain the maps for the virtual buffers. On a write that crosses a real buffer boundary into an as yet an unresolved region of a virtual buffer, a page fault occurs. When a page fault occurs, POOLS determines whether or not a real buffer can be assigned. If it can be assigned, the index of the real buffer relative to the base address of the particular buffer size is placed by VIMEM into the buffer map. The first buffer is implicitly associated with the Virtual Memory address for a particular virtual buffer and enough real memory must be available to support the first real buffer of each virtual buffer at initialization time. There is not necessarily enough real storage for all the possible real buffers associated with a virtual buffer. Buffer Pool Management (POOLS) Page 248 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Virtual Address Buffer Map Virtual Address Buffer Map 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 16 bit 2 bit 2 bit 2 bit 2 bit 2 bit 2 bit Buffer Limit Segment Register (32 bits) Note: The Buffer Index of the first buffer and the Virtual Address Index are the same. Also note that they are right justified. Buffer Index of the first buffer in the Virtual Address (16 bits max) Number of bits for largest Packet Size (17 bits max) 32 bit Virtual Address All real buffers of a particular size are stored in a contiguous region of memory. The buffer index, in conjunction with the base address for this real buffer size, points to a particular real buffer. The implicit buffers are also stored in a data structure of this type. pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 249 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Buffer/Virtual Memory Allocation Structure in Memory Buffer Size One Base Index Zero The single box represents the storage for the whole buffer, whatever its size. Buffer Size One Index One Buffer Size One Index Two ...... Buffer Size One Index N Skip to next buffer size bound Buffer Size Two Base Index Zero Buffer Size Two Index One Buffer Size Two Index Two ...... Buffer Size Two Index N Skip to next buffer size bound Buffer Size Three Base Index Zero Buffer Size Three Index One Buffer Size Three Index Two ...... Buffer Size Three Index H Skip to next buffer size bound Buffer Size Four Base Index Zero Buffer Size Four Index One Buffer Size Four Index Two ...... Buffer Size Four Index N Skip to implicit buffer base address These indexes are determined by the virtual buffer's virtual address Implicit Buffer Index Two ...... Implicit Buffer Index N Implicit Buffer Index Zero Implicit Buffer Index One The following example illustrates these concepts. Buffer Pool Management (POOLS) Page 250 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Virtual Address Buffer Map Base Address Registers Base Address Register Buffer Size(0) BRB0 Base Address Register Buffer Size(0) BRB0 Base Address Register Buffer Size(0) BRB0 Base Address Register Buffer Size(0) BRB0 Base Address Register Buffer Size(0) BRB0 Base Address Register Buffer Map BRBM BRB4 + Shifted Buffer Index 0 + Offset into PKT Packet Storage Area Buffer,Size(4) 256 Base Index Zero Buffer, Size(4) 256 Index One Buffer, Size(4) 256 Index Two ... BRB0 + Shifted Buffer Index 0 + Offset into PKT Buffer, Size(4) 256 Index N Skip to next buffer size base address Buffer, Size(0) 256 Base Index Zero BRB0 + Shifted Buffer Index 2 Offset into PKT Buffer, Size(0) 256 Index One Buffer, Size (0) 256 Index Two ... BRB2 + Shifted Buffer Index 0 + Offset into PKT Buffer, Size(0) 256 Index N Skip to next buffer size base address Buffer, Size(1) 1024 Base Index Zero Buffer, Size(1) 1024 Index One BBR2 + Shifted Buffer Index 4 Offset into PKT Buffer, Size (1) 1024 Index Two ... Buffer, Size(1) 1024 Index N BBR3 + Shifted Buf. Index Last + Offset into PKT 16 bits Pool Id 0000 16 bits Buffer Index 1 16 bits Buffer Index 2 16 bits Buffer Index 0 16 bits Pool Id 0000 16 bits Buffer Index 4 16 bits Buffer, Size (0) 4096 Index Two Buffer Index Last ... Buffer, Size(2) 4096 Index N Skip to next buffer size base address 16 bits Buffer Index Implicit 256 Byte 2 bits Buffer Index Size(0) 256 Byte 2 bits Buffer Index Size (0) 256 Byte 2 bits Buffer Index Size (1) 1024 Byte 2 bits Buffer Index Size(2) 4096 Byte 2 bits Buffer Index Size(3) 16384 Byte 2 bits Buffer, Size(3) 16384 Base Index Zero Buffer, Size(3) 16384 Index One Unused Buffer, Size (3) 16384 Index Two ... Buffer, Size(3) 16384 Index N Segment Decode Zero Yes? Segment Decode One Yes? Segment Decode Two Yes? Segment Decode Three Yes? Segment Decode Four Yes? Segment Decode Fourteen Yes? Segment Decoder Virtual Address. Index Implicit Buffer Index Size(4) 0 No. of bits for largest Packet Size(17 max) Packet Address Region BRBM + Shifted Buffer Index 0 + Offset into Map Skip to Virtual Address base address V.M. Address Index Zero V.M. Address Index One V.M. Address Index Two ... V.M. Address Index N Skip to next buffer size base address Buffer, Size(2) 4096 Base Index Zero Buffer, Size(0) 4096 Index One pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 251 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary The lower seventeen bits of the virtual address are used in conjunction with the segment template in the VIMEM Virtual Buffer Segment Size Register to determine from which portion of the buffer map the buffer index is retrieved. Once the buffer index is retrieved, it is combined with the appropriate base address for that particular buffer size. The offset into the buffer is then added to get the real 32-bit address that is used in physical memory. POOLS uses the data structures above to manage Packet Memory resources. Each LCD is associated with a particular POOL and multiple different LCDs may be associated with that same POOL. Within a POOL, there are five different resource categories and two variables to go with each resource. Resources and Variables Example Resource Type, Pool 0000 Virtual Memory Addresses Buffer Type One Buffer Type Two Buffer Type Three Buffer Type Four Virtual Memory Addresses Guaranteed Number 100 200 50 10 0 100 Total Number 150 300 100 5 10 150 9.1: POOLS Get Pointer Primitive The POOLS Get Pointer Primitive returns a pointer to the requester. The request to the virtual packet/buffer size 4 address will always return a memory address. If in virtual mode, the address will be virtual. Requests made for buffer sizes 0 to 3 will not return an address but rather a buffer index in bits 15-0. The real address associated with this index can be generated by shifting the index by the buffer size (for example, six bit positions for a 64-byte buffer) and adding the result to the base address for this size buffer. Access to buffer sizes 0 to 3 is not permitted in operational mode. The address of the primitive also selects the pool ID. The pool ID is contained in address bits 5-2, and it selects which pool will be charged for the pointer. The buffer size is selected with address bits 8-6. If there are no more pointers available in the specified pool, a null pointer is returned. The active pointer count for that pool is incremented if a non-null pointer is returned. If the guaranteed threshold has been exceeded and a buffer from the common pool is returned, the common pools count for that size is decremented by 1. Length Type Address 32 bits Read Only Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'00000000' During normal operations this register is to be used as a read only register. Writes to this address will be ignored. pnr25.chapt04.01 August 14, 2000 XXXX 3200 XXXX 3240 XXXX 3280 XXXX 32C0 XXXX 3300 Buffer Pool Management (POOLS) Page 252 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.2: POOLS Free Pointer Primitive The POOLS Free Pointer Primitive returns the pointer to the proper free list. If it is a Virtual Memory address, the Virtual Memory Buffer Map is traversed to free the indexes associated with the Virtual Memory address. In the case where it is a real memory buffer, the single index is freed. This primitive uses address mapping to select the size of the object to be freed. The size is contained in address bits 4-2. During normal operation, only frees to buffer size four are relevant. During initialization mode, buffer sizes 0 to 3 can be used to load indexes. The indexes are loaded into bits 31-16. In normal operations it is not necessary to read this "register". Length Type Address 32 bits Write Only Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'00000000' During normal operations this register is to be used as a Write only register. Reads from this address will return '0'. XXXX 3350 XXXX 3354 XXXX 3358 XXXX 335C XXXX 3360 9.3: POOLS Common Pools Count Registers The POOLS Common Pools Count Registers indicates the number of pointers in the particular common pool. The bits are a 16-bit count. The Get Pointers that exceed the guaranteed allocation decrement this count by one assuming that the count is non-zero. When the count is zero, the Get Buffer operation will fail. The Free Pointers that operate beyond the guaranteed threshold for a particular client and free the pointer(s) increment this count by one. The microcode should initialize these registers to the value of the respective common pool that it desires to have. Length Type Address 16 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets / Buffer Size 4 Power on Value Restrictions X'0000' During normal operations these registers are to be used as a read only. Writing to these registers during operation could create a data loss situation. This register should be set up by the microcode at initialization time. XXXX 3000 XXXX 3004 XXXX 3008 XXXX 300C XXXX 3010 pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 253 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 9.4: POOLS Client Thresholds Array The POOLS Client Thresholds Array holds the guaranteed and total threshold values for the 16 pools and the four (five) pointer sizes. This array contains the guaranteed and total thresholds for the managed POOLs. When a Get Pointer primitive is processed, the values in this array are used to determine if a primitive can return a pointer. The active count from the Active Packet Count Array is used with these registers to determine if a threshold has been exceeded. If the guaranteed threshold has been exceeded and the total not exceeded and there is a common pointer available, then the common count will be incremented. If there are no common buffers available or the request will cause the total threshold to be exceeded, the request will be rejected. During a Free Pointer primitive processing, the pointer is returned to the free list and these thresholds are used to determine if a common count should be credited. Length Type Address 32 bits x 16 Words Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'00000000' None Guaranteed Threshold Total Threshold XXXX 3400 XXXX 3440 XXXX 3480 XXXX 34C0 XXXX 3500 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-0 Guaranteed Threshold Total Threshold. Description 9 8 7 6 5 4 3 2 1 0 Buffer Pool Management (POOLS) Page 254 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.5: POOLS User Threshold and Client Active Packet Count Array The POOLS User Threshold and Client Active Packet Count Array holds the user thresholds and active pointer counts for each of the 16 managed pools and four (five) pointer sizes. When a Get Pointer primitive is processed, the active count is retrieved and compared with the threshold counts. If it falls within bounds and a pointer is available, the active count will be incremented by one reflecting the additional buffer charged to that queue. When a Free Pointer primitive is processed, the active count is retrieved, and, when the pointer is returned to the free list, the active buffer count is decremented by one. The user threshold may be used to check on resource utilization as opposed to resource allocation. The Guaranteed and Total Thresholds are used when allocating resources to make decisions. The User Threshold is not used to govern resource allocation directly. One such use is for high water mark indication. When a Free Pointer primitive is processed or a Get Pointer is processed The active packet count is compared to the user threshold. If the event interface is enabled and a boundary condition is crossed an event is issued to the event interface. Length Type Address 32 bits x 16 Words Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'00000000' None User Threshold Active Packet Count XXXX 3600 XXXX 3640 XXXX 3680 XXXX 36C0 XXXX 3700 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-0 User Threshold Active Packet Count Description 9 8 7 6 5 4 3 2 1 0 pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 255 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 9.6: POOLS Pointer Queues DRAM Head Pointer Offset Address Register The POOLS Pointer Queues DRAM Head Pointer Offset Address Register indicates the address in DRAM where the head of the queue starts. This address, however, is only relative to the DRAM portion of the queue. Unless the head of the queue portion of the cache is locked out and needs two frames, the actual head of the queue is in the cache. These 19 bits on write represent the offset to the address in DRAM of the head of the queue relative to the DRAM base address. On a read, the address in DRAM of the pointer is returned. This pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. Because each memory reference contains four indices, this allows for a possible 128K index locations in the queue. Length Type Address 32 bits Read/19 bits Write Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Restrictions XXXX 3014 XXXX 3018 XXXX 301C XXXX 3020 XXXX 3024 X'00 01 C0 00' X'00 02 00 00' X'00 02 40 00' X'00 02 60 00' X'00 02 70 00' During normal operations this register is to be used as a read only register. This register defaults to zero at initialization. It is assumed that the queues start on a maximum size queue boundary. These registers should be set up at initialization time. This register is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register is written to. Buffer Pool Management (POOLS) Page 256 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.7: POOLS Pointer Queues DRAM Tail Pointer Offset Address Register The POOLS Pointer Queues DRAM Tail Pointer Offset Address Register indicates the offset address in DRAM where the tail of the queue starts. This address, however, is only relative to the DRAM portion of the queue. Unless a `no cache frames to be written through' state is in effect, the actual tail of the queue is in the cache. These 19 bits on write represent the offset to the address in DRAM of the tail of the queue relative to the DRAM base address. On a read, the address in DRAM of the pointer is returned. This pointer is adjusted every time a cache frame boundary is crossed and a cache update cycle is completed to write through the additional queue elements. Since each memory reference contains four indices this allows for 128K index locations possible in the queue. Length Type Address 16 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Restrictions XXXX 3028 XXXX 302C XXXX 3030 XXXX 3034 XXXX 3038 X'00 01 C0 00' X'00 02 00 00' X'00 02 40 00' X'00 02 60 00' X'00 02 70 00' During normal operations this register is to be used as a read only register. This register defaults to zero at initialization. It is assumed that the queues start on the maximum size queue boundary. These registers should be setup at initialization time. This register is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register is written to. pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 257 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 9.8: POOLS Pointer Queues DRAM Lower Bound Address Register The POOLS Pointer Queues DRAM Lower Bound Address Register indicates the address in DRAM where the queue data structure is initially started. When the queue reaches the maximum address allowed for in the upper bound register, it wraps back around to the address specified in this register. This implements the queue in a circular buffer. These 32 bits represent the address in DRAM where the queue begins and eventually wraps to. At initialization, this register and the POOLS Pointer Queues DRAM Tail Pointer Offset Address Register and the POOLS Pointer Queues DRAM Head Pointer Offset Address Register must be equal. Length Type Address 32 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Restrictions XXXX 303C XXXX 3040 XXXX 3044 XXXX 3048 XXXX 304C X'00 01 C0 00' X'00 02 00 00' X'00 02 40 00' X'00 02 60 00' X'00 02 70 00' During normal operations, this register is to be used as a read only register. This register should be setup at initialization time. The size of the DRAM queue storage which is formed with the lower and upper bounds is constrained in its size. It can be written when the diagnostic mode bit is set, otherwise the write is ignored. Note that if the maximum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available. Buffer Pool Management (POOLS) Page 258 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.9: POOLS Pointer Queues DRAM Upper Bound Register The POOLS Pointer Queues DRAM Upper Bound Register indicates the max queue length in DRAM of the queue data structure. When the queue reaches this address, it wraps back to the address specified by the lower bound register. This implements the queue in a circular buffer. This upper bound is to be provided as an encoded field. The encoded field represents the number of eight-byte addresses that can be contained by the queue. These four bits represent the encoded maximum queue length in DRAM which, when matched, trigger the queue to wrap back to the address contained in the DRAM Lower Bound Address Register. Length Type Address 4 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Restrictions XXXX 3050 XXXX 3054 XXXX 3058 XXXX 305C XXXX 3060 X'B' X'A' X'9' X'9' X'B' During normal operations, this register is to be used as a read only register. This register should be setup at initialization time. The size of the DRAM queue storage which is formed with the lower and upper bounds is constrained in its size. It can be written when the diagnostic mode bit is set, otherwise the write is ignored. Note that if the maximum queue length exceeds the space available in the circular buffer, data corruption will occur when the actual queue length exceeds the maximum queue space available. pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 259 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Bit(s) Encoded Value X'0' X'1' X'2' X'3' X'4' X'5' X'6' X'7' X'8' X'9' X'A' X'B' X'C' X'D' X'E' X'F' Number of 32 Bit Words 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 65536 65536 Description Number of Indexes 16 32 64 128 256 512 1024 2048 4096 8192 16384 32768 65536 131072 131072 131072 3-0 Buffer Pool Management (POOLS) Page 260 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.10: POOLS Pointer Queues Length Registers The POOLS Pointer Queues Length Registers indicates the length of the queue. The bits are a 16-bit count. A primitive that adds to the queue increments this counter. Primitives that remove items from the queue decrement this counter. Length Type Address 16 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets / Buffer Size 4 Power on Value Restrictions X'00 00' During normal operations, this register is to be used as a read only register. It can be written when the diagnostic mode bit is set, otherwise the write is ignored. This register is cleared when the POOLS Pointer Queues DRAM Lower Bound Address Register is written to. XXXX 3064 XXXX 3068 XXXX 306C XXXX 3070 XXXX 3074 9.11: POOLS Interrupt Enable Register This register is used to enable bits from the POOLS Status Register and potentially generate interrupts to the control processor. When both a bit in this register and the corresponding bit(s) in the POOLS Status Register are set, the POOLS interrupt to PCINT will be enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See POOLS Status Register on page 265 for the bit descriptions. Length Type Address Power On Value Restrictions 32 bits Clear/Set XXXX 3078 and 07C X'00 03 F8 00' None pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 261 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 9.12: POOLS Event Enables This register is used to enable an event based on bits from the corresponding primitive transaction. If the bits are set in the enable and a transaction occurs that matches the event, an event will be sent to the RXQUE. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address 16 bits Clear/Set GTD Event Enables XXXX 3A00 and A04 Total Event Enables XXXX 3A08 and A0C User Event Enables XXXX 3A10 and A14 Power on Value Restrictions X'0000' None 9.13: POOLS Event Hysteresis Register The POOLS Event Hysteresis Register provide the capability for hysteresis on threshold checking. Length Type Address Power on Reset value Restrictions Hysteresis Value 8 bits Read/Write XXXX 3A18 X'0000' None 7 6 Bit(s) 5 4 3 2 1 0 Description When a free occurs, the value in this register is added to the next Active Packet Count. This value will be then tested against the threshold value. If it is equal to the threshold, an event will be issued if events are enabled and the event associated with this transaction is enabled. Function 7-0 Hysteresis Value Buffer Pool Management (POOLS) Page 262 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.14: POOLS Event Data Register The POOLS Event Data Register provides the data that was sent on the last event. Length Type Address Power on Reset value Restrictions Free Processed GTD Threshold Match with Hysteresis Free Processed Total Threshold Match with Hysteresis Free Processed User Threshold Match with Hysteresis 32 bits Read XXXX 3A1C X'0000003E' None Get Processed Total Threshold Match Get Processed User Threshold Match Get Processed GTD Threshold Match Buffer size of the Event POOL ID of the Event 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Function Free Processed GTD Threshold Match with Hysteresis 9 8 7 6 5 4 3 Event Source ID 2 1 Reserved Reserved Reserved 0 Description This event occurs when a free is processed and the threshold is matched. The threshold is modified by the value in the hysteresis register. The event is issued when the actual value of the Active Packet count plus the hysteresis equals the threshold. This event occurs when a free is processed and the threshold is matched. The threshold is modified by the value in the hysteresis register. The event is issued when the actual value of the Active Packet count plus the hysteresis equals the threshold. This event occurs when a free is processed and the threshold is matched. The threshold is modified by the value in the hysteresis register. The event is issued when the actual value of the Active Packet count plus the hysteresis equals the threshold. This event occurs when a get is processed and the threshold is matched. The event is issued when the new Active Packet count equals the threshold. This event occurs when a get is processed and the threshold is matched. The event is issued when the new Active Packet count equals the threshold. This event occurs when a get is processed and the threshold is matched. The event is issued when the new Active Packet count equals the threshold. Reserved 31 30 Free Processed Total Threshold Match with Hysteresis 29 Free Processed User Threshold Match with Hysteresis Get Processed GTD Threshold Match Get Processed Total Threshold Match Get Processed User Threshold Match Reserved 28 27 26 25-20 pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 263 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 19-16 15-11 10-8 7-6 5-0 Function POOL ID of the Event Reserved Buffer size of the Event Reserved Event Source ID Description This indicates which pool is associated with this event. Reserved This indicates which size is associated with this event. Reserved This indicates that POOLS is associated with this event. Preliminary Buffer Pool Management (POOLS) Page 264 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.15: POOLS Status Register The POOLS Status Register provides status information about pools operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 3080 and 084 X'00 00 00 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. Control Memory Access Timer Expired Packet Memory Access Timer Expired Common Buffers Size 4 Exhausted Common Buffers Size 3 Exhausted Common Buffers Size 2 Exhausted Common Buffers Size 1 Exhausted Common Buffers Size 0 Exhausted Buffer Size 4 Threshold Crossed Buffer Size 3 Threshold Crossed Buffer Size 2 Threshold Crossed Buffer Size 1 Threshold Crossed Buffer Size 0 Threshold Crossed 1 Active Count Error Detected Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-21 20 19 Reserved POOLs Event Issued Packet Memory Access Timer Expired Control Memory Access Timer Expired Function Reserved 9 8 7 6 5 4 3 2 Description This bit is set when a POOLs event is issued. This bit is set when the Packet Memory access timer hits the Packet Memory access threshold and the control bit in the control register is set to enable this function. This bit is set when the Control Memory access timer hits the Control Memory access threshold and the control bit in the control register is set to enable this function. This bit is set when a lock enable bit is set and the corresponding status bit is set. This causes all state machines to be held in idle once this bit is set. It is the functional equivalent to POOLS Control Register bit 0. This bit is set when too many indexes are freed to a queue. This bit is set when a previously freed buffer is detected during a free operation. This typically would occur when the buffer was freed two or more times. This bit is set when a bad map is detected during a free operation. This bit is set when an active packet count is decremented from '0' to X'FFFF'. This is most likely the result of a subtle map corruption where a POOL ID has been changed. This bit is set when an Index Threshold is crossed. 18 17 16 15 14 13 12 POOLs Locked Initialization Error Detected Unused Buffer Freed Error Bad Map Detected Active Count Error Detected Bad Index Detected pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 265 of 676 Get Pointer Primitive Failed 0 Initialization Error Detected Unused Buffer Freed Error POOLs Event Issued Bad Index Detected Bad Map Detected POOLs Locked Pointer IBM3206K0424 IBM Processor for Network Resources Bit(s) Function Free Pointer Primitive Null Detected/Max Pointer Queue Length Exceeded. Common Buffers Size 4 Exhausted Common Buffers Size 3 Exhausted Common Buffers Size 2 Exhausted Common Buffers Size 1 Exhausted Common Buffers Size 0 Exhausted Buffer Size 4 Threshold Crossed Buffer Size 3 Threshold Crossed Buffer Size 2 Threshold Crossed Buffer Size 1 Threshold Crossed Buffer Size 0 Threshold Crossed Get Pointer Primitive Failed Description This bit is set as a result of one of two detectable errors: Null index detected within free address. Total allowed storage for a particular queue has been exceeded. Common buffer count for size 4 is zero. Common buffer count for size 3 is zero. Common buffer count for size 2 is zero. Common buffer count for size 1 is zero. Common buffer count for size 0 is zero. The number of size 4 buffers is equal to or less than the threshold that was set for size 4 buffers. The number of size 3 buffers is equal to or less than the threshold that was set for size 3 buffers. The number of size 2 buffers is equal to or less than the threshold that was set for size 2 buffers. The number of size 1 buffers is equal to or less than the threshold that was set for size 1 buffers. The number of size 0 buffers is equal to or less than the threshold that was set for size 0 buffers. This bit is set when a null address is returned on a get. Preliminary 11 10 9 8 7 6 5 4 3 2 1 0 Buffer Pool Management (POOLS) Page 266 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.16: POOLS Control Register The POOLS Control Register provide status information about POOLs operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 30C8 and 0CC X'00 00 20 01' Caution must be used when asserting some of the bits during operation. Packet High Priority on Get or Free FIFOs Full Force All Queue Transactions to Memory 1 Control High Priority with Request Timer Packet High Priority with Request Timer Enable Out of Range Index Checking Primitive Trap Source Selector Use Compressed Virtual Maps Control High Priority Always Packet High Priority Always Limit Event Generation Enable Event Interface Lock POOLs on Error Virtual Memory Mode Initialization Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-19 18 Reserved Use Compressed Virtual Maps Function Reserved 9 8 7 6 5 4 3 2 Description This bit selects compressed virtual maps when set. These bits will select the source of the last primitive trapped register. 0000 Free from the PCI bus 0001 Free from RAALL 0010 Free from RXQUE 0011 Free from CSKED 0100 Free from SEGBF 0101 Free from DMAQS 0110 Get from PCI Bus 0111 Get from REASM 1(RA) 1000 Get from DMAQS 1001 Get from VIMEM (POOL ID (4 bits)), Size (2 bits), blank (10 bits), index (16 bits)) '1010' Get from REASM 0(RC) '1010' Last Get Processed (Buffer Addr:(31-4)), Source (3-0) see above) '1011' Last Free Accepted (Buffer Addr:(31-4)), Source (3-0) see above) '1100' Last Primitive Processed (Buffer Addr:(31-4)), Source (3-0) see above) '1101' Last Free Processed 17-14 Primitive Trap Source Selector pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 267 of 676 Diagnostic Mode 0 Fast Free Mode Reserved IBM3206K0424 IBM Processor for Network Resources Bit(s) 13 12 11 10 9 8 Function Lock POOLs on Error Packet High Priority on Get or Free FIFOs Full Packet High Priority Always Control High Priority Always Description When set, this bit in conjunction with the lock mask will hold pools state machines in an idle state until cleared. When set, this bit causes pools to turn on its high priority request to Packet Memory when either the free or get FIFO is full. When set, this bit causes pools to always use its high priority request to Packet Memory. When set, this bit causes pools to always use its high priority request to Control Memory. Preliminary Packet High Priority with Request When set, this bit causes pools to time the wait for Packet Memory service and when Timer the timer expires move to high priority. Control High Priority with Request When set, this bit causes pools to time the wait for Control Memory service and when Timer the timer expires move to high priority. When this bit is set, Fast Free Mode is enabled. When pools is in Fast Free Mode it does not write out the buffer map with the modified control information that indicates that the map is unused. When in this mode unused buffer free error checking is disabled. When the value of the bit is '0', initialization mode is set. When the value is '1', operational mode is set. During initialization mode indexes are in the upper 16 bits of the data word. It is assumed that when initialization mode is on other normal operations are not active such as transmit or receive. During operational mode packet addresses assumed to be on the data bus. When set to '0', Virtual Memory mode is enabled. When set to '1', real memory mode is enabled. When set, this bit causes pools to limit the issuance of events to RXQUE when a GTD threshold, Total Threshold or POOL Threshold is reached. It will issue the first event and disable the related event enable bit. Software must then reset the bit if it wishes to see another such event. However, it is possible that events may be lost when this bit is set on. When set, this bit causes pools to issue resource events to RXQUE when a GTD threshold, Total Threshold or POOL Threshold is reached. When set, this bit causes pools to check the indexes that are streaming by to be checked against a maximum value for that size index. If the normal initialization sequence is used, these maximum values will auto set. When set, this bit disables the internal tail to head transfer path within the queue. All indexes will proceed into memory before being brought to the head of the queue. This effectively preserves the operational history in memory. However, some caution is warranted since four full entries are required for a write to memory. This could cause indexes to get "stuck" at the back of the queue. When this residue occurs, a zero pointer is returned even though the operation might have otherwise returned a valid pointer. When set, pools is in diagnostic mode. When cleared, pools is in normal mode. When in diagnostic mode, state machines are held in idle. If they are already active, when they next go to idle they will hold there. 7 Fast Free Mode 6 Initialization Mode 5 Virtual Memory Mode 4 Limit Event Generation 3 Enable Event Interface Enable Out of Range Index Checking 2 1 Force All Queue Transactions to Memory 0 Diagnostic Mode Buffer Pool Management (POOLS) Page 268 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.17: POOLS Buffer Threshold Registers 0-4 The POOLS Buffer Threshold Registers 0-4 is the threshold set by the software to set the threshold crossed bit in the POOLS Status Register. This register is used to compare with the queue length register. This register consists of a 16-bit count match. The threshold count is compared to the queue length count. If the queue length is less than the value in this register, the appropriate bit is set in the status register respective to this queue. Length Type Address 16 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'0000' None XXXX 3088 XXXX 308C XXXX 3090 XXXX 3094 XXXX 3098 9.18: POOLS Index Threshold Registers 0-4 The POOLS Index Threshold Registers 0-4 provide error checking. These are the thresholds set by the software or hardware to set the index threshold crossed bit in the POOLS Status Register. This register is used to check indexes during free operations to look for an out of bounds index. Each register consists of a 16-bit compare value. The threshold count is compared to the index while being processed. If an index is greater than the value in this register, the appropriate bit is set in the status register. Length Type Address 16 bits Read/Write Buffer Size 0 Buffer Size 1 Buffer Size 2 Buffer Size 3 Virtual Packets/ Buffer Size 4 Power on Value Restrictions X'0000' None XXXX 30F0 XXXX 30F4 XXXX 30F8 XXXX 30FC XXXX 3100 pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 269 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 9.19: POOLS Last Primitive Trap Register The POOLS Last Primitive Trap Register provide debug assistance. It contains the 32-bit last primitive address, and it is the last primitive address to POOLS, as selected in the POOLS Control Register, while in operational mode. Length Type Address 32 bits Read XXXX 30E8 Power on Reset values X'00 00 00 00' Restrictions None 9.20: POOLS Last Buffer Map Read on Free Register The POOLS Last Buffer Map Read on Free Register provide debug assistance. It contains the 32-bit address of the buffer map used in the last free operation, and it is the address of the last buffer map read on a free. Length Type Address 32 bits Read XXXX 30EC Power on Reset values X'00 00 00 00' Restrictions None 9.21: POOLS Error Lock Enable Register The POOLS Error Lock Enable Register provides the ability to halt pools when the corresponding status bit in the status register are set. When a bit in this register that corresponds to a bit that is set in the status register, the state machines in pools will be held in idle state until the lock is disabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 21 bits Clear/Set XXXX 30D8 and DC X'00 F8 00' None Buffer Pool Management (POOLS) Page 270 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 9.22: POOLS Packet and Control Memory Access Threshold The POOLS Packet and Control Memory Access Threshold timers are used to help limit the amount of time that pools can be held off from its respective memory. The bits are a 12-bit count. When the proper bit in the POOLS Control Register is set and a request is made to the requisite memory, a counter is loaded with this value. The counter will then count down to zero in 30 ns ticks. When it hits zero, it forces the request to high priority. Length Type Address 12 bits Read/Write Packet Memory Timer Threshold Control Memory Timer Threshold Power on Reset value Restrictions X'080' None XXXX 30E4 XXXX 30E0 9.23: POOLS Buffer Map Group The POOLS Buffer Map Group holds the buffer map of the packet that is in the process of being freed. From this map, the pool ID and the indexes that have been used are returned to their correct queue. This register consists of a 16-bit flag field and 16-bit indexes. The flag field contains the pool id and the valid bit. When a packet is freed, the valid bit is set to '0'. When a get operation occurs, the valid bit is then set. This helps to find address duplicates and other address related problems that software can generate. Length Type Address 32 bits Read/Write Upper 16 Bits: Flag Field 0 Index 1 Flag Field 1 Index 4 Flag Field 2 Index 7 Flag Field 3 Index 10 Flag Field 4 Index 13 Power on Reset value Restrictions X'FFFFFFFF' None Lower 16 Bits: Index 0 Index2 Index 3 Index 5 Index 6 Index 8 Index 9 Index 11 Index 12 Index 14 XXXX 309C XXXX 30A0 XXXX 30A4 XXXX 30A8 XXXX 30AC XXXX 30B0 XXXX 30B4 XXXX 30B8 XXXX 30BC XXXX 30C0 pnr25.chapt04.01 August 14, 2000 Buffer Pool Management (POOLS) Page 271 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Buffer Pool Management (POOLS) Page 272 of 676 pnr25.chapt04.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Transmit Data Path Entities Entity 10: Transmit Buffer (CSKED) The transmit cell scheduler entity is responsible for receiving a packet from the processor, determining when cells from the packets need to be transmitted, and passing this information to the segmentation buffer entity. The logic consists of timers and counters for determining transmit opportunities and interfaces to ARBIT (for accessing the timing data and descriptors), PCINT (for register accesses), RXQUE (for queuing events), POOLS (for returning buffers when finished transmitting), and SEGBF (for getting the data from memory to transmit). Scheduling Overview This entity provides traffic shaping to ensure that traffic sent by the IBM3206K0424 conforms to the Quality of Service (QoS) parameters as defined by the ATM Forum. CSKED provides support for the following QoS parameters: * Peak Cell Rate (PCR) - The maximum number of cells per second that the connection can transfer into the network. * Sustained Cell Rate (SCR) - The average number of cells per second that the connection can transfer into the network. The burst tolerance determines the length of time over which the network measures this average. * Burst Tolerance - The maximum length of time that the user can transfer at the peak cell rate. Burst Tolerance can be measured in number of cells, a measurement known as maximum burst size (MBS). CSKED will send out cells at the SCR. If transmit opportunities are missed, as is the case when there is no data to send, the actual rate will become less than SCR. When data becomes available to send, CSKED will transmit up to MBS cells at the PCR, until the transmit rate returns to SCR. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 273 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Operational Description LCD Initialization A Logical Channel Data Structure (LCD) containing scheduling parameters for the circuit must be initialized before segmentation can be started. The parameters that are important to the operation of this entity are: average_interval This field contains the minimum average spacing allowed between cells transmitted on this connection. It is the reciprocal of the Sustainable Cell Rate (SCR), as specified in the ATM Forum Traffic Management Specification. The value for this field is expressed in slot times. The length of time for a slot is defined by the Timeslot Prescaler Register and should normally be set to one cell time. This field contains the minimum spacing allowed between consecutive cells on this connection. It is the reciprocal of the Peak Cell Rate as specified in the ATM Forum Traffic Management Specification. This spacing is also expressed in slot times. A connection that can transmit every slot time would have a value of `1' for this field. The values in these fields are used to limit the number of cells that can be transferred at the peak rate. The max_burst_value will be multiplied by four to the power of the max_burst_mult to yield the maximum credit time. This time is expressed in slot times and represents the time it would take to acquire the maximum number of cell credits. This maximum credit time should equal the average interval minus the peak interval, multiplied by the maximum number of cells (MBS) that can be transferred at the peak rate. This field specifies the priority of transmission on this connection. Three levels of priority are available. Connections needing the highest quality of service, such as a CBR connection, should use the highest priority. Connections with the lowest quality of service requirements, such as a UBR connection, should use the lowest priority. Data can be sent on up to four physical drops. This field specifies the drop for this connection. If this bit is set, the lower eight bits of the average interval and peak interval parameters contain a fractional component. This allows a finer resolution for scheduling. For example, for a peak interval of 1.5 time units, the value written to the peak_interval field should be hex 0180. If this bit is set, the initial value of timestamp should contain the current timeslot counter shifted 16 bits to the left. peak_interval max_burst_value and max_burst_mult transmit_priority drop max_resolution See Transmit Logical Channel Descriptor Data Structures on page 66 for further information. A Scheduling Example If a connection is to have an SCR of 50 Mbps and a PCR at the line rate of 150 Mbps and a MBS of 10 cells, the LCD needs to be initialized as follows: * average_interval = 150 Mbps/50 Mbps = 3 * peak_interval = 150 Mbps/150 Mbps = 1 * max_burst_value = 10*(3-1) = 20 The following example uses a timeline to show how a connection with these parameters is scheduled. Cells are sent every third slot while there is data to send. After the first two cells are sent there is no more data to Transmit Buffer (CSKED) Page 274 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources send until another packet is enqueued. For each missed transmit opportunity, a cell can be sent at the peak interval, which is one. In the 15 timeslots after the first cell, five cells are sent for an SCR of 50 Mbps. The burst size is three, which is less than MBS. The unfilled slots can be used by other connections. Timeline Example of Scheduling E S SS S S S |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|-> time T T T T T T |---| represents 1 time slot (the time it takes to send one cell). S represents a cell being sent. T represents a transmit opportunity at SCR. E represents a packet enqueue. CSKED Initialization Before packets are enqueued for transmission, in addition to initializing the above scheduling parameters in the LCD, the following registers need to be set up. * Timeslot Prescaler Register - The amount of time for one timeslot is defined by this register. It defaults to 707 ns which is one cell time on a 622 Mbps Sonet interface. * CSKED Control Register - Additional scheduling options such as number of physical drops needs to be set in this register. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 275 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Packet Initialization Packets to be segmented are written to Packet Memory, which has been allocated by POOLS. The address of the LCD describing the channel that this packet is to be transmitted on must be written to the header of the packet. Packet segmentation is started by issuing the transmit enqueue primitive to this entity. This entity will schedule segmentation of the packet according to the parameters set up in the LCD. Scheduling Options ABR Scheduling CSKED has logic to assist in the processing of ABR connections. If the connection is ABR, the LCD will have a different configuration, as specified in Transmit Logical Channel Descriptor Data Structures on page 66. The following fields need to be initialized before the packets are sent on the connection. * Scheduling type - This field must be set to the value specifying an ABR connection. * Nrm - This field should specify the maximum number of cells a source may send for each forward RM-cell. Number of cells = (2Nrm)+1. * Trm - This field provides an upper bound on the time between forward RM-cells for an active source. Time = 100(2-Trm) msec. * ADTF - The ACR Decrease Time Factor is the time permitted between sending RM-cells before the rate is decreased to ICR. Time = ADTF 0.01 msec. * All other ABR fields should be initialized to '0'. Frame Scheduling CSKED has logic to support frame-based scheduling. It is enabled whenever the PHY type is configured for POS-PHY in LINKC. In frame-based scheduling the packet is sent out at the line rate, but the start time of the next frame is determined by multiplying the peak interval by the number of 64-byte blocks in the packet. The average portion of the bandwidth used by a connection will be 1/(peak interval). For example, if a connection is to use 1/4 of the bandwidth, the peak interval should be set to four. The frames will be sent out at line rate, but the spacing between the start of each frame will be four timeslots for each cell sent from the packet, so on average 1/4 of the bandwidth will be used by the connection. The following timeline example depicts sending two packets, the first contains four cells and the second contains three cells. The unfilled slots can be used by other connections. Transmit Buffer (CSKED) Page 276 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Timeline Example of Frame Scheduling 4 cells 3 cells x 4 slots/cell x 4 slots/cell = 16 timeslots = 12 timeslots |<----------------------------->|<--------------------->| SSSS SSS S ... |-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|-|->time |-| represents 1 time slot (the time it take to send 1 cell). S represents a cell being sent. The above example assumes that one slot time is initialized to the time it takes to send 64 bytes out on the line. The term "cells" was used in this example to mean a 64-byte block of packet data. In frame mode, the ATM header is not prepended to the data being sent. Weighted fair queueing on a frame basis is supported on the low priority queue by setting bit 17 in the CSKED Control Register. When using frame-based scheduling and weighted fair queuing together, the average interval will be used to limit the spacing between packets, not cells. Path Scheduling CSKED has logic to support sharing scheduling parameters between multiple connections. In path scheduling, an LPD is set up to contain the scheduling parameters for the group of connections in the same way it is done for LCDs. All connections that wish to share this bandwidth set the alter_sched field in their LCD to indicate this VC is on a VP, and initialize the lpd_pointer field to point to the LPD. The segmentation portion of the LPD is not used since the segmentation parameters are taken from the LCD. The scheduling parameters in the LCDs are not used as they are in the LPD. The bandwidth is shared on a packet or cell basis depending the value of the alter_sched field in the LCD. Since both the LPD and LCD need to be fetched for each transmit opportunity, this scheduling method should not be used where the performance boundaries are being pushed, as in 622 Mbps. See Transmit Logical Channel Descriptor Data Structures on page 66 for further information on LPD descriptors. Primitives Enqueue After a packet has been written to memory and the packet header updated with the offset and length of the data and the LCD address of the connection, an enqueue primitive needs to be issued to the Transmit Enqueue Primitive address. Close Connection When no more traffic is to be sent on a connection, this primitive can be executed to cause an event to be generated when segmentation has stopped on this connection. Segmentation will be stopped immediately, or stopped after all packets on this connection have been transmitted as specified in the CSKED Control Register. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 277 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Start/Stop Timer When this primitive is executed, a timer is started or stopped whose parameters are contained in the specified LCD. When the timer pops, a DMA descriptor specified in the LCD will be executed. 10.1: Transmit Enqueue Primitive Enqueues a buffer for transmission. Length: Type Address Power On Value Restrictions 32 bits Write Only XXXX 1200 X'0000 0000' None Transmitted Buffer Address Ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5-0 Description 9 8 7 6 5 4 3 2 1 0 This must contain the address of the buffer to be transmitted. Buffers must be aligned on at least 64 byte boundaries. The lower six bits are ignored. Ignored 10.2: Resume Transmission Primitive Resumes transmission on an ABR connection that has been suspended. On an ABR connection, ADTF, CRM, and CCR=0 events will cause the transmission to be suspended until a rate conversion is completed, normally by the internal processor. This primitive will resume transmission on those connections, once the rate conversion is completed. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1204 X'0000 0000' This address should be written with care. This primitive should only be used on connections that have been suspended. Resume LCD Address Ignored 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-0 Description 9 8 7 6 5 4 3 2 1 0 This must contain the address of the LCD that is to resume transmission. The lower seven bits are ignored. Ignored Transmit Buffer (CSKED) Page 278 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.3: Start/Stop Timer Primitive Start or stop a timer with the parameters in the specified LCD address. When this primitive is executed, a timer is started or stopped whose parameters are contained in the specified LCD. Bit 0 specifies whether to start (0) or stop (1) the timer. When the timer pops, a DMA descriptor specified in the LCD will be executed. Length: Type: Address: Power On Value: Restrictions: 32 bits Read/Write XXXX 1208 X'0000 0000' None Start - Stop 2 1 0 2 1 0 Start/Stop Timer Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-1 0 Description This must contain the address of the LCD that contains the timer parameters. Reserved. This bit specifies whether the timer is to be started (0) or stopped (1). 9 8 7 6 5 4 3 10.4: Close Connection Primitive Transmission is complete on a connection specified by an LCD address. When no more traffic is to be sent on a connection, this primitive can be executed to cause an event to be generated when segmentation has stopped on this connection. Segmentation will be stopped immediately, or stopped after all packets on this connection have been transmitted, as specified in the CSKED Control Register. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 120C X'0000 0000' None Close LCD Address Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-0 Description 9 8 7 6 5 4 3 This must contain the address of the LCD that is to be closed. The lower seven bits are ignored. Reserved. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 279 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.5: Timeslot Prescaler Register This register determines the length of time for one timeslot. This controls the rate that the cell scheduling counters are incremented. Each clock cycle, the value in this register is added to a 24-bit counter. When the upper bit of the counter changes state, the Current Timeslot Counter is incremented. This should normally be set to the time it takes to transmit one cell. It will be initialized to the cell time for a 622 Mb/s SONET connection (599.04 Mb/s payload). The following formula should be used to determine the value to load in this register: Timeslot Prescaler = (clock interval/timeslot interval) x 223. Length Type Address Power On Value Restrictions 24 bits Read/Write XXXX 1210 X'02B67C' This register should be written only at initialization time. Timeslot Counter Rate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 23-0 9 8 7 6 5 4 3 2 1 0 Description This value will determine the rate at which the Current Timeslot Counter is advanced. 10.6: Current Timeslot Counter This counter contains a count of how many prescaled intervals have elapsed. It is used to determine if scheduling needs to be done or credits exist. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1218 X'0000 0000' This register is meant to be read only. It is writable for diagnostic purposes only. Elapsed Interval Count 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 This value represents how many expirations have occurred since the counter rolled over. Transmit Buffer (CSKED) Page 280 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.7: CSKED Control Register This register is used to control the actions of CSKED. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1220 and 224 X'0759' None Queue LCD-Based Memory Management Events Use Weighted Fair Queueing for Low Priority Disable Overlapping Transmit Requests Disable Virtual Buffer Error Detection Disable queuing virtual buffer errors Disable Preflushing TxLCD Cache LCD-Based Memory Management SEGBF Queue Length Threshold Disable SEGBF Queue Length Close Connection Immediately Enable Medium Priority Traffic Flush Transmit LCD Cache Enable High Priority Traffic Enable Low Priority Traffic 1 Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-28 27 26-22 21 Reserved Disable preflushing txLCD cache Reserved Disable overlapping transmit requests Close connection immediately Name Reserved 9 8 7 6 5 4 3 2 Description This bit disables automatically, flushing a cache line when all lines are dirty Reserved This bit is meant for debug purposes only. It will disable the ability of CSKED to overlap requests to SEGBF. Setting this bit will cause segmentation to stop immediately on any connection that has been issued a close connection primitive. If this bit is not set, an event will be generated after all traffic queued to this connection has been sent. Setting this bit will cause LCD-based memory management events to be queued to the Transmit Complete Queue, if enabled by bit 18 of this control register. If LCD-based memory management is enabled and this bit is off, the receive pool ID associated with this connection will be updated when a threshold is crossed. 20 19 Queue LCD-based memory management events 18 Setting this bit will enable LCD-based memory management for received packets. See LCD-based memory management Definition of LCD-Based Memory Management of Transmit LCD on page 73 for further information on this function. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 281 of 676 Enable Cell Scheduling 0 Buffer Request Priority Queue LCD Address Reschedule Packets Enable Timers Reserved Reserved IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description Preliminary 17 Setting this bit will cause low priority traffic to be scheduled using weighted fair queueing. The peak interval in the LCD is used to provide a relative weight in determining the amount of bandwidth the connection will use. For example, a peak interval of one will Use weighted fair queueing for low use twice the bandwidth as a connection with a peak interval of two. The average interpriority val specifies the maximum rate that the connection can use. For example if the average interval is set to two, the maximum rate at which it can send a cell is every two timeslot times (as defined in the Timeslot Prescaler Register). Reserved Reserved Reserved. Reserved. 16 15 14 13 12 Queue the LCD address if freeing Setting this bit will cause the LCD address, instead of the packet address, to be and queueing queued if both freeing and queueing on transmit are complete. Disable virtual buffer error detection Disable queuing virtual buffer errors Flush Transmit LCD Cache Setting this bit will cause the buffer enqueue logic to ignore virtual buffer errors. If virtual buffer error detection is not disabled, detected errors will be queued. If this bit is set, this queueing is disabled and the buffer will be freed. If this bit is set, the transmit LCD cache will be flushed. This bit will be reset after the cache has been flushed. Flushing the cache should not be needed in normal operation. Cells can be queued in SEGBF up to the number specified in this register. The default is seven, which is above the limit for pass two. Writing these bits to '0' will also disable this function. CSKED will normally include SEGBFs queue length in the calculations when rescheduling a cell. If this bit is on it will disable this function and the cell will be scheduled as if the cells were transferred when SEGBF accepted the cells. If this bit is not set, scheduling requests have a higher priority than buffer requests. If this bit is set this priority is reversed. It should be set if a significant percentage of packets are only a few cells in length. Timer descriptors can be enqueued to this entity that will cause a DMA descriptor to be executed on expiration. If these timers are used, this bit must be set. If they are not used, this bit should be reset. This function is not implemented in pass one. It is implemented in pass two. If the average or peak interval is greater than 255, the cells will be scheduled in the slow queue. The slow queues will be serviced every 64 pre-scaler time units. This means that a jitter of up to 64 pre-scaler time units should be expected for slow traffic. If this bit is set, packets in the slow queue will be rescheduled at the appropriate time to the fast queue. This will decrease the variation in the scheduling but may cause some performance degradation if traffic is heavy. For each priority enabled 16KB of Control Memory must be reserved for timing data. If only one or two priorities are to be used, bits corresponding to unused priorities should be cleared to improve performance. Enable Medium Priority Traffic. Enable Low Priority Traffic. If this bit is off, no primitives will be handled or cells scheduled. 11 10-8 SEGBF Queue Length Threshold 7 Disable SEGBF Queue Length in Scheduling 6 Priority of buffer requests 5 Enable timers 4 Reschedule Packets in the Slow Queue to the Fast Queue 3 2 1 0 Enable High Priority Traffic Enable Medium Priority Traffic Enable Low Priority Traffic Enable Cell Scheduling Transmit Buffer (CSKED) Page 282 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.8: Transmit Segmentation Throttle Register This register contains the number of cycles to wait between successive requests to transmit a cell. Its purpose is to slow segmentation on all VCIs if it is determined by software that the network can not handle the generated load. The value in this register will be loaded into the Transmit Segmentation Counter each time a cell is accepted for transmission. For normal operation the value in this register should be '0'. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 1230 X'0000' None Queue Length 15 14 13 12 11 10 Bit(s) 15-0 9 8 7 6 5 4 3 2 1 0 Description When the transmit complete queue length reaches this value an interrupt will be generated. pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 283 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.9: Transmit Segmentation Throttle Counter This register is loaded with the value in the Transmit Segmentation Throttle Register after each cell is accepted for transmission and counts down until it reaches '0'. A new cell transmission will not be requested until this counter reaches '0'. Length Type Address Power On Value Restrictions 16 bits Read Only XXXX 1234 X'0000' Read Only Transmit Segmentation Throttle Counter 15 14 13 12 11 10 Bit(s) 15-0 9 8 7 6 5 4 3 2 1 0 Description When this counter reaches '0', a new cell can be transmitted. 10.10: MPEG Conversion Register This register is used to convert MPEG time units into timeslot time units. If MPEG traffic is configured in the LCD, the data stream will be monitored for PCRs. If a PCR is detected, it will be scheduled at the time specified in the PCR. A conversion factor needs to be written into this register to convert the MPEG time units into timeslot units. It will be initialized to a value that converts the MPEG time units (90 KHz) into the timeslot units (353.2 KHz, assuming one timeslot is the time it takes to send one cell over a SONET connection). The lower 12 bits of this register contain the fractional portion of this conversion factor. Example: 353.2076 KHz / 90 KHz = 3.924528 = 3.ECB hex Length Type Address Power On Value Restrictions 15 bits Read/Write XXXX 125C X'3ECB' None MPEG Time Conversion Factor 14 13 12 11 10 Bit(s) 14-0 9 8 7 6 5 4 3 2 1 0 Description Contains the conversion factor. Transmit Buffer (CSKED) Page 284 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.11: ABR Timer Prescaler Register This register determines the length of time for a tick of the RM Cell Timer. This controls the rate that the cell scheduling counters are incremented. Each clock cycle, the value in this register is added to a 24-bit counter. When the upper bit of the counter changes state, the RM Cell Timer is incremented. This should be set to value of 0.78 ms. It will be initialized to 0.78 ms assuming a 30-ns clock (as set up in SCLOCK). The following formula should be used to determine the value to load in this register: ABR Timer Prescaler = (clock interval/0.78 ms) x 223. Length Type Address Power On Value Restrictions 24 bits Read/Write XXXX 127C X'0000A2' This register should be written only at initialization time. ABR Counter Rate 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 23-0 9 8 7 6 5 4 3 2 1 0 Description This value will determine the rate at which the ABR counter is advanced. 10.12: RM Cell Timer This register is used to keep track of the last time that an ABR RM cell was sent. Its period should be 0.78 ms. Length Type Address Power On Value Restrictions 24 bits Read/Write XXXX 126C X'000000' None RM Timer Value 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 23-0 Timer value. 9 8 7 6 5 4 3 2 1 0 Description pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 285 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.13: CSKED LCD Update Data Registers Used to specify data to write into the LCD on the update LC operation. These registers contain the data used in the LC Update Operation. For more information on its use, see the CSKED LCD Update Operation Registers on page 287. This register changes to contain the updated data written to the LC word while the operation is completing. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update1 Update2 X'000000' None XXXX 1300 XXXX 130C 10.14: CSKED LCD Update Mask Registers Used to specify data to write into the LCD on the update LC operation. These registers contain the mask used in the LC Update Operation. For more information on its use, see the CSKED LCD Update Operation Registers on page 287. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update1 Update2 X'000000' None XXXX 1304 XXXX 1310 Transmit Buffer (CSKED) Page 286 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.15: CSKED LCD Update Operation Registers Used to specify the LCD word to update. This operation is used to update a portion of an LCD. If this operation is not used, software or IBM3206K0424 updates of the LCD may be lost because the LCD is cached in IBM3206K0424 while cells are being processed. This register is written with the address of the LCD word to update. Once this register is written the update operation starts. All subsequent reads or writes to the data, mask, or update registers are held off until the operation completes. A read-modify-write will occur to update the portion specified by the mask with the masked value in the data register. Normally this register would not be read. However, if it is read then the low order bit is read as '0' and the next lowest order bit (bit 1) is read as the busy bit. This signifies whether an operation is still going on. If an operation is still going on, then a new write to any of the data, mask, or update operation registers is held off until the original operation is complete. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update1 Update2 X'000000' The low order two bits are not writable XXXX 1308 XXXX 1314 pnr25.chapt05.01 August 14, 2000 Transmit Buffer (CSKED) Page 287 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.16: Drop Access Control Register Each drop(4) has registers that can be used for debugging purposes and bandwidth limiting. To conserve address space, this register determines the drop for the register access. These registers are Fast Serviced Counters, Slow Serviced Counters, and Priority Bandwidth Limit Registers. This register must be rewritten whenever values for a different drop need to be read or written. Length Type Address Power On Value Restrictions Drop 2 bits Read/Write XXXX 1288 X'00000000' None 1 0 Bit(s) 1-0 Description This value represents the drop number or the above registers that will be accessed. Transmit Buffer (CSKED) Page 288 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Performance Registers This section contains registers that are for performance purposes. 10.17: High Priority Bandwidth Limit Register This register can be used to limit the bandwidth used by high priority connections. The upper eight bits of this register specifies the number of high priority cells that can be sent in a window specified by the lower eight bits of this register. If no data needs to be sent by lower priority connections, high priority connections will not be limited. Length Type Address Power On Value Restrictions Cells Transmitted 16 bits Read/Write XXXX 1270 X'00000000' None Cell Times in Window 15 14 13 12 11 10 Bit(s) 15-8 7-0 9 8 7 6 5 4 3 2 1 0 Description This value specifies the number of cells that can be transmitted from high priority connections in one time window. This value specifies the number of cell times in the window. pnr25.chapt05.01 August 14, 2000 Performance Registers Page 289 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.18: Medium Priority Bandwidth Limit Register This register can be used to limit the bandwidth used by medium priority connections. The upper eight bits of this register specify the number of medium priority cells that can be sent in a window specified by the lower eight bits of this register. If no data needs to be sent by low priority connections, medium priority connections will not be limited. Length Type Address Power On Value Restrictions Cells Transmitted 16 bits Read/Write XXXX 1274 X'00000000' None Cell Times in Window 15 14 13 12 11 10 Bit(s) 15-8 7-0 9 8 7 6 5 4 3 2 1 0 Description This value specifies the number of cells that can be transmitted from medium priority connections in one time window. This value specifies the number of cell times in the window. 10.19: Low Priority Bandwidth Limit Register This register can be used to limit the bandwidth used by low priority connections. The upper eight bits of this register specify the number of low priority cells that can be sent in a window specified by the lower eight bits of this register. Length Type Address Power On Value Restrictions Cells Transmitted 16 bits Read/Write XXXX 1278 X'00000000' None Cell Times in Window 15 14 13 12 11 10 Bit(s) 15-8 7-0 9 8 7 6 5 4 3 2 1 0 Description This value specifies the number of cells that can be transmitted from low priority connections in one time window. This value specifies the number of cell times in the window. Performance Registers Page 290 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.20: High Priority Cells Transmitted Counter This register contains the number of cells transmitted from high priority connections. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1260 X'00000000' None Number of High Priority Cells Transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 This value represents the number of cells transmitted from high priority connections. 10.21: Medium Priority Cells Transmitted Counter This register contains the number of cells transmitted from medium priority connections. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1264 X'00000000' None Number of Medium Priority Cells Transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 This value represents the number of cells transmitted from medium priority connections. pnr25.chapt05.01 August 14, 2000 Performance Registers Page 291 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.22: Low Priority Cells Transmitted Counter This register contains the number of cells transmitted from low priority connections. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1268 X'00000000' None Number of Low Priority Cells Transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 This value represents the number of cells transmitted from low priority connections. Performance Registers Page 292 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.23: Bytes Queued Counters These registers (12) contain the number of bytes queued for transmission for each priority (3) on each drop (4). The addresses are assigned to the range in the following order: High priority High priority High priority High priority Medium priority Medium priority Medium priority Medium priority Low priority Low priority Low priority Low priority Port 0 Port 1 Port 2 Port 3 Port 0 Port 1 Port 2 Port 3 Port 0 Port 1 Port 2 Port 3 Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1290-2BC X'00000000' None Number of bytes Waiting to be Transmitted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description 9 8 7 6 5 4 3 2 1 0 This value represents the number of bytes waiting to be transmitted for each priority on each drop. pnr25.chapt05.01 August 14, 2000 Performance Registers Page 293 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Debugging Register Access This section contains registers that are for debug purposes only. These registers need not be written or read during normal operations. 10.24: Fast Serviced Counters There are three fast serviced counters, one for each transmit priority: high, medium, and low. These registers contain the value of the last fast time slot that has been serviced. When this count differs from the current timeslot count, at least one fast slot needs servicing. Each time the fast slot is serviced, this counter will increment. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 1240 XXXX 1244 XXXX 1248 X'0000' This register is meant to be read only. It is writable for diagnostic purposes only. Fast Serviced Counters 15 14 13 12 11 10 Bit(s) 15-0 9 8 7 6 5 4 3 2 1 0 Description This value represents how many times this time wheel has been serviced since the counter rolled over. 10.25: Slow Serviced Counters There are three slow serviced counters, one for each transmit priority: high, medium, and low. These registers contain the value of the last slow time slot that has been serviced. When this count differs from the current timeslot count, at least one slow slot needs servicing. Each time the slow slot is serviced, this counter will increment. Length Type Address Power On Value Restrictions 10 bits Read/Write XXXX 124C XXXX 1250 XXXX 1254 X'000' This register is meant to be read only. It is writable for diagnostic purposes only. Slow Serviced Counters 9 8 Bit(s) 9-0 7 6 5 4 3 2 1 0 Description This value represents how many times this slow wheel has been serviced since the counter rolled over. Debugging Register Access Page 294 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.26: Timer Serviced Counters In addition to the counters above, there is an additional counter for processing timer requests. These registers contain the value of the last timer slot that has been serviced. When this count differs from the current timeslot count (bits 22-15), at least one slow slot needs servicing. Each time a timer slot is serviced, this counter will increment. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 1280 X'00' This register is meant to be read only. It is writable for diagnostic purposes only. Service Count 15 14 13 12 11 10 Bit(s) 15-0 9 8 7 6 5 4 3 2 1 0 Description This value represents how many times this timer wheel has been serviced since the counter rolled over. pnr25.chapt05.01 August 14, 2000 Debugging Register Access Page 295 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.27: CSKED Status Register This register is used to control the actions of CSKED. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Restrictions Power On Value Medium Priority Serviced Counter Medium Priority Serviced Counter 14 bits Clear/Set XXXX 1228 and 22C None X'0' Medium Priority Serviced Counter Medium Priority Serviced Counter Virtual Memory Error Detected High Priority Serviced Counter High Priority Serviced Counter High Priority Serviced Counter High Priority Serviced Counter Low Priority Serviced Counter Low Priority Serviced Counter Low Priority Serviced Counter Low Priority Serviced Counter 1 13 12 11 10 Bit(s) 9 8 7 6 Name 5 4 3 2 Current Timeslot Counter 0 Description 13 Virtual memory error detected If a virtual memory write operation could not complete because a real buffer was not available, a signature is written to the packet header. If this signature is detected when the buffer is enqueued for transmission, this bit will be set and an event will be posted to RXQUE. High priority serviced counter has overrun on drop 3. Medium priority serviced counter has overrun on drop 3. Low priority serviced counter has overrun on drop 3. High priority serviced counter has overrun on drop 2. Medium priority serviced counter has overrun on drop 2. Low priority serviced counter has overrun on drop 2. High priority serviced counter has overrun on drop 1. Medium priority serviced counter has overrun on drop 1. Low priority serviced counter has overrun on drop 1. High priority serviced counter has overrun on drop 0. Medium priority serviced counter has overrun on drop 0. Low priority serviced counter has overrun on drop 0. Current timeslot counter has wrapped. If this bit is on, the timeslot counter has wrapped. 12 11 10 9 8 7 6 5 4 3 2 1 0 High priority serviced counter Medium priority serviced counter Low priority serviced counter High priority serviced counter Medium priority serviced counter Low priority serviced counter High priority serviced counter Medium priority serviced counter Low priority serviced counter High priority serviced counter Medium priority serviced counter Low priority serviced counter Current timeslot counter Debugging Register Access Page 296 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.28: CSKED Interrupt Enable Register This register is used to enable interrupts from CSKED. If a bit is on in the status register and the corresponding enable bit is on in this register then an interrupt will be generated if enabled in INTST. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 14 bits Clear/Set XXXX 1238 and 23C X'0' None Enables Interrupts 13 12 11 10 Bit(s) 13-0 9 8 7 6 5 4 3 2 1 0 Description Enables interrupts 10.29: CSKED Timing Data Array Pointer The CSKED Timing Data Array contains data relevant to scheduling cells. It contains 96 32-bit words. It should only be written for diagnostic purposes to test the array. It will power up to all zeros and should be rewritten to zeros after the array has been tested. This register points to an offset in the CSKED timing data array for accesses from the PCI bus. This register must be loaded with the correct offset before the desired data can be read from the CSKED timing data array data register. This register will auto-increment after each access to the associated data register. When the last address is accessed, this register wraps to zero. Length Type Address Power On Value Restrictions 9 bits Read/Write XXXX 12C0 X'000' None Not Used 2 1 0 Description These bits provide an offset into the CSKED cell staging array for accesses from the PCI bus. These bits provide access to the 256 unique four-byte locations in the array. Accessing the last location in the array will cause the address to wrap back around to the beginning of the array. These bits are not implemented. They cannot be written and will always return '0' when read. Offset into CSKED 8 7 Bit(s) 8-2 1-0 6 5 4 3 pnr25.chapt05.01 August 14, 2000 Debugging Register Access Page 297 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.30: CSKED Timing Data Array Data This register is used to access the array pointed to by the CSKED Timing Data Array Pointer. Length Type Address Power On Value Restrictions Should be written for diagnostic use only. Initialize back to '0's when through testing. Access Data 32 bits Read/Write XXXX 12C4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Access data Description 9 8 7 6 5 4 3 2 1 0 10.31: CSKED Time Wheel Array Pointer The CSKED Time Wheel Array contains data relevant to scheduling cells. It contains 16K 19-bit words. It should only be written for diagnostic purposes to test the array. It will power up to all zeros and should be rewritten to zeros after the array has been tested. This register points to an offset in the CSKED time wheel array for accesses from the PCI bus. This register must be loaded with the correct offset before the desired data can be read from the CSKED Time Wheel Array Data register. This register will auto-increment after each access to the associated data register. When the last address is accessed, this register wraps to zero. Length Type Address Power On Value Restrictions 17 bits Read/Write XXXX 12C8 X'000' None Not used 6 5 4 3 2 1 0 Description These bits provide an offset into the CSKED cell staging array for accesses from the PCI bus. These bits provide access to the 16K unique 19-bit locations in the array. Accessing the last location in the array will cause the address to wrap back around to the beginning of the array. These bits are not implemented, they can not be written and will always return '0' when read. Offset into CSKED 16 15 14 13 12 11 10 Bit(s) 16-2 1-0 9 8 7 Debugging Register Access Page 298 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.32: CSKED Time Wheel Array Data This register is used to access the array pointed to by the CSKED Time Wheel Array Pointer. Length Type Address Power On Value Restrictions Should be written for diagnostic use only. Initialize back to zeros when through testing. Access Data 19 bits Read/Write XXXX 12CC 18 17 16 15 14 13 12 11 10 Bit(s) 18-0 Access data 9 8 7 6 5 4 3 2 1 0 Description 10.33: CSKED LCD Cache Array Pointer The CSKED LCD Cache Array contains the transmit portion of LCDs used by CSKED and SEGBF. It contains 64 32-bit words. It should only be written for diagnostic purposes to test the array. It will power up to all zeros and should be rewritten to zeros after the array has been tested. This register points to an offset in the LCD Cache array for accesses from the PCI bus. This register must be loaded with the correct offset before the desired data can be read from the LCD Cache Array Data register. This register will auto-increment after each access to the associated data register. When the last address is accessed, this register wraps to zero. Length Type Address Power On Value Restrictions 18 bits Read/Write XXXX 1318 X'000' None Not used 7 6 5 4 3 2 1 0 Description These bits provide an offset into the CSKED cell staging array for accesses from the PCI bus. These bits provide access to the 64 unique 32-bit locations in the array. Accessing the last location in the array will cause the address to wrap back around to the beginning of the array. These bits are not implemented. They can not be written and will always return '0' when read. Offset into CSKED 17 16 15 14 13 12 11 10 Bit(s) 17-2 1-0 9 8 pnr25.chapt05.01 August 14, 2000 Debugging Register Access Page 299 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 10.34: CSKED LCD Cache Array Data This register is used to access the array pointed to by the CSKED LCD Cache Array Pointer. Length Type Address Power On Value Restrictions Should be written for diagnostic use only. Initialize back to zeros when through testing. Access Data 32 bits Read/Write XXXX 131C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Access data Description 9 8 7 6 5 4 3 2 1 0 10.35: CSKED Congestion Control Register CSKED can halt scheduling on up to 160 groups of connections. A connection specifies which group it belongs to by encoding the QNR(0-39) and DP(0-3) bits in the LCD. This register contains 160 bits which specify which of the 160 groups should be halted. Bit xx in the CSKED control register must be set in order to write to these bits from software. This register is read in eight groups of 20 bits. The group is specified by bits four through two of the address, with increasing addresses corresponding to increasing group numbers. Length Type Address Power On Value Restrictions 28 bits Read/Write XXXX 120F0-2FC X'000' None Specifies Segmentation will be Halted Specifies which Groups Written 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 27-20 19-0 9 8 7 6 5 4 3 2 1 0 Description These bits specify which eight groups of 20 bits will be written when writing this register. From one to all eight groups can be written at the same time, but all will be written with the same data specified in bits 19-0. When set, these bits specify that segmentation will be halted for all connections associated with the corresponding group. Debugging Register Access Page 300 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 10.36: State Machine Variables This register contains the current state of the three main state machines in this entity. Length Type Address Power On Value Restrictions 14 bits Read XXXX 1258 X'0000' None State Machine Variables 13 12 11 10 Bit(s) 13-0 9 8 7 6 5 4 3 2 1 0 Description Value of state machine variables. pnr25.chapt05.01 August 14, 2000 Debugging Register Access Page 301 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 11: ATM Transmit Buffer Segmentation (SEGBF) The segmentation buffer entity (SEGBF) accepts frames from the cell scheduler (CSKED) or software, and then generates ATM cells to send out over the external physical interface. This entity knows or cares nothing about scheduling cells over time; it will simply construct a cell when it is provided an address of a logical circuit descriptor to operate on. All rate and scheduling concerns must be addressed by the CSKED logic or software prior to queueing a frame to SEGBF. The SEGBF logic consists of four input LCD address latches, two specialized processors and the associated ROM/RAM for each, a 16-cell array buffer, and various support logic. The input latches and cell buffers are logically divided into four different drops, with each drop consisting of an input latch and four cell buffers. Under normal operation (CSKED providing LCD), the drop is defined by the drop field in the transmit LCD. When an LCD is enqueued by software, data bits five and six of the enqueued address define which drop the enqueued LCD is associated with. The four logical drops in SEGBF can be mapped to any of the physical link level addresses via registers in LINKC (LINKC Map Transmit Ports to Configuration). The processors fetch instructions from ROM/RAM and handle normal segmentation activity such as LCD update operations and cell generation functions. The type of cell that is generated by the segmentation logic is determined by the initial instruction pointer that is contained in the LCD structure. For example, software can enqueue an LCD that has the initial instruction pointer field set for normal AAL5 cells, and SEGBF will generate a single AAL5 cell as a result of the enqueue operation. If, however, software enqueues an LCD that has the initial instruction pointer field set for POS-PHY operation, then SEGBF will continue to generate buffers to pass to the link level until all the data has been exhausted. For a more complete description of the segmentation entry points, refer to the seg_prc_Entry_point field in the transmit LCD data structure section of this document. After the buffers/cells are built in a 16-by-64 byte array, they are marked as available to the link level layer (LINKT) in the IBM3206K0424. A simplified block diagram is shown in the SEGBF Block Diagram. ATM Transmit Buffer Segmentation (SEGBF) Page 302 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources SEGBF Block Diagram CSKED LCD Interface Software LCD Enq Interface Drop 0 Drop 1 Drop 2 Drop 3 RAM LCD Processor Cell Processor RAM Cell Array Drop 0 Cell 0 Drop 0 Cell 1 Drop 0 Cell 2 Drop 0 Cell 3 Drop 1 Cell 0 Drop 1 Cell 1 Drop 1 Cell 2 Drop 1 Cell 3 Drop 2 Cell 0 Drop 2 Cell 1 Drop 2 Cell 2 Drop 2 Cell 3 Drop 3 Cell 0 Drop 3 Cell 1 Drop 3 Cell 2 Drop 3 Cell 3 The sequence of events that happens when an AAL5 frame is enqueued to SEGBF is as follows: 1. An initial check is made to determine if there is space available in the cell buffer. If no space is available, processing stops for this drop until a cell buffer is freed by the link logic (LINKT). 2. When buffer space becomes available, the enqueued LCD address is requested from the transmit LCD cache (there are four entries in the LCD cache). The segmentation logic waits for a valid indication from the cache; at this time all LCD information is available to the segmentation logic on the LCD cache interface. 3. The initial instruction pointer (IP) is fetched from the LCD and loaded for both of the segmentation processors. Software controls what type of cells are generated by the segmentation logic by initializing this field in the LCD to the entry points defined for different types of cell generation. For a more complete description of the segmentation entry points, refer to the seg_prc_Entry_point field in the transmit LCD data structure section of this document. 4. Assuming an AAL5 entry point is setup in the LCD, the segmentation logic will first initiate a memory fetch of the data required to build the cell. 5. While the data fetch is in process, the segmentation processors will update various fields in the LCD including statistics and the next segmentation pointer. Cell construction will be started using the ATM pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 303 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary header from the LCD. 6. When the payload data is available from memory, it is written to the cell buffer following the header. 7. If the segmentation logic determines that the current cell being assembled will be the last cell of this frame, the AAL5 trailer is appended to the cell buffer, with any unused bytes being padded with zeros. 8. If the current cell is not the last of the frame, the partial CRC is written back out to the LCD. 9. After the cell has been completed, it is marked as available to the link level logic ATM Transmit Buffer Segmentation (SEGBF) Page 304 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.1: SEGBF Software LCD Enqueue This register provides a mechanism for software to transmit a single cell or a group of cells making up a buffer that can contain any user-defined data at any time. To cause a cell/buffer to be transmitted, the software must write the address of a valid LCD control block to this register. The segmentation hardware will then construct a cell to match the AAL type defined in the LCD control block, using the segmentation pointer contained in the LCD to fetch data and present this cell to the next lower level of hardware to transmit. This method of cell transmission bypasses the cell scheduler completely, so it is the responsibility of the software to ensure that peak and average rates are not violated. When the segmentation logic has completed building the cell/frame and queued it for transmission, the LCD address will be loaded into the software LCD complete register. This method of cell transmission is not designed for high performance and, as such, there is only a single level of queueing underneath the complete register. It is recommended that only a single software LCD be queued to the segmentation logic at any one time to prevent hanging the segmentation logic as it attempts to queue a complete software LCD to the complete queue. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1400 X'0000 0000' Before enqueing a VCI, software must ensure that the previous software enqueue has been handled by the hardware. This is accomplished by reading this register before an enqueue is attempted. If a value of '0' is returned, the segmentation hardware is ready to accept an enqueue operation. If a non-zero value is returned, it will be the address of the previous VCI that was enqueued and this indicates that the segmentation hardware has not been able to enqueue the VCI to it's internal VCI buffer segmentation queue. If this mechanism shows that this interface is busy and unable to accept new VCI addresses for any appreciable amount of time (tens of s), it is likely that a condition exists which is preventing the hardware below the segmentation logic from accepting cells for transmission, and the segmentation logics input buffer is full. This mechanism also adds the restriction that a VCI control block should never exist at address `0'. VCI Control Block Address Drop Cell Type 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-5 4-0 Description These bits contain the upper 25 bits of the address of the VCI control block. These bits define which drop this enqueue operation will be associated with. 9 8 7 6 5 4 3 2 1 0 These bits control what type of cell will be built by the segmentation logic. There are currently only two valid values for these bits. If these bits are all '0', a normal cell as defined by the LCD will be built. If these bits have a value of 0x1F, an ABR cell will be built using fields defined in the LCD. pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 305 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.2: SEGBF Control Register This register provides a mechanism to control the various programmable features of SEGBF. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Clear/Set XXXX 1408 and 40C X'98400000' None Enable Transmit Complete Logic Ignore All Requests from SCKED Disable LCD Statistics Wrapping Enter SEGBF Diagnostics Mode 0 Reset SEGBF Control Logic # of Buffers for "Not Ready" Queue "Complete" Event Steer Internal Status to ENSTATE Outputs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15 14 Description These bits are used to steer internal SEGBF status to the ENSTATE outputs. 9 8 7 6 5 4 3 2 This bit, when set, will cause the segmentation processors to free a software enqueued buffer after the last cell has been generated. This bit, when set, will cause the segmentation processors to queue a transmit complete event after the last cell has been generated for a software enqueued frame. This bit, when set, will cause the segmentation logic to pause when it reaches the idle state. Segmentation will not be continued until this bit has been reset. Care must be taken to leave this bit set for a very short duration so that segmentation throughput will not be adversely affected. Reserved These two bits define the prioritization scheme used by the segmentation logic to determine which drop to build a cell for when running in frame mode. A value of `00' will provide for equal priority among all drops, the drops will be processed in order from zero to three as long as data is available to segment and space is available in the cell buffer for the drop. A value of `01' will provide descending priority from drop 0 to drop 3. If data exists and a cell buffer is available for drop 0, a drop 0 cell will always be built regardless of the situation on any other drops. In this mode, a cell will only be built on drop three if all other drops either have not data or no cell buffer available. This bit, when set, will reset all control logic in the entity. After being set, this bit must be reset before the segmentation logic will function properly. This bit must remain set for at least one microsecond to reset the segmentation logic properly. These two bits define the number of cell buffers that can be filled on a given drop before a not ready condition is returned to the cell scheduler. This addresses latency issues caused by multiple cells waiting for transmission by the lower link level. A value of `00' allows all four cell buffers to be used at any time; a value of `01' allows one cell buffer to be used; a value of `10' allows two cell buffers to be used, and a value of `11' allows three buffers to be used. This bit, when set, enables the transmit complete event modification logic in the segmentation processors. This logic will retrieve two bits from the xmit_comp_evnt_mod field in the LCD and logically OR them with bits eight down to seven of the buffer address being enqueued to RXQUE. This logic only functions when buffer addresses are being queued; it will not modify the event if LCD addresses are being enqueued. This also adds the restriction that all buffer addresses must start on a 512-byte boundary or greater. 13 12-10 9-8 7 6-5 4 ATM Transmit Buffer Segmentation (SEGBF) Page 306 of 676 pnr25.chapt05.01 August 14, 2000 Disable Couner Wraps 1 Free Enqueued Buffer Pause at Idle Drop Priority Reserved IBM3206K0424 Preliminary Bit(s) 3 2 1 0 Description This bit, when set, disables the LCD statistics wrap events. This bit, when set, will cause all requests from the cell scheduler to be ignored. This allows complete program control of all cells being sent out on the external interface. This bit, when set, disables the programmable counter wrap events. This bit, when set, causes the SEGBF entity to enter diagnostic mode. This bit must be set in order to access the internal array. When accessing the array, care must be taken that normal entity reads and writes of the array are not happening at the same time or the results will be indeterminate. IBM Processor for Network Resources pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 307 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.3: SEGBF Status Register This register provides feedback to the user on the current status of SEGBF. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Cell Generation Complete 3 2 1 8 bits Clear/Set XXXX 1410 and 414 X'00' None Invalid Condition Detected 0 Description Reserved This bit, when set, indicates that the segmentation logic has completed cell generation for an LCD that was enqueued by the software to the software LCD enqueue register. This bit, when set, indicates that the segmentation logic has detected an invalid condition in one of the LCDs that it was processing. The address of the LCD in error is contained in the Invalid LCD register. Any invalid LCDs detected are not processed further by the segmentation logic, so the program must do something to clear this condition. Reserved 7 6 5 4 Bit(s) 7-2 1 0 ATM Transmit Buffer Segmentation (SEGBF) Page 308 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.4: SEGBF Invalid LCD Register This register provides feedback to the program when the segmentation logic detects an invalid LCD. If multiple invalid LCDs are being processed, this register will contain the address of the last one that was processed by the segmentation logic. There are several invalid LCD situations that the segmentation logic checks for: The first is the LCD address not being on the correct boundary. For example, if the chip is configured to have all LCDs on 128-byte boundaries and an LCD is encountered that is not on a 128-byte boundary. Another invalid condition is when the transmit length configured in the LCD plus the offset in the LCD when added together exceed the maximum overall packet size configured in the chip. It is up to the program to determine which of the possible conditions caused the error to be reported. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1418 X'00000000' None Detected VCD Error Address Always Read as `0' 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-0 Description These bits contain the 32-bit address of the LCD detected to be in error. Reserved. Always read as '0'. 9 8 7 6 5 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 309 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.5: SEGBF Software LCD Complete This register provides feedback to the program when the segmentation logic completes cell generation for an LCD that was enqueued by the software. After the segmentation logic has updated the LCD, the address of the LCD is copied into this register providing any previous LCD addresses written to this register have been read by the software. If multiple software queued LCDs are outstanding to the segmentation logic at any time, the segmentation process can be delayed when multiple software enqueued LCDs complete without the software getting a chance to read the LCD addresses from this register. To guarantee that the segmentation logic never has to wait for the software to read this register, it is recommended that only one software LCD be enqueued at any one time. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 141C X'00000000' Bits 5 through 0 are not implemented and will always return '0'. To maintain future compatibility, '0's should be written to these bits. Last Cell 1 0 Upper 25 Bits of LCD Address Drop Read as 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6-5 4-1 0 Description 9 8 7 6 5 4 3 2 These bits contain the upper 25 bits of the LCD address that the segmentation logic has finished processing. These bits indicate the drop on which the cell was sent. These bits will read back as '0'. This bit will be set when the cell that was built was the last cell of a frame and reset if the cell that was built was not the last cell of a frame. ATM Transmit Buffer Segmentation (SEGBF) Page 310 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.6: SEGBF Interrupt Enable Register This register allows the user to selectively determine which bits in the SEGBF status register will cause processor interrupts. A '0' in a bit position masks interrupts from the corresponding bit location in the SEGBF status register. A '1' in a bit position allows interrupts for the corresponding bit in the SEGBF status register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 12 bits Clear/Set XXXX 1420 and 424 X'00' None 11.7: SEGBF Programmable Counters This register provides the user with feedback on the number of times that a particular event or condition has occurred in the segmentation logic. The event or condition that causes this counter to increment is defined by the associated SEGBF Programmable Counter Source Specification register. When the counter wraps, an event is generated. Length Type Address 32 bits Read/Write Counter 0 Counter 1 Counter 2 Counter 3 Power On Value Restrictions X'0000 0000' None Count of Occurrences XXXX 1430 XXXX 1434 XXXX 1438 XXXX 143C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description These bits contain a count of the occurrences of the desired event or condition. 9 8 7 6 5 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 311 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.8: SEGBF Transmit LCD Size This register should be loaded with the number of eight-byte words that are needed for the maximum-sized LCD that will be setup by software. Refer to the previous section describing LCD layout to determine the number of words required to support the different modes. The minimum value is six. This is the correct value when running only AAL5 mode; it includes three words of scheduling information, two words shared between CSKED and SEGBF, and one word for SEGBF to maintain statistics. Setting this register to a value that is too small will likely cause the chip to function improperly. Setting this register to a value that is too large will adversely affect performance. Length Type Address Power On Value Restrictions Number of Words 4 bits Write/Read XXXX 1488 X'6' (This is the correct value when running AAL5 with statistics.) Minimum is 6, maximum is 0xA 3 2 1 0 Description These bits contain the number of eight-byte words in the LCD to be used by the transmit logic. Bit(s) 3-0 ATM Transmit Buffer Segmentation (SEGBF) Page 312 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.9: SEGBF Cell Queue Status This register indicates the number of cells queued up for transmission over the media. SEGBF can have a maximum of 16 cells queued up for transmission: four cells on each of four drops. When a bit is set to '1', the corresponding cell buffer contains a cell that has not been completely processed by the link logic. Length Type Address Power On Value Restrictions 16 bits Read XXXX 148C X'0000' None Incomplete Cell Incomplete Cell Incomplete Cell Incomplete Cell in Drop 3 in Drop 2 in Drop 1 in Drop 0 15 14 13 12 11 10 Bit(s) 15-12 11-8 7-4 3-0 9 8 7 6 5 4 3 2 1 0 Description These bits indicate which cell buffers contain cells that have not been processed by the link level for drop 3. These bits indicate which cell buffers contain cells that have not been processed by the link level for drop 2. These bits indicate which cell buffers contain cells that have not been processed by the link level for drop 1. These bits indicate which cell buffers contain cells that have not been processed by the link level for drop 0. pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 313 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.10: SEGBF Processor 1 Control/Status Reading this register provides feedback to the user on the current state of segmentation processor 1. Writing the appropriate bits in this register causes processor 1 to begin executing at a new location specified in the data that was written. Length Type Address Power On Value Restrictions 32 Read/Write XXXX 14A0 X'0000C000' None Reset Processor 1 Reserved Halt Processor 1 Load IP 1 Reserved Instruction Pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15 14 13 12-9 8-0 Reserved Description 9 8 7 6 5 4 3 2 1 0 Writing `0' to this bit causes the instruction pointer (IP) for processor 1 to be loaded with the data in bits 8 down to 0. This bit will immediately be set back to '1' after the IP load completes. Writing `0' to this bit halts processor 1. Writing '1' makes the processor fetch and execute instructions. Setting this bit to '1' resets processor 1. Reserved. When written, these 9 bits contain the new IP for processor 1. When read, these bits reflect the current IP for processor 1. ATM Transmit Buffer Segmentation (SEGBF) Page 314 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.11: SEGBF Processor 2 Control/Status Reading this register provides feedback to the user on the current state of segmentation processor 2. Writing the appropriate bits in this register causes processor 2 to begin executing at a new location specified in the data that was written. Length Type Address Power On Value Restrictions 32 Read/Write XXXX 14A4 X'0000C000' None Reset Processor 2 Reserved Load IP 2 Halt Processor 2 Reserved Instruction Pointer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15 14 13 12-9 8-0 Reserved Description 9 8 7 6 5 4 3 2 1 0 Writing a '1' to this bit will cause the instruction pointer (IP) for processor 2 to be loaded with the data in bits 8-0. This bit will immediately be set back to a '1' after the IP load completes. Writing a '0' to this bit will halt processor 2; writing a '1' will make the processor fetch and execute instructions. Setting this bit to a '1' will reset processor 2. Reserved When written, these nine bits contain the new IP for processor 2. When read, these bits reflect the current IP for processor 2. pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 315 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.12: SEGBF Programmable Counter Source Specification This register determines what event or condition will cause the associated counter to increment. Length Type Address 32 Read/Write Counter 0 Counter 1 Counter 2 Counter 3 Power On Value Counter 0 Counter 1 Counter 2 Counter 3 Restrictions None Count All Drops XXXX 14B0 XXXX 14B4 XXXX 14B8 XXXX 14BC X'000 0803' X'000 0903' X'008 0803' X'002 0203' Reserved Event Source Data Byte Mask Byte SpecificDrop Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-27 26-25 Reserved. Description 9 8 7 6 5 4 3 2 1 0 These bits select the source of the event to be counted. '00' selects the cell events that are further defined in bits 23 down to 0 of this register. '01' selects the number of bytes transmitted on a given drop. '10' selects the number of frames transmitted on a given drop. The drop is selected by bits seven and six, or all drops can be included by setting bit 24. This bit, when set, causes the counter to count the specified event for all drops, not just the drop specified in bits seven and six. These bits define the data byte that is compared to the result of logically anding the data byte being written to the cell array at the offset specified in bits 5-0 with the mask in bits 15-8. If there is an exact match, the counter will increment. These bits define the mask byte to be logically anded with the data byte being written to the cell array. These bits determine which drop this counter is associated with. These bits define a byte offset into the cell being built in the segmentation cell array. Zero corresponds to the first byte in the cell and 63 corresponds to the last byte in the cell. When the segmentation logic copies a byte of data into the cell array at this offset, the logic compares the byte defined in bits 23-16 to the logical and of the data being written and the mask defined in bits 15-8 of this register. If an exact match is detected, the counter will be incremented. 24 23-16 15-8 7-6 5-0 ATM Transmit Buffer Segmentation (SEGBF) Page 316 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.13: SEGBF Cell Staging Array Pointer This register points to an offset in the SEGBF cell staging array for accesses from the PCI bus. This register must be loaded with the correct offset before the desired data can be read from the SEGBF Cell Staging Array Data Register. This register will auto-increment after each access to the associated data register. When the last address is accessed, this register wraps to zero. Length Type Address Power On Value Restrictions Offset 10 Read/Write XXXX 14C0 X'000' None `00' 9 8 Bit(s) 9-2 1-0 7 6 5 4 3 2 1 0 Description These bits provide an offset into the SEGBF cell staging array for accesses from the PCI bus. These bits provide access to the 256 unique four-byte locations in the array. Accessing the last location in the array will cause the address to wrap back around to the beginning of the array. These bits are not implemented, they can not be written and will always return `0' when read. pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 317 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 11.14: SEGBF Cell Staging Array Data This array is divided into 16 64-byte buffers used to assemble cells that are ready for transmission on the physical interface. Length Type Address Power On Value Restrictions 32 Read/Write XXXX 14C4 Undefined This array can only be accessed when the diagnostic mode bit in the control register is set. Accesses attempted when not in diagnostic mode will return 0xBADDBADD. 11.15: SEGBF Instruction SRAM Pointer This register points to an offset in the SEGBF SRAM that is used to store processor instructions. This register must be loaded with the correct offset before the desired data can be read/written from/to the SEGBF instruction SRAM data register. This register will auto-increment after each access to the associated data register. When the last address is accessed, this register wraps to zero. The first 256 locations in the array should be loaded with the instructions for processor 1, and the second 256 locations should be loaded with the instructions for processor 2. Length Type Address Power On Value Restrictions Offset 10 Read/Write XXXX 14C8 X'000' None `0' 9 8 Bit(s) 9-1 0 7 6 5 4 3 2 1 0 Description These bits provide an offset into the SEGBF instruction SRAM for accesses from the PCI bus. These bits provide access to the 512 unique two-byte locations in the array. Accessing the last location in the array will cause the address to wrap back around to the beginning of the array. This bit is not implemented; it can not be written and will always return `0' when read. ATM Transmit Buffer Segmentation (SEGBF) Page 318 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 11.16: SEGBF Instruction SRAM Data This register address can be used to read/write the instruction data that is needed by the segmentation processors. All instructions must be written before the processors can be brought out of the halt state. Length Type Address Power On Value Restrictions 16 Read/Write XXXX 14CC Undefined This array can only be accessed when the processors are in the halt state. Reads attempted when the processor is in run mode will return invalid data. Writes attempted when the processor is in run mode will be ignored. 11.17: MPEG-2 PCR Increment Register Each tick of the time base will add the contents of this register to the MPEG PCR Reference Register. This register contains a fixed point number with 27 bits of fraction and five bits of units. This means that the external reference clock can range in speed from 22.5 Khz to the maximum speed of this entity which is TBD. Assuming that the entity will run with a 50 Mhz clock, the conversion to 720Khz can be done with an accuracy of 1.1 parts in two million. (A clock of 19.4 Mhz will give a conversion accuracy of one part in 4.9 million.) If the input clock is 19.4 Mhz, then the value to put in the increment register is (720,000 / 19,400,000) * 2**27 or 4,981,277. If the input clock is 33 Mhz, then the value to put in the increment register is (720,000 / 16,666,666) * 2**27 or 5,798,206. Length Type Address Power On Value Restrictions Units 32 Read/Write XXXX 1468 X'002C3C9F' (33 Mhz) None Fraction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-27 26-0 Description These bits contain the whole part of the increment value. These bits contain the fractional part of the increment value. 9 8 7 6 5 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 ATM Transmit Buffer Segmentation (SEGBF) Page 319 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Receive Data Path Entities Entity 12: Cell/Packet Re-assembly (REASM) REASM is the top level receive entity that encapsulates all of the receive sub-entities. Note: The receive portion of the chip is very different from previous versions of the processor. REASM no longer does HEC correction or detection, since everything we interface to already does this function. The following figure shows how REASM interacts with the other entities: REASM Entity Interfaces POOLS RXQUE DMAQS COMET PAKIT INTST REASM PCINT LINKR Cell/Packet Re-assembly (REASM) Page 320 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources REASM is made up of a number of sub-entities to provide the overall receive functionality. REASM contains the following sub-entities: RXBUF RXXLT RXCRC RXAAL RXLCD Provides receive cell/packet buffering between LINKC and REASM. Also defines the port configurations and mappings. Provides general LCD translation facilities. Provides CRC facilities. Performs the Cell And Packet reassembly functions including AAL processing and all Cell and Packet Post-Processing functions. Provides RX LCD caching for the REASM sub-entities. REASM Sub-Entity Block Diagram POOLS COMET PAKIT RXQUE DMAQS RXLCD RXXLT RXCRC RXAAL REASM RXBUF LINKR RXXLT, RXCRC, and RXAAL form a cell processing pipeline. Each stage is allowed up to a cell time to process the cell it is currently working on. This means each cell has the potential to have a three-cell time latency through the REASM entity. The overall performance should be at its maximum since a single cell completes processing every cell time. The stages are allowed to run faster if there is no blocking condition. The only blocking condition is the latency of memory accesses and the total length of the nano-program that needs to run. The following sections provide a brief description of each sub-entity and the function it provides. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 321 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Miscellaneous Reassembly Functions ATM OAM Cell Processing When processing an ATM data stream, OAM cell processing may be necessary. This function needs to be enabled in the REASM Reassembly Modes Register. REASM performs OAM discrimination when enabled. This function can be enabled on a per port basis. As cells arrive for processing, the nano-code works together with some dedicated logic to discriminate between different types of OAM cell traffic. Each type that is discriminated produces a different event when traffic is surfaced to a receive queue. The different types that are discriminated are: Segment End to End Segment End To End Forward Cell Backward Cell Reserved Cell End to End Alarm Segment Alarm End to End Loopback Segment Loopback End to End Pm Cell Segment Pm Cell End to End Activate/Deactivate Cell Segment Activate/ Deactivate Cell VCI = 0003 VCI=0004 Not F4 and PTI field = "100" Not F4 and PTI field = "100" PTI = "110" and DIR=0 PTI = "110" and DIR=1 PTI field = "111" End to End and OAM type=0001 and func=0000 or 0001 Segment and OAM type=0001 and func=0000 or 0001 End to End and OAM type=0001 and func=1000 Segment and OAM type=0001 and func=1000 End to End and OAM type=0010 Segment and OAM type=0010 End to End and OAM type=1000 Segment and OAM type=1000 Both the RXCRC and RXAAL nano-code understand and process OAM traffic differently when enabled. In the receive LCD there are control bits that allow the user to specify on a per connection basis how the OAM traffic should be handled. There are two types of flows when processing OAM traffic. A connection can be either "routed" or "terminated." A terminated connection is any connection that terminates either cells or packets. AAL5 and packet LCDs that are fast forwarded are considered "terminated" because the packet is terminated before the packet is fast forwarded. A "routed" connection is a raw LCD that is fast forwarded including raw mode with early packet discard. When OAM traffic is processed on a "terminated" connection, the OAM traffic can be terminated or dropped based on the discrimination configuration bits in the receive LCD. A mask value of '0' specifies to terminate the cell, and a mask value of '1' specifies to drop the cell. When OAM traffic is processed on a "routed" connection, the OAM traffic can be fast forwarded or dropped based on the discrimination configuration bits in the receive LCD. A mask value of '0' specifies to fast forward the cell, and a mask value of '1' specifies to drop the cell. This allows the user to filter the OAM traffic based on the type of OAM traffic on a per connection basis. The mask bit is determined by using the sub-type mask bit if pertinent. For example, an F5 Segment Pm Cell will use the "Segment Pm Cell" mask bit. If one of the sub-types does not match, then the basic types are Cell/Packet Re-assembly (REASM) Page 322 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources used (that is, F4 End-to-end). There is a 16-bit mask field in the receive LCD. A description of each bit is in the table below: Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved F4 segment F4 End to End F5 Segment F5 End to End Rm Forward Cell Rm Backward Cell Pti Reserved Cell End to End Alarm Segment Alarm End to End Loopback Segment Loopback End to End Pm Cell Segment Pm Cell End to End Activate/Deactivate Cell Segment Activate/Deactivate Cell Description When an OAM cell is processed, the configuration information from the gpmtagE is used to make reassembly decisions like which buffer pool or receive queue to use. TCP/IP Receive Checksum Verification When enabled, the IBM3206K0424 is able to perform verification of the IP header checksum and the associated protocol checksum for the user. The final checksum status is raised to the user in the packet header flags. This function is accomplished by the RXCRC entity using the CRC nano-program. To enable and use the function, several things must be done: * TCP/IP checksum function must be enabled in the REASM Mode Register. This enables the overall function and includes the checksum state words in the receive portion of the LCD. * Specify a frame type in the frameType field of the receive LCD. This field specifies an entry point into the checksum verification nano-code. The entry point points to a piece of code that understands how to locate the IP header based on the current frame type. For example, a connection might be native IP over ATM or LANE ETH. For the currently supported types, see the crc.txt file provided with the RXCRC code load. Note: Other types can be added if needed. Once properly enabled, TCP/IP checksums are verified as packets arrive. The status is raised to the user in the packet header using four bits of status (two bits for IP and two bits for protocol). The format and meanings of the bits are specified in Packet Header. For connections that have mixed traffic, the checksum operation is only run on packets that are recognized as TCP/IP. For example, on a LANE ETH connection packets of different protocols can be interleaved. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 323 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Scatter/Cut Through Receive Processing The scatter/cut through support is very versatile and easy to use. Scatter typically refers to scattering pages from a contiguous IBM3206K0424 buffer into multiple non-contiguous host pages. Cut through refers to moving contiguous data from IBM3206K0424 buffers into contiguous storage in host memory. The functions are similar, and the terms scatter and cut through may be interchanged in the following text since cut through is really a special case of scatter. The correct term is used when context requires it. The scatter processing is performed by RXAAL along with RXQUE and DMAQS. The following items need to be setup: * DMAQS should be setup and ready to run. * RXQUE should be setup and ready to run. Each queue that is used should have the proper event size selected, the direction should be set correctly, and timestamps and bcach advice should be disabled. * Page buffers or descriptors should be placed on the configured receive queues. * The scatter configurations need to be set in the RXALL - Scatter/Cut Through Info Registers. * The scatter flags need to be set in the RXALL - Scatter/Cut Through Flag Registers. * Each LCD that is to use scatter, needs to have the ppMode field set to do scatter. * A scatter configuration needs to be selected for each connection by setting the cutThruSel field in the receive LCD. Once set up, the scatter mechanism is performed by RXAAL for the user. There is user intervention required to process the packets when the scatter is complete, and for page recovery in error scenarios. There are many options when setting up scatter, and the selection of the type of scatter processing to perform depends on the users environment. The basic scatter mechanism will be described followed by a discussion of the different options that can be used. When packets are received and scattered, the following structure shows the main components of the received packet: General Layout of a Received Packet in Scatter Mode struct ScatterRxPacket { packetHeader; // Charm packet header dmaList; // Scatter dma list padbytes; // Pad out to receive offset from lcd packetData; // Actual receive packet }; The DMA list is maintained immediately after the IBM3206K0424 packet header, and before the receive packet data. For this reason, the user should allocate enough space between the packet header and the packet data to accommodate a maximum-sized DMA list based on the maximum number of pages that could be DMAed. The rxOffset field in the receive LCD is where this offset is specified. The maximum receive offset is 256 bytes, which is specified with an rxOffset value of '0'. The following is the layout of the DMA list: Cell/Packet Re-assembly (REASM) Page 324 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources General Layout of a Scatter DMA List struct dmaList { bit16 numHeadbytes; bit16 numTailbytes; // number of bytes included with header dma // number of bytes in last dma page bit1 deqLocked; // error status bit1 deqInvalid; // " bit1 headerTruncated; // " bit1 badDmaList; // " bit4 DeqLockedQueueNum; // " bit16 reserved; bit2 cutThruSel; // copy of cutThruSel used from receive lcd bit6 numPages; // number of page entries that follow (max=63) bit32 pageList[N]; // Actual dma descriptors or page addresses // Note: each entry can be 32, 64, or 128 bits wide }; The first eight bytes are always present and are filled in when the packet is complete or when an error occurs. The actual page list is filled in as the data is DMAed. The first location is initially skipped and is filled in later when the header is DMAed. The second and subsequent entries are filled as each page is DMAed. Each page list entry contains either physical page addresses, IBM3206K0424-based DMA descriptor addresses, or user data. Whether a physical page address or DMA descriptor address is present depends on the cut through configuration. From here on, the term page address and DMA descriptor are used interchangeably as either is valid based on the configuration, but the correct term is used when the context requires it. A page list entry can contain one or two pieces of information. Each page list entry can be 32, 64, or 128 bits long. If using 32 bit addresses, then the entry is 32 or 64 bits. If using 64-bit addresses, then the entry is 64 or 128 bits. The first piece is always the page address or the DMA descriptor address. Each cut through configuration allows the user to specify an optional second deque operation from the receive queue being used. This allows the user to place user information associated with the particular page address in the receive queue and the page list. Thus, the corresponding virtual address of a page could be surfaced along with the physical page address. It is very important to enque information to the receive queue in the proper order if using this mode. The physical page address is first, followed by the user information. As the receive packet data is being received, it is DMAed as soon as a page crossing occurs if there is a DMA descriptor available on the receive queue being used. If no descriptor is available, then no DMA takes place until the next receive cell is received, at which time the receive queue availability is checked again. This catch-up process continues until the packet is complete. When the packet is complete, all DMAs are scheduled if page addresses are available. If a page address is not available, then a "no DMA descriptor available" is surfaced to the user so the packet can be used and the DMA list recovered. As each data page is DMAed to the user, a DMA descriptor is formed and enqueued to the DMAQS DMA queue specified in the cut through configuration. The DMA descriptor is formed based on if page addresses or DMA descriptor are provided on the receive queue being used. If IBM3206K0424-based DMA descriptors are being used, then the receive queue contains DMA descriptor chains where the low order bits of the DMA descriptor address specify how many descriptors are in the chain. Typically, this chain length is one, but more can be used. The first descriptor in the chain provides the destination address (page address) which is filled in by the user. The source address, the length, and the flags are filled in by the IBM3206K0424 for the first descriptor in the chain. The source address is filled in with the beginning address of the page within the current receive buffer. The length is filled in with either the page size (if a full page is present) or the number of bytes in the last page for the last page. The flags are filled in using the flags from the appropriate RXALL Scatter/Cut Through Flag Registers. If physical page addresses are contained in the receive queue, then a pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 325 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary single DMA descriptor is formed by DMAQS directly in DMA queue storage using the page address and the same information that would have been filled into the DMA descriptor. Generally, using page addresses performs better, but is less versatile, which is usually a good trade off. Normally no DMA event is generated in the flags when pages are DMAed. When the last cell of a packet is received, and all the data pages have been DMAed, the packet header and DMA list are updated and DMAed into a header buffer. The mechanism and configuration of the header buffer is similar to the pages, but separate configuration is usually necessary for correct functionality. For example, different flags are normally used in order to get an event for the header DMA so the user can process the packet. The header DMA normally frees the IBM3206K0424 buffer; another difference is the page (or buffer) size used for headers is normally different than the normal page size. Some of the optional features described later also drive having different configuration for the header DMAs. Once the user gets the event for the header DMA, the user processes the received packet using the DMA list and the packet header. Once the packet has been processed, the pages or descriptors need to be returned to the proper receive queue when the pages can be reused, thus completing the scatter processing. There are several ways of getting that important event to start the receive processing. Usually the event is generated when the last header DMA is complete. If DMA descriptors are being used, then there are two choices. First, the normal DMA flag that generates an event can be used. This generates an event with the DMA descriptor address in the significant bits. While this works and may be desirable in some environments, the DMA descriptor needs to be read in order to get access to the host header buffer address. The second way to generate an event when using descriptors is to provide a second DMA descriptor in the DMA descriptor chain that enqueues the header buffer address and a user-defined event in the lower order bits. Generating an event in this manner provides the user with the buffer address; the header DMA descriptor address is available in the header buffer as part of the DMA list. When using page addresses, the event source in the cut through configuration should be set to use the destination address as the event data. When this is done, the event data contains the header buffer address as in the second case above. Error Recovery There are two types of error that need to be handled. First, if there is no error on the receive packet and a page address was not available, then the packet is surfaced to the user with a "no DMA descriptor available" event in the event type field and the IBM3206K0424 buffer address in the event information field. The user has a choice at this point. The packet is good so it can be used or freed by the user. In either case, the DMA list in the packet header must be recovered. So if the DMA list in the header is not used, it should be recovered by returning it to the proper receive queues. The event surfaced specifies which type of page address failed so the user can parse the DMA list properly. The event will specify whether a normal page descriptor, optional header descriptor, or packet header descriptor. The same descriptor recovery must be performed when an error event is surfaced (that is, CRC error). When there is an error event, no packet header DMA is performed so no packet header descriptor is in the DMA list. Scatter Options Most of the optional scatter features have to do with the header bytes and how the header DMA is performed. How the number of header bytes is determined is explained below. For now, just assume there are some number header bytes. The numHeadbytes field in the DMA header specifies the number of header bytes that are available. The location of the header bytes in the DMA buffers can be configured. The default is for them to be kept with the packet header and DMA list in the packet header buffer. For this case, the user should be sure the packet header buffer size is large enough to contain all of this data. Alternatively, the header bytes can be placed in a separate buffer. To do this, split header mode should be Cell/Packet Re-assembly (REASM) Page 326 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources enabled in the cut through configuration. This buffer is referred to as the optional header page and uses its own page size and receive queue to allow for better storage utilization. When enabled, the second entry in the DMA list becomes the optional header page entry, and should be treated accordingly for page recovery. In split header mode, the header bytes are DMAed as soon as they are all received. This mode is useful if the user environment requires the header bytes to be in a separate buffer from the packet header and DMA list. Another optional feature is to DMA the header only. This feature is enabled in the cut through configuration. When enabled, only the packet header, DMA list, and header bytes are DMAed. Either a single DMA or two DMAs occur based on if the optional header feature is enabled. This feature can be useful when a routing decision needs to be made for a packet and the entire packet does not need to be brought into host storage. Another possible scenario is the header bytes may determine how the user wants to DMA the packet data to the host. For smaller packet sizes, it may be more efficient to perform a single DMA and keep the packet header, DMA list, and packet data in a single buffer. To do this, single page mode should be enabled in the cut through configuration. When enabled, the header page size is used to determine the DMA behavior. If a packet completes and the total length of the packet and headers will fit in the header page size, then a single DMA is performed. If the data length exceeds the single page size as it is being received, the data is scattered using the normal options (might need to catch up). This feature can be useful for optimizing user processing for smaller packets. For example, all packets less than 2K might be a candidate for this feature. Head Bytes There are two ways to set the number of head bytes. They are set on a per connection basis in the receive LCD using the numHeadbytes and useCrcNumHead fields. When the useCrcNumHead field is set to '0', the numHeadbytes field provides a fixed number of bytes that is used as the number of header bytes. When useCrcNumHead field is set to '1', then the RXCRC nano code will calculate the number of header bytes using the frameType field to index an IP procedure. Currently, RXCRC will only set the number of header bytes for recognized TCP/IP headers. Other headers can be recognized. Contact IBM technical support to discuss requirements. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 327 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.1: REASM Logical Channel Descriptor Base Register The REASM Logical Channel Descriptor Base Register indicates the starting address of the logical channel descriptor table. This register defines where the Logical Channel Descriptors are located. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1618 X'00008000' The value must be in the range of the physical memory allocated for Control Memory. LCD Table Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description This register defines where the Logical Channel Descriptors are located. 9 8 7 6 5 4 3 2 1 0 Cell/Packet Re-assembly (REASM) Page 328 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.2: REASM Mode Register Used to set REASM and sub-entity modes. This register contains the mode bits that specify how REASM is to operate. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1610 and 614 X'00000000' None Enable TCP/IP Checksums 1 Disable Counter Overflow Reset Receive Logic RXRTO Free Buffer RXAAL RXCRC RXXLT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-28 27-24 23-8 7-5 4 3 2 1 0 Description 9 8 7 6 5 4 3 2 RXAAL code specific mode bits. If used, documented in code load documentation. RXCRC code specific mode bits. If used, documented in code load documentation. RXXLT code specific mode bits. If used, documented in code load documentation. Each nibble is for a port. Bits 23-20 are RXXLT mode bits 3-0 for port 3, bits 19-16 are RXXLT mode bits 3-0 for port 2, bits 15-12 are for port 1, and bits 11-8 are for port 0. Reserved. Reset receive logic. Disable counter overflow events. RXRTO free buffer option. When set, a buffer that times out is freed and the event will contain the LCD address instead. Enable TCP/IP checksums. When set, TCP/IP checksum verification is enabled. When enabled, the receive LCD data structure includes the IP state. Diagnostic mode. When set, REASM is placed in diagnostic mode. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 329 of 676 Diagnostic 0 Reserved IBM3206K0424 IBM Processor for Network Resources Preliminary 12.3: REASM Reassembly Modes Register Used to set reassembly modes. This register contains the mode bits that specify different reassembly modes. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1630-34 X'00000000' None Specifies Congestion Bit Source Enable OAM Cell Discrimination Disable AAL5 Length Checking Disable AAL5 CRC Checking 1 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-13 12 Reserved Enable new RM events Name Reserved 9 8 7 6 5 4 3 2 Description When set, the new RM cell events are enabled, and the ABR event routing register is ignored. This allows separate events for forward and backward RM cells, but routes the events to the general OAM cell receive queue. When set, the OAM processing is enabled for ports 0-3. When cleared, OAM cells are NOT discriminated. Reserved Specify which congestion bit source to use if doing routing. Values are: 00 Use value from LCD routed LCD ptr field 01 Use ORed congestion value (or last in case of cell) 10 Use value from last cell Specify which CLP source to use if doing routing. Values are: 00 Use value from LCD routed LCD ptr field 01 Use ORed CLP value (or last in case of cell) 10 Use value from last cell. 11-8 7 Enable OAM cell discrimination Reserved 6-5 4-3 2 1 0 Disable AAL5 length checking Disable AAL5 CRC checking Disable AAL5 CPI checking When set, the AAL5 trailer length field is not checked. When set, the AAL5 trailer CRC is not checked. When set, the AAL5 trailer CPI bytes are not checked against zero. Cell/Packet Re-assembly (REASM) Page 330 of 676 pnr25.chapt05.01 August 14, 2000 Disable AAL5 CPI Checking 0 Enable New RM Events Specifies Chip Source Reserved IBM3206K0424 Preliminary IBM Processor for Network Resources 12.4: REASM Status Register Used to surface REASM and sub-entity status. This register contains the status bits for the REASM sub-entities. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions RXQUE Dequeue State Mach. Locked RXBUF Cell Buffer Thrshd Exceeded 32 bits Read/Write XXXX 1600 and 604 X'00000000' None Bad LCD Receive Offset Detected Bad LCD Update Operation RXXLT drop 3 nano status RXXLT drop 2 nano status RXXLT drop 1 nano status Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-28 27 Reserved. Description 9 8 7 6 5 4 3 2 RXXLT drop 0 nano status 1 0 RXBUF cell buffer threshold exceeded. This bit is set when the number of receive cell buffers exceeds the threshold set in RXBUF Receive Buffer Threshold. This bit is sticky and must be reset by software after being set. Bad LCD receive offset detected. This bit is set when a receive LCD is used that does not have a good receive offset. Either the receive offset does not allow for enough room for the configured packet header, or there is not enough room for the DMA list entry that would have been written. RXQUE deque state machine is locked. This bit is set when an RXQUE deque operation is attempted in order to get a piece of user data for the DMA list and there is no data available. When using two pieces of data in a DMA list entry, both must be available. Bad LCD update operation. This bit is set when a receive LCD update was attempted on an offset that falls in the transmit portion of the LCD, or when an LCD that is out of range is updated. RXAAL nano status. These bits can be set from the RXAAL nano code. If they are used, they are documented in the code load instructions (that is, aal.txt). They may or may not be used. RXCRC nano status. These bits can be set from the RXCRC nano code. If they are used, they are documented in the code load instructions (that is, crc.txt). They may or may not be used. RXXLT drop 3 nano status. These bits can be set from the RXXLT nano code for drop 3. If they are used, they are documented in the code load instructions (that is, atm.txt). They may or may not be used. RXXLT drop 2 nano status. These bits can be set from the RXXLT nano code for drop 2. If they are used, they are documented in the code load instructions (that is, atm.txt). They may or may not be used. RXXLT drop 1 nano status. These bits can be set from the RXXLT nano code for drop 1. If they are used, they are documented in the code load instructions (that is, atm.txt). They may or may not be used. RXXLT drop 0 nano status. These bits can be set from the RXXLT nano code for drop 0. If they are used, they are documented in the code load instructions (that is, atm.txt). They may or may not be used. Cell/Packet Re-assembly (REASM) 26 25 24 23-20 19-16 15-12 11-8 7-4 3-0 pnr25.chapt05.01 August 14, 2000 RXCRC nano status RXAAL nano status Page 331 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.5: REASM Interrupt Enable Register Used to enable interrupts for REASM status conditions. When set, the corresponding status condition generates an interrupt from REASM to INTST. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1608 and 60C X'00000000' None Status Interupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Description See the bitwise descriptions for the REASM Status Register on page 331. 9 8 7 6 5 4 3 2 1 0 12.6: REASM DEBUG State Selector Register Selects which entity states are surfaced. This register specifies which entity states are surfaced. Use this register only under the advice of IBM technical support. Length Type Address Power On Value Restrictions 2 x 32 bits Read/Write XXXX 1620-24 X'00000000' None Cell/Packet Re-assembly (REASM) Page 332 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXBUF Block Diagram Read Interface to RXXLT Read Interface to Sub-Entities Done RXBUF 16 Entry Cell Info 16 64-byte Cell Buffers clst(16-0) ovrs rest Asynchronous Boundary with LINKR wrtic sop eop err portId(4-0) cfgId(1-0) cellLen(6-0) addr(6-3) clps addr(6-0) data963-0) wrtc clst(16-0) ovrs RXBUF Functional Description RXBUF provides the cell/packet buffering mechanism between LINKR and the rest of REASM. The buffering provides enough storage for 16 64-byte cells and the associated control information for each cell buffer. LINKR writes the cell/packet data and control information into the buffers. The buffering mechanism is then exposed to the remainder of the REASM sub-entities for reading. The cell buffers are sequenced through in sequential order regardless of which port received cells arrive on. Thus, a total of 16 cells of buffering exists and is used as a shared 16-cell FIFO. 12.7: RXBUF Cell Data Buffer Address Provides the read/write address for accessing cell data buffer. This register provides the read/write address for accessing cell data buffer. When RXBUF Cell Data Buffer Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written, the address rolls over to zero. Length Type Address Power On Value Restrictions 11 bits Read/Write XXXX 1640 X'00000000' Low two bits are always zero pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 333 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.8: RXBUF Cell Data Buffer Read/Write Port Provides read/write access to receive cell data buffer. The array is divided into 16 64-byte buffers used to buffer/assemble cells received from the line. When this register is read/written, the address provided by RXBUF Cell Data Buffer Address is used to select the array word to be accessed. RXBUF Cell Data Buffer Address is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 256 words x 32 bits Read/Write XXXX 1648 X'00000000' The array can only be accessed in diagnostic mode. If not in diagnostic mode, zero is returned on reads and writes are silently ignored. 12.9: RXBUF Cell Info Buffer Address Provides the read/write address for accessing cell information buffer. This register provides the read/write address for accessing cell information buffer. When RXBUF Cell Info Buffer Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written the address rolls over to zero. Length Type Address Power On Value Restrictions 6 bits Read/Write XXXX 1644 X'00000000' Low two bits are always zero 12.10: RXBUF Cell Info Buffer Read/Write Port Provides read/write access to the Receive Cell Info buffer. The array is divided into 16 areas used to provide information about each received cell from LINKR. When this register is read/written, the address provided by RXBUF Cell Info Buffer Address is used to select the array word to be accessed. RXBUF Cell Info Buffer Address is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 16 words x 32 bits Read/Write XXXX 1650 X'00000000' The array can only be accessed in diagnostic mode. If not in diagnostic mode, zero is returned on reads and writes are silently ignored. Cell/Packet Re-assembly (REASM) Page 334 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.11: RXBUF Receive Buffer Threshold Provides a method to monitor number of cell buffers in use. The value of this register is used to compare against the number of active cell buffers. When this threshold is exceeded, the status is raised in the REASM status register. Length Type Address Power On Value Restrictions 5 bits Read/Write XXXX 1660 X'00000000' None pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 335 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary RXXLT Block Diagram POOLS Get Interface CM Read Interface RXLCD Interface RXXLT XLATE Nano Processor LCD Translation Cache RXCRC Interface RXBUF Interface RXXLT Functional Description RXXLT is the first stage in the cell processing pipeline. RXXLT provides general LCD translation facilities and link level statistics. These are provided via a nano-processor and nano-programs. Up to four unique drops/ports can be supported, each with a unique configuration. Each port is able to run a unique nano-program to do LCD address translation. For example, one port may be a packet-based PHY using 64-byte segments with PPP LCD translation, and another port may be an ATM cell based PHY. The drop/config number (0-3) along with the port id is passed to RXXLT from RXBUF/LINKR. The drop number (0-3) is used to specify which nano-program is executed by RXXLT to translate cell/packet information into an LCD address. This is different from previous versions of the processor which had a fixed LCD translation mechanism. RXXLT instruction formats are not defined here and are IBM Confidential. RXXLT uses the resulting LCD address to load the LCD cache for the next stage of the pipeline. The LCD address and cell buffer address are passed to RXCRC upon completion of processing. There are a number of degrees of freedom in the LCD translation. Generally, the nano program performs the following steps: * * * * * Gather some bytes from the cell buffer Do some error checking and default LCD checking Select and shift appropriate bits to form an LCD translate table index Read the LCD translate table to get an LCD index Generate the LCD address from the LCD index and the LCD base address There are eight general purpose registers per PHY drop and four drops. These eight registers contain values that the nano-code uses, and are available on a per port basis. For example, the LCD translate table addresses would reside in these registers (this is different from previous versions of the processor where these registers were at fixed addresses). Other items that might reside in these registers are default/error LCD addresses, compare values, and masks. Because these are general purpose registers, multiple LCD tables or multiple default LCDs can be specified. One quarter of the total registers are available to each port, so there can be an LCD translate table (etc.) for each port. The total LCD translate tables and LCD table sizes are only limited in size by the amount of memory that is available to the IBM3206K0424. The LCD indexes are limited to 16 bits, and LCD addresses are always 128-byte aligned. The LCD translation code must execute in one cell time in order to run at full bandwidth. The only variable portion of the code execution time is the reads to IBM3206K0424 memory when reading the LCD translation Cell/Packet Re-assembly (REASM) Page 336 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources table. Thus, while a double lookup is possible, it may not meet the time constraints of running at full bandwidth. The following pseudo code shows some of the types of LCD translations that are possible using the nano-processor. Note: The following do not imply types/numbers of instructions needed, but the different variable names imply different general purpose registers are being used, so variables are specified on a per port basis. In the following code there are shift, mask, and compare values that are not specified. These are values that would be customizable at run time. These will be customized via the general purpose registers. The following code uses nomenclature that matches the IBM3206K0424 (zero-based big endian). So bit(1) in a comm spec might be bit(0) in the following code. The comments use spec nomenclature so you can match the two up. Standard ATM atmH = read 4 bytes from rxbuf at offset 0 -- read the atm header from cell if non_user_data { lcdAddr = defaultLcd return } -- non-user data as specified in pti -- field is handled by the deafult lcd tblIndex = (atmH and vciMask) >> 4 tblIndex |= ((atmH and vpiMask) >> X) if non-masked bits on { out of range counter++ if mode(X) { flush cell } else { lcdAddr = errorLcdAddr } return } if tblIndex == 0 { zero id counter++ if mode(X) { flush cell } else { lcdAddr = errorLcdAddr } return } -- gather pertinent vci bits -- gather pertinent vpi bits -- X depends on num of vci bits used -- check for out of range -- update counter -- if configured to flush out of -- range cells flush and we are done -- check for zero id -- update counter -- if configured to flush zero id -- cells flush and we are done lcdIndex = Lookup(lcdTable, tblIndex) lcdAddr = lcdBase + lcdIndex*128 -- read index from cm using tableIndex -- calc lcd addr from index pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 337 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary PPP label = read 4 bytes from rxbuf at offset 0 -- read the ??? if label == 0xff030021 { -- what is this field called?? read 1 bytes from rxbuf at offset 4 -- read the ip header version (5th byte) if IPVER_HEADERLGT == 0x45 { tblIndex = read byte from offset 5 -- read QOS field (6th byte) lcdIndex = Lookup(lcdTable, tblIndex) -- read index from cm using tableIndex lcdAddr = lcdBase + lcdIndex*128 -- calc lcd addr from index } else { lcdAddr = defaultPortLcd -- use port default lcd } } else { lcdAddr = defaultPortLcd -- use port default lcd } Q.922 2 Byte Addressing head = read 2 bytes from rxbuf at offset 0 -- read the header (network bytes 0-1) if (bit(0) == 1) && (bit(8) == 0) { -- EA bits indicate two byte addr -- byte 0 bit 1 == 0 && byte 1 bit 1 == 1 tblIndex = (head and dlciMask0) >> X -- gather 6 of 10 dlci bits from byte 0 tblIndex |= ((head and dlciMask1) >> X) -- gather 4 of 10 dlci bits from byte 1 lcdIndex = Lookup(lcdTable, tblIndex) -- read index from cm using tableIndex lcdAddr = lcdBase + lcdIndex*128 -- calc lcd addr from index } else { lcdAddr = errorLcdAddr -- not a two byte addr } Q.922 4 Byte Addressing head = read 4 bytes from rxbuf at offset 0 -- read the header (network bytes 0-3) if (bit(0) == 1) && (bit(8) == 0) && -- EA bits indicate four byte addr (bit(16) == 0) && (bit(24) == 0) { -- byte 0 bit 1 == 0 && byte 1 bit 1 == 0 && -- byte 2 bit 1 == 0 && byte 3 bit 1 == 1 if dcBit == 1 { -- check for dc bit being set lcdAddr = defaultPortLcd -- and surface on default port lcd } else { -- gather 16 least significant dlci bits tblIndex = (head and dlciMask1) >> X -- gather 3 dlci bits from byte 1 tblIndex |= ((head and dlciMask2) >> X) -- gather 7 dlci bits from byte 2 tblIndex |= ((head and dlciMask3) >> X) -- gather 6 dlci bits from byte 3 lcdIndex = Lookup(lcdTable, tblIndex) -- read index from cm using tableIndex lcdAddr = lcdBase + lcdIndex*128 -- calc lcd addr from index } } else { lcdAddr = errorLcdAddr -- not a four byte addr } Cell/Packet Re-assembly (REASM) Page 338 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources FUNI 2.0 2 Byte Addressing head = read 2 bytes from rxbuf at offset 0 -- read the header (network bytes 0-1) if (bit(0) == 1) && (bit(8) == 0) { -- EA bits indicate two byte addr -- byte 0 bit 1 == 0 && byte 1 bit 1 == 1 if (bit(2) == 0) && (bit(9) == 0) { -- FID1 & FID2 == 0 (byte 0 bit 2 & byte 1 bit 3) tblIndex = (head and faMask1) >> X -- gather 6 of 10 FA bits from byte 0 tblIndex |= ((head and faMask0) >> X) -- gather 4 of 10 FA bits from byte 1 lcdIndex = Lookup(lcdTable, tblIndex) -- read index from cm using tableIndex lcdAddr = lcdBase + lcdIndex*128 -- calc lcd addr from index } else { lcdAddr = defaultPortLcd -- otherwise surface on port default lcd } } else { lcdAddr = errorLcdAddr -- not a two byte addr } FUNI 2.0 4 Byte Addressing head = read 4 bytes from rxbuf at offset 0 -- read the header (network bytes 0-3) if (bit(0) == 1) && (bit(8) == 0) && -- EA bits indicate four byte addr (bit(16) == 0) && (bit(24) == 0) { -- byte 0 bit 1 == 0 && byte 1 bit 1 == 0 && -- byte 2 bit 1 == 0 && byte 3 bit 1 == 1 if (bit(18) == 0) && (bit(25) == 0) { -- FID1 & FID2 == 0 (byte 0 bit 2 & byte 1 bit 3) -- gather 16 vpi/vci bits tblIndex = (head and vciMask0) >> 1 -- gather X vci bits from byte 3 tblIndex = (head and vciMask1) >> X -- gather X vci bits from byte 2 tblIndex = (head and vciMask2) >> X -- gather X vci/vpi bits from byte 1 tblIndex = (head and vpiMask3) >> X -- gather X vpi bits from byte 0 lcdIndex = Lookup(lcdTable, tblIndex) -- read index from cm using tableIndex lcdAddr = lcdBase + lcdIndex*128 -- calc lcd addr from index } else { lcdAddr = defaultPortLcd -- otherwise surface on port default lcd } } else { lcdAddr = errorLcdAddr -- not a four byte addr } pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 339 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.12: RXXLT Register Array Address Port Provides the read/write address for accessing register array. This register provides the read/write address for accessing register array. When RXXLT Register Array Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written the address rolls over to zero. Length Type Address Power On Value Restrictions 7 bits Read/Write XXXX 1680 X'00000000' Low two bits are always zero 12.13: RXXLT Register Array Read/Write Port Provides read/write access to the register array. The array is divided into four groups of eight registers. Each group is associated with a receive port (0-3). So each nano-program has eight registers to use. These registers have intended uses and also serve as the link level counters, so they are not general purpose registers. When this register is read/written, the address provided by RXXLT Register Array Address Port is used to select the array word to be accessed. RXXLT Register Array Address Port is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 32 words x 32 bits Read/Write XXXX 1688 X'00000000' None Cell/Packet Re-assembly (REASM) Page 340 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.14: RXXLT Processor State Selector Allows user to select which data should be accessed with RXXLT Processor State Read/Write Port. This register provides the encoded selector for accessing internal processor registers and state via reads/writes to the RXXLT Processor State Read/Write Port. Length Type Address Power On Value Restrictions 4 bits Read/Write XXXX 1698 X'00000000' None Bit(s) Description The following are the meanings of the encoded values: 0000 Accumulator register 0001 Header register 0010 LCD index register 0011 Reserved 0100 Reserved 0101 Flags 0110 Reserved 1111 Instruction ptr 3-0 12.15: RXXLT Processor State Read/Write Port Provides read/write access to the internal state of the processor. The internal processor state is externalized for debug and testing reasons. See the description of RXXLT Processor State Selector for definitions on the addresses. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 169C X'00000000' Processor state can only be set in diagnostic mode. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 341 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.16: RXXLT Instruction Array Address Port This register provides the read/write address for accessing the instruction array. When RXXLT Instruction Array Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written, the address rolls over to zero. Length Type Address Power On Value Restrictions 9 bits Read/Write XXXX 1684 X'00000000' Low two bits are always zero 12.17: RXXLT Instruction Array Read/Write Port Provides read/write access to the instruction array. The instruction array is divided into four groups of 32 entries. Each group is associated with a receive port (0-3) so a nano-program can be loaded for each active port. When this register is read/written, the address provided by RXXLT Instruction Array Address Port is used to select the array word to be accessed. RXXLT Instruction Array Address Port is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 128 words x 19 bits Read/Write XXXX 1690 X'00000000' None, but the instruction stream of an active nano-program should not be written Cell/Packet Re-assembly (REASM) Page 342 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.18: RXXLT Last LCD Index Register These registers provide the previous LCD index that was used for the corresponding port. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 16a0-ac X'0000' Can only be written in diagnostic mode pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 343 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary RXCRC Block Diagram RXLCD Interface RXCRC RXXLT Interface CRC-32 Generation Logic CRC-10 Generation Logic RXCRC Interface RXBUF Interface RXCRC Functional Description RXCRC is the second stage in the cell processing pipeline. It performs the ATM CRC-32 (Ethernet FCS) and ATM CRC-10 functions if necessary. RXCRC gets LCD type, state, and seed information from the LCD cache, and updates the cache on completion. The results are passed to RXAAL upon completion, along with the LCD address. 12.19: RXCRC Instruction Array Address Port This register provides the read/write address for accessing the instruction array. When RXCRC Instruction Array Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written, the address rolls over to zero. Length Type Address Power On Value Restrictions 10 bits Read/Write XXXX 16C4 X'00000000' Low two bits are always zero Cell/Packet Re-assembly (REASM) Page 344 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.20: RXCRC Instruction Array Read/Write Port Provides read/write access to the instruction array. The instruction array contains a single nano-program. When this register is read/written, the address provided by RXCRC Instruction Array Address Port is used to select the array word to be accessed. RXCRC Instruction Array Address Port is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 256 words x 19 bits Read/Write XXXX 16D0 X'00000000' None, but the instruction stream of an active nano-program should not be written 12.21: RXCRC Processor State Selector Allows user to select which data should be accessed with RXCRC Processor State Read/Write Port. This register provides the encoded selector for accessing internal processor registers and state via reads/writes to the RXCRC Processor State Read/Write Port. Length Type Address Power On Value Restrictions 3 bits Read/Write XXXX 16D8 X'00000000' None Bit(s) Description The following are the meanings of the encoded values: 000 Accumulator register 001 Header register 010 Reserved 011 Reserved 100 Reserved 101 Flags 110 Reserved 111 Instruction ptr 2-0 pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 345 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.22: RXCRC Processor State Read/Write Port Provides read/write access to the internal state of the processor. The internal processor state is externalized for debug and testing reasons. See the description of RXCRC Processor State Selector on page 345 for definitions on the addresses. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 16Dc X'00000000' Processor state can only be set in diagnostic mode 12.23: RXCRC Last LCD Index Register These registers provide the previous LCD index that was used for the corresponding port. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 16E0 X'0000' Can only be written in diagnostic mode 12.24: RXCRC Checksum Protocol Registers These registers provide additional protocol bytes for which checksum calculations should be enabled. The first register allows up to four protocols to be enabled with headers that are similar to UDP and TCP which use a pseudo-header. The second register allows up to four protocols to be enabled with headers that are similar to ICMP (no pseudo header). IP, UDP, TCP, V4 ICMP, and V6 ICMP are automatically recognized and should not be specified again in these registers. Each byte specifies a different protocol. Length Type Address Power On Value Restrictions 2x32 bits Read/Write Checksum Type: With header XXXX 16E4 Checksum Type: With no header XXXX 16E8 X'00000000' None Cell/Packet Re-assembly (REASM) Page 346 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXAAL Functional Description The following is a block diagram of RXAAL: RXAAL Block Diagram PM Write Interface RXLCD Interface RXAAL RXCRC Interface AAL Nano Processor RXQUE Interface DMAQS Interface RXBUF Interface RXAAL performs the cell and packet reassembly functions. This includes the AAL processing and moving cell data and packet headers to Packet Memory. The nano-program uses state and configuration informations from the LCD cache to perform the necessary function for each cell. The nano-processor is capable of executing programs to run the following types of reassembly: * AAL5 * AAL3/4 * Raw cells * Non-user data (this might be the same as raw) * Packets * MPEG FIFO Mode RXAAL also performs the cell/packet post processing step. This includes event generation to RXQUE, cut through processing, scatter processing, and DMA enqueues. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 347 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.25: RXAAL Instruction Array Address Port This register provides the read/write address for accessing the instruction array. When RXAAL Instruction Array Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written, the address rolls over to zero. Length Type Address Power On Value Restrictions 11 bits Read/Write XXXX 1704 X'00000000' Low two bits are always zero 12.26: RXAAL Instruction Array Read/Write Port Provides read/write access to the instruction array. The instruction array contains a single nano-program. When this register is read/written, the address provided by RXAAL Instruction Array Address Port is used to select the array word to be accessed. RXAAL Instruction Array Address Port is auto-incremented on each read/write. Thus, this port can be read/written multiple times to read/write the entire array. Length Type Address Power On Value Restrictions 512 words x 24 bits Read/Write XXXX 1710 X'00000000' None, but the instruction stream of an active nano-program should not be written Cell/Packet Re-assembly (REASM) Page 348 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.27: RXAAL Processor State Selector Allows user to select which data should be accessed with RXAAL Processor State Read/Write Port. This register provides the encoded selector for accessing internal processor registers and state via reads/writes to the RXAAL Processor State Read/Write Port. Length Type Address Power On Value Restrictions 3 bits Read/Write XXXX 1718 X'00000000' None Bit(s) Description The following are the meanings of the encoded values: 000 Accumulator register 001 Header register 010 Reserved 011 Reserved 100 Reserved 101 Flags 110 Reserved 111 Instruction ptr 2-0 12.28: RXAAL Processor State Read/Write Port Provides read/write access to the internal state of the processor. The internal processor state is externalized for debug and testing reasons. See the description of RXAAL Processor State Selector on page 349 for definitions on the addresses. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 171C X'00000000' Processor state can only be set in diagnostic mode. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 349 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.29: RXAAL Last LCD Index Register This register provides the previous LCD index that was used. Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 1720 X'0000' None Cell/Packet Re-assembly (REASM) Page 350 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.30: RXAAL Transmit Queue Length Compression Configuration This register allows the user to configure how the transmit queue lengths should be compressed for use in the receive packet header. CSKED provides twelve transmit queue lengths specified in bytes. A 32-bit register (the Bytes Queued Counters in CSKED) is available for the high, medium, and low priority queues for each of the four PHY ports. Using the full counts in the receive packet header generally uses too much room. This register allows the user to configure how this information should be compressed for use in the receive packet header. Length Type Address Power On Value Restrictions 4 bits Read/Write XXXX 1730 X'00000000' None Bit(s) Description The following are the options: 0000 Use the full register representation for port zero only (3 - 32 bit words) 0001 Use the 2K scaled representation for port zero only (1 - 32 bit words) 0010 Use the 4K scaled representation for port zero only (1 - 32 bit words) 0011 Use the 8K scaled representation for port zero only (1 - 32 bit words) 0100 Use the 16K scaled representation for port zero only (1 - 32 bit words) 0101 Use the 32K scaled representation for port zero only (1 - 32 bit words) 0110 Use the 64K scaled representation for port zero only (1 - 32 bit words) 0111 Use the 128K scaled representation for port zero only (1 - 32 bit words) 1000 Reserved 1001 Use the 2K scaled representation for all ports (3 - 32 bit words) 1010 Use the 4K scaled representation for all ports (3 - 32 bit words) 1011 Use the 8K scaled representation for all ports (3 - 32 bit words) 1100 Use the 16K scaled representation for all ports (3 - 32 bit words) 1101 Use the 32K scaled representation for all ports (3 - 32 bit words) 1110 Use the 64K scaled representation for all ports (3 - 32 bit words) 1111 Use the 128K scaled representation for all ports. (3 - 32 bit words) For example, using option "0001," a single 32-bit word is used. The most significant byte contains the transmit queue length for the high priority queue for port zero divided by 2K bytes. If the scaled count overflows (greater than 2K*0xff), a value of 0xff is used. The next byte contains the scaled count for the medium priority queue, and the third byte contains the scaled count for the low priority queue. The least significant byte is not used. Using option "1010" three 32-bit words are used. The first word contains the scaled counts for the high priority queue. The second word contains the scaled counts for the medium priority queue. The third word contains the scaled counts for the low priority queue. Within each word, the first byte contains the scaled count for port zero, and the subsequent bytes are used for the other ports (1, 2, 3). The counts are divided by 4K in this case. 3-0 pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 351 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.31: RXAAL Packet Header Configuration Allows user to configure the contents of each optional packet header word, and specify how many optional packet words are used. This register configures the contents of each optional packet header word in the optional portion of the packet header. There are four possible configurations, and the configuration used is selected with the packHeadSel field in the receive LCD. The first three words of the packet header are fixed, and up to seven additional words can be configured. The low nibble of this register specifies how many optional packet header words are used, and the remaining nibbles of the register configure each packet header word if used. Note: The base receive and transmit packet headers must be compatible if internal cell or packet routing is being used. The receive packet header becomes the transmit packet header in this scenario. User 0 and user 1 values can be used to place non-standard values in the packet header. These values are built by the nano-code, and are then placed in the packet header. In order to use these values, the nano-code must be customized. Do this only under the advisement of IBM technical support. Length Type Address 32 bits Read/Write Config 0 Config 1 Config 2 Config 3 X'00000000' None Configure Packet Header Word 4 Configure Packet Header Word 5 Configure Packet Header Word 6 Configure Packet Header Word 7 Configure Packet Header Word 8 Configure Packet Header Word 9 XXXX 1740 XXXX 1744 XXXX 1748 XXXX 174C Power On Value Restrictions Configure Packet Header Word 3 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-28 27-24 23-20 19-16 15-12 Configure packet header word 3 Configure packet header word 4 Configure packet header word 5 Configure packet header word 6 Configure packet header word 7 Description 9 8 7 6 5 4 3 2 Optional Packet Header Words 1 0 Cell/Packet Re-assembly (REASM) Page 352 of 676 pnr25.chapt05.01 August 14, 2000 Reserved IBM3206K0424 Preliminary Bit(s) 11-8 7-4 3 Configure packet header word 8 Configure packet header word 9 Reserved Specifies how many optional packet header words to use. Each nibble specifies what should be selected for the corresponding packet header word. The following are the options: 0000 Start Timestamp 0001 End Timestamp 0010 ATM Header 2 0011 Host data 0100 VBA - Virtual buffer address 0101 Transmit queue length word 0 0110 Transmit queue length word 1 0111 Transmit queue length word 2 1000 User 0 1001 User 1 1010 AAL5 trailer, two user bytes and the length 1011 VBA with the number of header bytes in the low 10 bits 1100 Reserved Description IBM Processor for Network Resources 2-0 12.32: RXAAL Error Count Register Maintains a count of detected errors. This register maintains a count of error conditions that are detected. For example, CRC errors and other protocol types of errors are counted. This count is useful when the chip is configured to only surface good packets. When this counter overflows, a counter overflow event is generated to RXQUE. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1734 X'00000000' None pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 353 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.33: RXAAL Dropped Count Register This register maintains a count of packets that are dropped due to a lack of resource. For example, if no POOLS buffer (real or virtual mode) is available, the packet is dropped and this counter is incremented. This count is useful when the chip is configured to only surface good packets. When this counter overflows, a counter overflow event is generated to RXQUE. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1738 X'00000000' None 12.34: RXAAL Maximum SDU Length Register Specifies the maximum SDU size for a packet. This register contains the maximum SDU size for a packet. This size includes only the protocol data length of the packet. For example, this length would be compared with the AAL5 length field in the AAL5 trailer. When a packet is completely received, this register is used to make sure it does not exceed the MSDU specified. Length Type Address Power On Value Restrictions 18 bits Read/Write XXXX 173C X'0000FFFF' None 12.35: RXAAL OAM LCD Information Register This register specifies the reassembly information for OAM cells. The format of this register is equivalent to word zero of the receive LCD. The following fields are valid: ppMode, size, storeCrc10, rxqNum, rxPoolId, rxOffset, and cutThruSel. Refer to the format of LCD word zero for the Raw receive LCDs. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 172C X'0000FFFF' None Cell/Packet Re-assembly (REASM) Page 354 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.36: RXALL - Scatter/Cut Through Info Registers These registers specify the scatter/cut through configurations. A configuration is selected in the LCD via the cut through selector field when doing cut through/scatter mode. A configuration consists of three registers. The first two registers, described here, define the four possible configurations for scatter/cut through. The third register, RXALL - Scatter/Cut Through Flag Registers, is described in "RXALL - Scatter/Cut Through Flag Registers. The first register, one of cti(0-3), is defined as follows: 12.36.1: Scatter/Cut Through Info Register 1 Length Type Address 32 bits Read/Write Config 0 Config 1 Config 2 Config 3 Config 4 Config 5 Config 6 Config 7 XXXX 1750 XXXX 1754 XXXX 1758 XXXX 175C XXXX 1770 XXXX 1774 XXXX 1778 XXXX 177C Power On Value Restrictions Enable Optional Header Addresses X'00000000' None Optional Header Page Size Enable Header Addresses Enable Split Header Mode Enable Single Page Mode Enable Page Addresses RXQUE to deq Optional RXQUE to deq Header RXQUE to deq Page Enable Double deq Header Page Size Vent Source 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 Enable single page mode Enable double deq for packet header buffers to get virtual addresses Enable header addresses vs. descriptor (1->addresses 0->descriptor) Enable optional header addresses vs. descriptor (1->addresses 0->descriptor) Description 9 8 7 6 5 4 3 2 Page Size 1 0 pnr25.chapt05.01 August 14, 2000 DMAQS Cell/Packet Re-assembly (REASM) Page 355 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Description Event source: Specify how the event data (if any) is formed. Normally, the DMA descriptor is used for DMA events, but when the entire DMA descriptor is built there is no descriptor address to use. The following sources are possible: 00 Use DMA descriptor address (DMA queue address where built) 01 Use source address 10 Use destination address DMAQS DMA queue to enqueue DMA descriptor to RXQUE to deq header DMA descriptor addresses from Header page size: Specifies the page size of the buffer that the header is DMAed into. The following encodings are used: 0 128 bytes 1 256 bytes 2 512 bytes 3 1K bytes 4 2K bytes 5 4K bytes 6 8K bytes 7 6K bytes 8 32K bytes 9 64K bytes RXQUE to deq optional header DMA descriptor addresses from Enable Split Header Mode (optional header buffer) Optional header page size: Specifies the page size of the buffer that the header is DMAed into. The following encodings are used: 0 64 bytes 1 128 bytes 2 256 bytes 3 512 bytes 4 1K bytes 5 2K bytes 6 4K bytes 7 8K bytes RXQUE to deq page DMA descriptor addresses from Enable page addresses vs. page descriptor Page size: Specifies the page size of the page buffers that the scatter pages are DMAed into. The following encodings are used: 0 512 bytes 1 1K bytes 2 2K bytes 3 4K bytes 4 8K bytes 5 16K bytes 6 32K bytes 7 64K bytes Preliminary 27-26 25-24 23-20 19-16 15-12 11 10-8 7-4 3 2-0 Cell/Packet Re-assembly (REASM) Page 356 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.36.2: Scatter/Cut Through Info Register 2 Length Type Address 32 bits Read/Write Config 0 Config 1 Config 2 Config 3 Config 4 Config 5 Config 6 Config 7 XXXX 1750 XXXX 1754 XXXX 1758 XXXX 175C XXXX 1770 XXXX 1774 XXXX 1778 XXXX 177C Power On Value Restrictions X'00000000' None Enable Double deq for opTional Header Enable Double deq for pAge Buffers Reserved Enable Header only DMA Optional Header Packet Header Page deq Size Optional Header Flags 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-22 21 20 19 18 17 16 15-0 Reserved. Packet Header deq size: 0 = 32 bit, 1 = 64 bit Optional Header deq size: 0 = 32 bit, 1 = 64 bit Page deq size: 0 = 32 bit, 1 = 64 bit Enable double deq for optional header buffers to get virtual addresses Enable double deq for page buffers to get virtual addresses Description 9 8 7 6 5 4 3 2 1 0 Enable header only DMA. When set, only the header bytes as specified in the LCD or from RXCRC will be DMAed along with the DMA list and packet header Optional Header Flags. These flags are used when DMAing the optional header page. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 357 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.37: RXALL - Scatter/Cut Through Flag Registers Use to specify the scatter/cut through flags. These registers specify the scatter/cut through flags. A flag register is selected in the LCD via the cut through selector field when doing cut through/scatter mode. The flags are used when building DMA descriptors for scatter pages and the first scatter buffer (packet header, DMA list, etc.). Length Type Address 32 bits Read/Write Config 0 Config 1 Config 2 Config 3 XXXX 1760 XXXX 1764 XXXX 1768 XXXX 176C Power On Value Restrictions X'00000000' None Header Flags Page Flags 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-0 Name Header Flags Page Flags Description 9 8 7 6 5 4 3 2 1 0 These flags are used when DMAing the packet header, DMA list, and header bytes from the packet. These flags are used when DMAing a scatter page (other than the header page). Cell/Packet Re-assembly (REASM) Page 358 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXLCD Block Diagram CM Read/Write Interface RXLCD LCD Cache RXXLT Interface RXCRC Interface RXAAL Interface RXRTO Interface RXLCD Functional Description RXLCD provides an LCD cache for REASM sub-entities. This cache holds the last four receive LCDs. The sub-entities can request to load an LCD, read the LCD words, and update parts of the LCD. 12.38: RXLCD Cache Data Array Address Port This register provides the read/write address for accessing the LCD cache data array. When the RXLCD Cache Data Array Read/Write Port is read/written, this register is auto-incremented. When the last address is read/written, the address rolls over to zero. The cache is organized as 64 32-bit words. Each 16 words comprises an LCD. The first four words and the last word of each LCD do not contain valid data and can not be written. These locations return zero on reads. Length Type Address Power On Value Restrictions 6 bits Read/Write XXXX 1780 X'00000000' The low two bits are always zero pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 359 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.39: RXLCD Cache Data Array Read/Write Port Provides read/write access to the LCD cache data array. When this register is read/written, the address provided by RXLCD Cache Data Array Address Port is used to select the array word to be accessed. RXLCD Cache Data Array Address Port is auto-incremented on each read/write so this port can be read/written multiple times to read/write the entire array. The cache is organized as 64 32-bit words. Each 16 words comprises an LCD. The first four words and the last word of each LCD do not contain valid data and can not be written. These locations return zero on reads. Length Type Address Power On Value Restrictions 64 words x 32 bits Read/Write XXXX 1788 X'00000000' Must be in diagnostic mode to read/write the cache 12.40: RXLCD Cache Line Info Registers These registers provide the cache line tags, valid, and dirty bits. There is a register for each of the four cache lines. Length Type Address Power On Value Restrictions 4 x 32 bits Read/Write XXXX 17a0-7ac X'00000000' Must be in diagnostic mode to write these registers Reserved Valid Dirty LRU LCD Index 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30-20 19-17 16 15-0 Valid Dirty bits LRU bits Reserved LCD index Description 9 8 7 6 5 4 3 2 1 0 Cell/Packet Re-assembly (REASM) Page 360 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.41: RXLCD Mode Register This register provides a means to control cache operation. Length Type Address Power On Value Restrictions 1 bit Read/Write XXXX 17b8-7bc X'00000000' None Bit(s) 0 Name Flush all entries Description When set, all dirty entries are flushed to memory but remain in the cache. This bit will reset when the operation is complete. pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 361 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary RXRTO Block Diagram PM Read/Write Interface RXLCD Interface RXQUE Interface RXRTO RTO Nano Processor POOLS Interface RXRTO Functional Description RXRTO performs periodic reassembly timeout processing and LCD update operations. Reassembly Timeout (RTO) Processing Reassembly timeout processing is generally an AAL5 operation. It is supported for other LCD types as well. It can be enabled on an LCD basis by turning on the RTO enable bit in the LCD. The following registers also need to be properly set up to run RTO processing: * RXRTO RTO LCD Table Bound Registers * RXRTO Reassembly Timeout Value Register * RXRTO Reassembly Timeout Pre-Scaler Register See the register descriptions for more register details. The LCD table registers define the LCD table that the RTO process examines. The value register is used as a compare value against a counter that counts based on a pre-scaler. Each time the registers compare, RTO processing is started for a single LCD and the time base is reset. RTO processing checks the RTO test and set bit. If it is reset, it sets it and continues. If it is set, then a timeout occurs and the LC is placed in error state and the current packet is surfaced to the user via an event. Any resource associated with the packet must be recovered by software. For example, if the LCD is setup to use scatter mode, then there may be scatter DMA pages in the DMA list that need to be returned to the proper receive queue. The RTO bit is reset with each inbound cell received. An LCD needs to be touched twice to cause a timeout (once to set it and once to detect that it is already set). The time base starts running as soon as the RTO processing is complete. Thus, RTO processing is a low priority task. Shutting Down an LCD To shut down a receive LCD, the following steps should be followed: Clear the entry for this LCD in the LCD table (to stop receiving cells for this LCD) Do an LCD update operation that sets LCD state to down Read the LCD REASM ptr If REASM ptr is non-zero and LCD is set up to do cut through, be sure to free any DMA descriptor that was added with cut through operation * If REASM ptr is non-zero and LCD is set up to do scatter, be sure to free any pages in the DMA list * If REASM ptr is non-zero, free it to POOLS * * * * Cell/Packet Re-assembly (REASM) Page 362 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.42: RXRTO LCD Update Data Registers These two registers are used to specify data to write into the receive LCD on the update LC operation. They contain the data used in the LC update operation. For more information on their use, see the RXRTO LCD Update Op Registers on page 364. The Update Date Register changes to contain the updated data written to the LC word while the operation is completing. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update 1 register Update 2 register X'00000000' None XXXX 17C0 XXXX 17D0 12.43: RXRTO LCD Update Mask Registers These two registers are used to specify which data to write into the LCD on the update LC operation. They contain the mask used in the LC update operation. For more information on their use, see the RXRTO LCD Update Op Registers on page 364. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update 1 register Update 2 register X'00000000' None XXXX 17C4) XXXX 17D4 pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 363 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 12.44: RXRTO LCD Update Op Registers Used to specify the LCD word to update. This operation is used to update a portion of the receive LCD. If this operation is not used, then software or the IBM3206K0424 updates of the LCD may be lost because the receive LCD is cached in the IBM3206K0424. This register is written with the address of the LCD word to update. Once this register is written the update operation starts. All subsequent reads or writes to the data, mask, or update registers are held off until the operation completes. A read-modify-write will occur to update the portion specified by the mask with the masked value in the data register. Normally this register would not be read. However, if it is read then the low order bit is read as `0' and the next lowest order bit (bit 1) is read as the busy bit. This signifies whether an operation is still going on. If an operation is still going on, then a new write to any of the data, mask, or update operation registers is held off until the original operation is complete. The second set of LCD update registers is meant for the core to use, but is available for general use. Length Type Address Power On Value Restrictions 32 bits Read/Write Update 1 register XXXX 17C8 Update 2 register XXXX 17D8 X'00000000' The low order two bits are not writable 12.45: RXRTO RTO LCD Table Bound Registers Used to specify the lower/upper bounds of the LCD table. The lower bound should be initialized to the LCD index of the first LCD in the LCD table if reassembly timeout processing is to be done. The upper bound should be initialized to the LCD index of the last LC in the LC table if reassembly timeout processing is to be done. Length Type Address 16 bits Read/Write Lower bound 1 register Upper bound 1 register Lower bound 2 register Upper bound 2 register X'00000000' None XXXX 17E0 XXXX 17E4 XXXX 17F0 XXXX 17F4 Power On Value Restrictions Cell/Packet Re-assembly (REASM) Page 364 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 12.46: RXRTO Reassembly Timeout Value Register Used to specify the time interval used for reassembly timeout processing. This register is the number of pre-scaler intervals between reassembly processing. The pre-scaler interval is determined by RXRTO Reassembly Timeout Pre-Scaler Register. A single LC is checked for reassembly timeout during each reassembly processing interval. When this register is set to '0', reassembly timeout processing is disabled. For more information on how reassembly timeout conditions are processed see Reassembly Timeout (RTO) Processing on page 362. Length Type Address Power On Value Restrictions 32 bits Read/Write Timeout 1 register Timeout 2 register X'00000000' None XXXX 17E8 XXXX 17F8 12.47: RXRTO Reassembly Timeout Pre-Scaler Register Used to specify the time interval of each RTO timer tick. This register determines the number of 15 ns intervals between RTO timer ticks. The value in the register plus 1 is the number of 15 ns intervals between RTO timer ticks. Thus, the default value of '0' means that the RTO timer ticks every 15 ns. If a value of nine is placed in this register, the RTO timer ticks every 150 ns (10 * 15 ns). For more information on how reassembly timeout conditions are processed, see Reassembly Timeout (RTO) Processing on page 362. Length Type Address 16 Read/Write Prescale 1 Prescale 2 Power On Value Restrictions X'00000000' None XXXX17EC XXXX 17FC pnr25.chapt05.01 August 14, 2000 Cell/Packet Re-assembly (REASM) Page 365 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 13: Receive Queues (RXQUE) Functional Description RXQUE has a single function: to manage the receive queues for software by providing an easy to use primitive interface. When talking about the receive queues, the term rxq is used to talk about a receive queue, and the term deq is used to refer to a dequeue operation, and the term enq is used to refer to an enqueue operation. Receive Queue Interface A group of sixteen receive queues is available for software use. The receive queues hold events or user specified data. Each queue entry (event) is either 32 or 64 bits and contains two fields: event-identifier and event-information. The seven least significant bits in the entry contain the event-identifier field. The most significant bits in the entry comprise the event-information field. Warning: In order to maintain the atomicity of 64-bit atomic transfers, the user must ensure that 64-bit transfers are bus atomic within the particular bus system in which IBM3206K0424 is being used. The event information typically contains a pointer (when low order bits are zeroed) to a packet buffer, a cell buffer, or an LCD. It can also contain a DMA descriptor address or user-specified data. Event Summary and Routing Information on page 367 lists the different event types. Receive Queues (RXQUE) Page 366 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Event Summary and Routing Information (Page 1 of 3) Event Number 0000000 = 00 0000001 = 01 0000010 = 02 0000011 = 03 0000100 = 04 0000101 = 05 0000110 = 06 0000111 = 07 0001110 = 0e 0001000 = 08 0001001 = 09 0001010 = 0a 0001011 = 0b 0001100 = 0c 0001101 = 0d 0010000 = 10 0010001 = 11 0010010 = 12 0011000 = 18 0011001 = 19 0011010 = 1a 0011011 = 1b 0011100 = 1c 0011101 = 1d 0011110 = 1e 0011111 = 1f 0100000 = 20 0100001 = 21 0100010 = 22 0100011 = 23 0100100 = 24 0100101 = 25 0100110 = 26 0100111 = 27 0101000 = 28 Description AAL5 packet event (packet complete) AAL5 packet header event (packet start) AAL5 packet with bad CRC AAL5 packet with bad length field Event Information Packet/LCD Packet Packet/LCD Packet/LCD X X X X X X Error Count Tx Comp ABR POOLS AAL5 packet that exceeds maximum length in LC Packet/LCD AAL5 packet timeout AAL5 packet forward abort AAL5 packet CPI field not equal to zero AAL5 FIFO packet Cell event (user data) NUD cell event (non-user data) NUD cell with bad CRC-10 Bad cell - bad HEC Bad cell - out of range Bad cell - index equal zero AAL0 cell dropped - lack of POOLS buffers AAL5 cell dropped - lack of POOLS buffers OAM cell dropped - lack of POOLS buffers Total user cells receive counter overflow Total user cells rx clp=0 counter overflow Total user cells tx counter overflow Total user cells tx clp=0 counter overflow Threshold 1 crossed - down Threshold 1 crossed - up Threshold 1 crossed - down Threshold 2 crossed - up Transmit complete Transmit complete buffer freed "bad" found in first word of packet Connection closed Transmit DMA complete Receive DMA complete Transmit DMA complete with error Receive DMA complete with error Transmit DMA complete with virtual error Packet/LCD Packet/LCD Packet/LCD Packet Packet/LCD Packet/LCD Packet/LCD Packet Packet Packet LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD LCD Packet Packet/LCD Packet LCD Descriptor Descriptor Descriptor Descriptor Descriptor X X X X X X X X X X X X X X X X X X X pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 367 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Event Summary and Routing Information (Page 2 of 3) Event Number 0101001 = 29 0101010 = 2a 0101100 = 2c 0101101 = 2d 0101110 = 2e 0101111 = 2f 0110000 = 30 0110001 = 31 0110010 = 32 0110011 = 33 0110100 = 34 0110101 = 35 0110110 = 36 0110111 = 37 0111000 = 38 0111001 = 39 0111010 = 3a 0111011 = 3b 0111100 = 3c 0111101 = 3d 0111110 = 3e 1000000 = 40 1000001 = 41 1000010 = 42 1000011 = 43 1000100 = 44 1000101 = 45 1000110 = 46 1000111 = 47 1010000 = 50 1010001 = 51 1010010 = 52 1010011 = 53 1010100 = 54 1010101 = 55 Description Zero address in DMA descriptor SRC/DST address Transmit buffer allocated ADTF Event CRM Event CCR=0 Event RM Cell Event User event User event User event User event User event User event User event User event Virtual memory resource event Buffer overflow event No DMA descriptor for AAL7 packet DMA canceled for AAL7 packet due to error No scatter pages available and packet complete Entity counter overflow event POOLS status event Frame event (good frame) Frame event (error) Frame event (protocol error) Frame event (dropped - lack of buffers) Frame event (reserved) Frame event (reserved) Frame event (reserved) Frame event (reserved) PCORE event PCORE event PCORE event PCORE event PCORE event PCORE event X X X Packet/LCD Packet/LCD Packet/LCD Descriptor Packet/LCD Counter Status X X X X X X LCD LCD LCD Packet X X X X Event Information Descriptor Error Count Tx Comp ABR POOLS Receive Queues (RXQUE) Page 368 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Event Summary and Routing Information (Page 3 of 3) Event Number 1010110 = 56 1010111 = 57 1011000 = 58 1011001 = 59 1011100 = 5c 1011101 = 5d 1011110 = 5e 1011111 = 5f 1100100 = 64 1100101 = 65 1100110 = 66 1100111 = 67 1101000 = 68 1101001 = 69 PCORE event PCORE event REASM counter-overflow event SEGBF counter-overflow event System - receive queue event (start of buffer) System - receive queue event (end of buffer) Timestamp event 64-bit timestamp event Tx DMA complete Rx DMA complete Tx DMA complete with error Rx DMA complete with error Tx DMA complete with virtual error Zero address in DMA descriptor SRC/DST address Counter Counter Previous lower bound Next lower bound Timestamp Timestamp Descriptor Descriptor Descriptor Descriptor Descriptor Descriptor X X Description Event Information Error Count Tx Comp ABR POOLS pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 369 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary AAL5 Packet Events For AAL5 packet events, the event specifies the packet buffer address, and the event type field specifies the type of packet event. The following event types are defined: Bit(s) 0x00=0000000 Name Normal AAL5 Packet Event (Packet Complete) Description This event specifies that an AAL5 packet was received and has passed all AAL5 protocol checks (CRC, length). The event information contains a pointer to the packet. This event specifies that an AAL5 FIFO packet was received and has passed all AAL5 protocol checks (CRC, length,...). The event information contains a pointer to the packet. This event specifies that the AAL5 packet header threshold was exceeded as set in the LCD. The event information contains a pointer to the packet header, and the user can access up to the packet header threshold bytes of data. This event specifies that an AAL5 packet was received and the AAL5 CRC is bad. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that a AAL5 packet was received and the AAL5 length field is bad. For example, there is too much data or not enough, but typically the bad CRC is detected first. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that an AAL5 packet was received but the amount of data has exceeded the maximum length as specified in the LCD or in the MSDU register. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that a reassembly timeout has occurred for an AAL5 packet that was being reassembled. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that an AAL5 packet was terminated with a forward abort. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that a AAL5 packet was received and the AAL5 CPI field was not set to '0' which is an AAL5 protocol violation. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. 0x0e=0001110 Normal AAL5 FIFO Packet Event 0x01=0000001 Normal AAL5 Packet Header Threshold Event (Packet Start) AAL5 Packet with Bad CRC was RX on LC 0x02=0000010 AAL5 Packet with Bad Length 0x03=0000011 Field was RX on LC 0x04=0000100 AAL5 Packet that exceeds Max Len in LC was RX 0x05=0000101 AAL5 Packet Timeout on this LC 0x06=0000110 AAL5 Packet Forward Abort 0x07=0000111 AAL5 Packet CPI Field not equal to Zero Receive Queues (RXQUE) Page 370 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Cell Events For AAL0 events, the event specifies a cell buffer address, and the event type field specifies type of AAL0 event. The following event types are defined: Bit(s) Name Description This event specifies that an AAL0 (non-FIFO mode) cell was received. The event information contains a pointer to the cell. This event specifies that a non-user data cell was received and the CRC-10 was good if checking was enabled. The event information contains a pointer to the cell. This event specifies that a non-user data cell was received and the CRC-10 was bad. The event information contains either a pointer to the cell if receiving bad frames, or a pointer to the LCD on which this cell was received. This event specifies that a cell was received with a bad HEC. The event information contains a pointer to the cell. This event specifies that a cell was received with a VP/VC that was out of range. The event information contains a pointer to the cell. This event specifies that a cell was received with a VC index equal zero. The event information contains a pointer to the cell. 0x08=0001000 AAL0 Cell Event 0x09=0001001 Non-User Data Cell Event Non-User Data Cell with Bad CRC-10 Event 0x0a=0001010 0x0b=0001011 Cell with Bad HEC Event 0x0c=0001100 Cell with VP/VC Out Of Range Event 0x0d=0001101 Cell with VC Index Equal Zero pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 371 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary LC Events For LC events, the event specifies a LC, and the event type field specifies what happened on the LC. The following event types are defined: Bit(s) 0x10=0010000 Name AAL0 Cell was Dropped due to Lack of POOLS Buffers AAL5 Cell was Dropped due to Lack of POOLS Buffers Non-user Data Cell was Dropped due to Lack of POOLS Buffers Description This event specifies that a AAL0 (non-FIFO mode) cell was received, but was discarded because no POOL buffers were available. The event information contains a pointer to the LCD on which this cell was received. This event specifies that the first AAL5 cell for a packet was received, but was discarded because no POOL buffers were available. The event information contains a pointer to the LCD on which this cell was received. This event specifies that a non-user data cell was received, but was discarded because no POOL buffers were available. The event information contains a pointer to the LCD on which this cell was received. Reserved This event specifies that the TUC RX counter in the LCD has overflowed. The event information contains a pointer to the LCD. This event specifies that the TUC w/CLP=0 RX counter in the LCD has overflowed. The event information contains a pointer to the LCD. This event specifies that the TUC TX counter in the LCD has overflowed. The event information contains a pointer to the LCD. This event specifies that the TUC w/CLP=0 TX counter in the LCD has overflowed. The event information contains a pointer to the LCD. 0x11=0010001 0x12=0010010 0x17=0010111 Reserved 0x18=0011000 0x19=0011001 0x1a=0011010 0x1b=0011011 LC Total User Cells RX Counter Overflow LC Total User Cells CLP=0 RX Counter Overflow LC Total User Cells TX Counter Overflow LC Total User Cells CLP=0 TX Counter Overflow ABR Events The following events are used for ABR processing and are routed to the receive queue specified in the ABR event routing register. Bit(s) 0x2c=0101100 ADTF Event 0x2d=0101101 CRM Event 0x2e=0101110 CCR = 0 Event 0x2f=0101111 RM Cell Rx-ed Name Description This event specifies that the ADTF timer expired. The event information contains a pointer to the LCD. This event specifies that the CRM count has been exceeded. The event information contains a pointer to the LCD. This event specifies that CCR = 0. The event information contains a pointer to the LCD. This event specifies that a RM cell was received. The event information contains a pointer to the receive buffer. Receive Queues (RXQUE) Page 372 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Miscellaneous Events Bit(s) Name Description This event specifies that a memory management threshold was crossed downwards. The event information contains the LCD address. This event specifies that a memory management threshold was crossed upwards. The event information contains the LCD address. This event specifies that a memory management threshold was crossed downwards. The event information contains the LCD address. This event specifies that a memory management threshold was crossed upwards. The event information contains the LCD address. This event specifies that a packet/cell was successfully transmitted. The event information contains a pointer to the buffer transmitted. This event specifies that a packet/cell was successfully transmitted and the buffer was freed back to POOLS. The event information contains a pointer to the buffer transmitted. This event specifies that a packet was to be transmitted, but the buffer was marked as bad, so was canceled. This is caused by getting a page fault when DMAing into the transmit packet buffer. The event information contains a pointer to the bad buffer. This event specifies that all packets for the given LCD have been transmitted. The event information contains the LCD address. This event specifies that a TX DMA completed successfully. The event information depends on how the DMA was set up. Event-identifier 0x64 is an alias. This event specifies that an RX DMA completed successfully. The event information depends on how the DMA was set up. Event-identifier 0x65 is an alias. 0x1c=0011100 Thresh 1 Event - Down 0x1d=0011101 Thresh 1 Event - Up 0x1e=0011110 Thresh 2 Event - Down 0x1f=0011111 Thresh 2 Event - Up 0x20=0100000 Transmit Complete 0x21=0100001 Transmit Complete Buffer Freed 0x22=0100010 Transmit Bad 0x23=0100011 Connection Closed 0x24=0100100 0x25=0100101 0x26=0100110 0x27=0100111 TX DMA Complete (into IBM3206K0424) RX DMA Complete (out of IBM3206K0424) TX DMA Complete with Error (into This event specifies that a TX DMA had errors. The event information depends on IBM3206K0424) how the DMA was set up. Event-identifier 0x66 is an alias. RX DMA Complete with Error (out This event specifies that an RX DMA had errors. The event information depends of IBM3206K0424) on how the DMA was set up. Event-identifier 0x67 is an alias. TX DMA Complete with Virtual Error This event specifies that a TX DMA had a virtual error. The remainder of the DMA descriptor was cancelled. The event information contains the DMA descriptor address. Event-identifier 0x68 is an alias. This event specifies that a DMA descriptor source destination address was zero. The remainder of the DMA descriptor was cancelled. The event information contains the DMA descriptor address. Event-identifier 0x69 is an alias. 0x28=0101000 0x29=0101001 DMA Desc has Zero Address 0x2a=0101010 Transmit-Buffer Allocated 0x30=0110000 User Defined 0x31=0110001 User Defined 0x32=0110010 User Defined 0x33=0110011 User Defined 0x34=0110100 User Defined 0x35=0110101 User Defined 0x36=0110110 User Defined 0x37=0110111 User Defined pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 373 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Miscellaneous Events (Continued) Bit(s) Name Description This event specifies that an AAL5 cell was received, but could not be written into the buffer because a virtual memory boundary was crossed and a buffer was not available to fill in the next segment. This can also happen if the cell crosses a boundary that would make the buffer larger than the virtual buffer size. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that an AAL5 cell was received, but could not be written into the buffer because it would exceed the real buffer size. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that an AAL7 (AAL5 with cut through) packet was completed, but no DMA descriptors were available to DMA the packet header. The event information contains either a pointer to the packet if receiving bad frames, or a pointer to the LCD on which this packet was received. This event specifies that a DMA descriptor enqueued with a cut-through operation was cancelled because an error condition was detected with the packet (CRC, length,...). The event information contains the system descriptor address that was cancelled. This event specifies that an AAL5 packet completed with no errors, but there was a lack of scatter buffers to complete the scatter DMA. The user must interrogate the partial DMA list in the packet header to recover the system pages. Once this is done, the packet should be freed. The user can alternately treat this as a good packet and complete the packet processing by setting up additional DMAs to move the remaining data to system pages. The event information contains the IBM3206K0424 buffer address. 0x38=0111000 Virtual Memory Resource Event 0x39=0111001 Buffer Overflow Event 0x3a=0111010 No DMA Desc for AAL7 Packet Event DMA Cancelled for AAL7 Packet 0x3b=0111011 Due to Error Event 0x3c=0111100 No Pages Available for AAL5 Scatter Packet This event specifies that a counter overflow event has been raised. The event information specifies which counter overflowed. Multiple counter overflows can be specified with a single event. The following is the definition of the event information: IBM3206K0424 Counter Overflow Bit 27 GPDMA Write DMA Byte Count Overflow 0x3d=0111101 Event Bit 26 GPDMA Read DMA Byte Count Overflow Bit 25 RXQUE Timestamp Counter Overflow Bit 24 PCINT Performance Counter 1 Overflow Bit 23 PCINT Performance Counter 2 Overflow 0x3e=0111110 POOLS Status Event This event specifies that a POOLS status event has been raised. The event information contains the status. See Buffer Pool Management (POOLS) on page 247 for the definition. This event specifies that a timestamp event has been placed ahead of next event. The event information contains the timestamp. This event specifies that a timestamp event has been placed ahead of next event. The most significant word in the event-information field contains the full 32-bit timestamp. 0x5e=1011110 Timestamp Event 0x5f=1011111 64-bit Timestamp Event Receive Queues (RXQUE) Page 374 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Frame-Based Events Bit(s) Name Description 0x40=1000000 Frame Event (good frame) 0x41=1000001 Frame Event (error) 0x42=1000010 Frame Event (protocol error) 0x43=1000011 Reserved (dropped - lack of buffers) 0x44=1000100 Reserved 0x45=1000101 Reserved 0x46=1000110 Reserved 0x47=1000111 Reserved PCORE Events Bit(s) Name Description 0x50=1010000 PCORE Event 0x51=1010001 PCORE Event 0x52=1010010 PCORE Event 0x53=1010011 PCORE Event 0x54=1010100 PCORE Event 0x55=1010101 PCORE Event 0x56=1010110 PCORE Event 0x57=1010111 PCORE Event 0x58=1011000 REASM Counter-Overflow Event 0x59=1011001 SEGBF Counter-Overflow Event This specifies that REASM raised counter-overflow event. The event information specifies which counter overflowed. This specifies that SEGBF raised counter-overflow event. The event information specifies which counter overflowed. System-Receive-Queue Events Bit(s) 0x5c=1011100 0x5d=1011101 Name System-Receive-Queue Start-of-Buffer Event System-Receive-Queue End-of-Buffer Event Description The receive queues are maintained by RXQUE with the following operations being available to software: * dequeue - Remove the entry at the head of the queue * enqueue - Add arbitrate entry at the tail of the queue The following figure shows how events in a receive queue link to other data structures including LC control blocks, packet buffers, and cell buffers. pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 375 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary General Queue, Event, and Data Structure Linkage 1C CB Head Status 1C Raw Packet Event Event Event Event Event Tail Event 1C Info Raw Cell Header Data Packet Header Data Receive Queues (RXQUE) Page 376 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXQUE Structure Each queue has a number of registers that define the queue and its behavior: Lower bound Properties Head pointer Tail pointer Queue length Threshold Next lower bound Pointer to starting address of queue's buffer Indicates the queue's size, type, and behavior Pointer to head of queue Pointer to the next free entry in queue - points to head if queue is full or empty Current length of the queue Length threshold used to generate interrupts Pointer to starting address of a system receive queue's next buffer RXQUE Initialization To set up a receive queue, at least two pieces of information are needed. The first is the receive queue's set of properties, and the second is its base address. The following restrictions should be taken into account when setting up a queue: * The properties register must be set up before the lower-bound and next-lower-bound registers can be set up. * The lower bound and next lower bound must be at least 1K aligned. The low order 10 bits of these registers are not writable, so the minimum physical size of a receive queue is 1024 bytes (256 32-bit entries). The alignment should correspond to the size specified in the properties register. * The head and tail pointers are initialized when the lower bound register is written. These registers are only writable for diagnostic purposes. * The threshold is level sensitive, so as long as the queue length is greater than or equal to the threshold, the appropriate status bit is driven. * All registers, except the threshold and next-lower-bound registers, can only be written in diagnostic mode and are intended to only be written once when they are set up. pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 377 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary RXQUE Event Routing Events are routed to a receive queue based on the current event type and mode of the chip. Events fall into these categories: * * * * * * * Normal Events Error Events Counter Events Transmit Complete Events DMA Events (tx/rx) ABR Events POOLS Status Events See Event Summary and Routing Information on page 367 to see how the different events are categorized. All events other than normal, DMA, and error events are routed using the corresponding RXQUE Event Routing Registers. Normal events are always routed to the receive queue specified in the receive portion of the LCD. DMAQS specifies the route for all DMA events. Error events are special, in that they are routed based on the values of the "receive bad frame mode" bit and the "always route error events" mode bit in RXQUE Control Register. If the "always route error events" bit is on, then the error events are always routed to the error queue. Otherwise, if the receive bad frame mode is on, then the error events are routed to the receive queue specified in the receive portion of the LCD just like a normal event would be. When receive bad frames is off, then the error events are routed to the error queue. Receive Queues (RXQUE) Page 378 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources RXQUE Normal Operation This section describes how to use the receive queues (rxq) and the rxq operations. The receive queue contains events for the end user to process. These events are obtained by the user by executing the rxq deq operation. The user can be notified of new events by setting up the threshold and interrupt enable registers appropriately. Otherwise, the rxq length register can be polled to check for events. The deq operation is executed by reading the deq register address for the appropriate rxq. The event at the head of the queue is returned and the event is removed from the queue. Some events have a packet/cell buffer associated with it. This buffer is owned by the user, and it is the users responsibility to free this buffer. The following pseudo code illustrates how an rxq could be processed: RXQUE Dequeue Event Loop // rxq was polled or int ocurred to get here Event = RXQUE->Deq; // read an event from rxq if (Event neq 0) { // need to check for null event EventType = Event & 0x7f; // calc event type Event = Event & ~(0x7f); // calc lc or buffer ptr switch (EventType) { case(Event1): ProcessSimpleEvent1(Event); break; case(Event2): ProcessSimpleEvent2(Event); break; case(EventX): ProcessSimpleEventX(Event); break; } } RXQUE Queue Full Operation When a receive queue is full (length is equal to maximum length), the appropriate status bit is set. When a queue is full, all subsequent events are flushed until room is available in the receive queue. If a buffer was associated with the event and the RXQUE-Properties-Register bit Disable Auto-Free is not set, then that buffer is freed back to POOLS. When an event is dropped, the event dropped status bit is set and the event data that was dropped can be found in RXQUE Last Event Dropped Register. The RXQUE Last Event Dropped Register will not be changed until the event dropped status bit is cleared. It is not good to let a receive queue become full. pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 379 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary RXQUE Event Timestamping When timestamp mode is set in the RXQUE Control Register, events are timestamped. When timestamping is enabled, a timestamp event is placed in the corresponding rxq followed by the actual event. The event information of the timestamp event carries the timestamp. The timestamp is determined from the RXQUE Timestamp Register, RXQUE Timestamp Pre-Scaler Register, and the RXQUE Timestamp Shift Register. If the corresponding rxq is full, both events are dropped. It is possible to lose only the timestamp event or lose the actual event depending on the length of the queue and the timing of the dequeue operations. RXQUE System Receive Queues To set up a system receive queue, set the "Diagnostic-Mode" bit in the RXQUE Control Register. Next, set the system receive queue bit in the RXQUE Properties Register. Load the upper bound and size of event fields, as well. After this, allocate two identical buffers in system memory. Let each buffer be large enough to contain N events (the upper bound field prescribes the value N) and initialize both to all zeros. Write one buffer's starting address into the RXQUE Lower Bound Register (LOBR), and write the other's starting address into the RXQUE Next Lower Bound Register (NLBR). Finally, reset the diagnostic mode bit in the RXQUE Control Register. System-receive-queue setup is complete. The first event enqueued to a system receive queue causes RXQUE to begin filling the buffer which LOBR references. RXQUE fills the buffer's first entry with a "System-Receive-Queue Start-of-Buffer" event whose information is the value `0'. After this, RXQUE fills the buffer's second entry with the enqueued event and writes the value `2' into the RXQUE Length Register (LENR). The second event enqueued to the system receive queue causes RXQUE to fill the buffer's third entry and write the value `3' into LENR. The third event enqueued to the system receive queue causes RXQUE to fill the buffer's fourth entry and write the value `4' into LENR. This continues until LENR contains the value `N-1'. At that time, RXQUE fills the buffer's Nth entry with a System-receive-queue end-of-buffer event whose information is the value in NLBR. After this, RXQUE begins filling the buffer which NLBR references. RXQUE fills its first entry with a "System-Receive-Queue Start-of-Buffer" event whose information is the value in LOBR. After this, RXQUE copies the contents of NLBR into LOBR and writes the value `1' into LENR. Finally, RXQUE writes the value `0' into NLBR. Subsequent events enqueued to the system receive queue fill the buffer which LOBR references. To prevent the system receive queue from becoming full, write a non-zero value into NLBR. The system receive queue becomes full when the value in LENR becomes `N-1' while NLBR contains the value `0'. At that time, RXQUE fills the buffer's Nth entry with a system-receive-queue end-of-buffer event whose information is the value `0'. RXQUE writes the value N into LENR and preserves the contents of LOBR while dropping subsequent enqueued events. To restart the system receive queue from the "full" state, write a non-zero value into NLBR. After restarting, the next event enqueued to the system receive queue causes RXQUE to begin filling the buffer which NLBR references. RXQUE fills the buffer's first entry with a system-receive-queue start-of-buffer event whose information is the value preserved in LOBR. RXQUE fills the buffer's second entry with the enqueued event. After this, RXQUE copies the contents of NLBR into LOBR and writes the value `2' into LENR. Finally, RXQUE writes the value `0' into NLBR. Subsequent events enqueued to the system receive queue fill the buffer which LOBR references. To prevent the system receive queue from becoming full, write a non-zero value into NLBR. The RXQUE Queues' Status Register bit "Threshold Exceeded" indicates that the value in LENR is greater than or equal to the value in the RXQUE Threshold Register while NLBR contains the value `0'. To reset this Receive Queues (RXQUE) Page 380 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources status bit, write a non-zero value into NLBR. Events enqueued to a system receive queue may not be dequeued via the RXQUE Dequeue Register. To dequeue from a system receive queue, poll system memory directly. A buffer's entry is filled if its value is non-zero. RXQUE synchronizes its internal-register operations with the initiation, rather than completion, of its system-memory operations. Therefore, the state of system memory lags the state of RXQUE. pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 381 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.1: RXQUE Lower Bound Registers These registers specify the lower bound of the corresponding receive queue data structure. The head and tail of the receive queue are initialized when this register is written. When the receive queue wraps past the upper bound, it wraps back to the value in the lower bound register, thus implementing the receive queue as a circular buffer. When this register is written, the corresponding receive queue is essentially reset. This is because the head, tail, and length of the queue are all reset. The length of the RXQUE Lower Bound Register is 64 bits if all three conditions, below, are met; otherwise, the length is 32 bits. * System Receive-Queue in the RXQUE Properties Register is set. * System-Memory Select in the RXQUE Properties Register indicates "PCI Memory." * Enable Master 64-bit Addressing in the PCINT 64bit Control Register is set. Length Type Address 32 or 64 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'0000000000000000' During normal operations, these registers are read only. These registers can only be written when the diagnostic bit has been set in the control register. The lower bound registers must be at least 1K aligned (low order 10 bits not writable). The alignment should also correspond to the size specified in the upper bound register. For example, it should be 4K aligned if the upper bound specifies 4K size. XXXX 1800 XXXX 1840 XXXX 1880 XXXX 18C0 XXXX 1900 XXXX 1940 XXXX 1980 XXXX 19C0 XXXX 1A00 XXXX 1A40 XXXX 1A80 XXXX 1AC0 XXXX 1B00 XXXX 1B40 XXXX 1B80 XXXX 1BC0 Receive Queues (RXQUE) Page 382 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.2: RXQUE Properties Registers These registers specify the properties of the corresponding receive queue. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00010001' Bits 11-0 may only be written when the diagnostic bit has been set in the control register. There are no restrictions for bits 32-12. XXXX 1808 XXXX 1848 XXXX 1888 XXXX 18C8 XXXX 1908 XXXX 1948 XXXX 1988 XXXX 19C8 XXXX 1A08 XXXX 1A48 XXXX 1A88 XXXX 1AC8 XXXX 1B08 XXXX 1B48 XXXX 1B88 XXXX 1BC8 pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 383 of 676 IBM3206K0424 IBM Processor for Network Resources Status-Multiplexer Control Preliminary System Receive Queue Disable BCACH Advice System-Memory Select Disable Timestamps Disable Auto-Free Queue Direction Reserved Size of Event Reserved Reserved Upper Bound 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-18 Reserved Name Reserved. 00 01 10 11 9 8 7 6 5 4 3 2 1 0 Description 17-16 Status-Multiplexer control Select "Full/Empty" Select "Threshold Exceeded" (power-on value) Select "Head Valid" Reserved 15 14 13 Disable Auto-Free Disable BCACH Advice Disable Timestamps Inhibits freeing of packet-buffers when the receive queue is full. When set, the bcach advice is disabled for this queue. This is necessary in order to use a queue as a general purpose container for user data. When set, timestamps are disabled for this queue. This is necessary in order to run cut through modes. When set, the direction of the queue is assumed to be reversed. This only affects the full condition and the threshold exceeded condition. When this bit is set, the polarity of these status signals changes. Thus, the full condition becomes an empty condition, and the two threshold conditions trigger when the length of the queue is less than the corresponding threshold instead of greater than or equal. This mode is mainly used for queues that relay information from the system to the IBM3206K0424. Also, event enqueues to a queue that is reversed do not start the event latency timer (since no new event for system has arrived). Reserved This is valid only when bit 9 (System Receive Queue) is set. 0 PCI Memory (power-on value) 1 On-Chip Memory 12 Queue Direction 11 10 9 8 7-4 Reserved System-Memory Select System Receive Queue Size of Event Reserved 0 1 32 bits (power-on value) 64 bits Reserved Receive Queues (RXQUE) Page 384 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description This specifies the encoded upper bound of the corresponding receive queue data structure. The actual upper bound is calculated by adding the decoded queue size to the lower bound. When the receive queue wraps past the upper bound, it wraps back to the lower bound register, thus implementing the receive queue as a circular buffer. 0000 Reserved 0001 256 entries (power-on value) 0010 512 entries 0011 1024 entries 0100 2K entries 0101 4K entries 0110 8K entries 0111 16K entries 1000 32K entries 1001 64K entries 101- Reserved 11-- Reserved 3-0 Upper Bound pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 385 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.3: RXQUE Head Pointer Registers These registers point to the head element of the corresponding receive queue. During normal operations, these registers do not need to be read or written, as they are used by the IBM3206K0424 to implement the receive queues. These registers are initialized when the lower bound register for the corresponding receive queue is written. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. These registers can only be written when the diagnostic bit has been set in the control register. The head pointer registers are four-byte aligned (low order two bits not writable). Bits 31-19 are calculated internally, and are not writable. XXXX 1810 XXXX 1850 XXXX 1890 XXXX 18D0 XXXX 1910 XXXX 1950 XXXX 1990 XXXX 19D0 XXXX 1A10 XXXX 1A50 XXXX 1A90 XXXX 1AD0 XXXX 1B10 XXXX 1B50 XXXX 1B90 XXXX 1BD0 Receive Queues (RXQUE) Page 386 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.4: RXQUE Tail Pointer Registers These registers point to the next free element of the corresponding receive queue. During normal operations, these registers do not need to be read or written, as they are used by the IBM3206K0424 to implement the receive queues. These registers are initialized when the lower bound register for the corresponding receive queue is written. Length Type Address 32 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000000' During normal operations, these registers are read only. These registers can only be written when the diagnostic bit has been set in the control register. The tail pointer registers are four-byte aligned (low order two bits not writable). Bits 31-19 are calculated internally, and are not writable. XXXX 1814 XXXX 1854 XXXX 1894 XXXX 18D4 XXXX 1914 XXXX 1954 XXXX 1994 XXXX 19D4 XXXX 1A14 XXXX 1A54 XXXX 1A94 XXXX 1AD4 XXXX 1B14 XXXX 1B54 XXXX 1B94 XXXX 1BD4 pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 387 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.5: RXQUE Length Registers These registers specify the length (number of valid entries) of the corresponding receive queue. They can be used to query the status of a receive queue. This register is cleared when the corresponding lower bound is written. Length Type Address 17 bits Read Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000' These registers can only be written in diagnostic mode. XXXX 1818 XXXX 1858 XXXX 1898 XXXX 18D8 XXXX 1918 XXXX 1958 XXXX 1998 XXXX 19D8 XXXX 1A18 XXXX 1A58 XXXX 1A98 XXXX 1AD8 XXXX 1B18 XXXX 1B58 XXXX 1B98 XXXX 1BD8 Receive Queues (RXQUE) Page 388 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.6: RXQUE Threshold Registers These registers specify a queue length threshold at which the corresponding status bit is generated. These registers should be set equal to the number of queue entries that should cause status to be generated. For example, if the value was set to five, then no interrupt would be generated until five or more events were queued on the corresponding receive queue. The threshold is level sensitive, so as long as the length is greater than or equal to the threshold, the corresponding status bit is set. When this register is set to '0', no thresholding is done. When the direction bit is set for a receive queue, the threshold has the opposite polarity. For example, as long as there are more events in the queue than specified in the threshold register, no status would be raised. Length Type Address 17 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000' None XXXX 181C XXXX 185C XXXX 189C XXXX 18DC XXXX 191C XXXX 195C XXXX 199C XXXX 19DC XXXX 1A1C XXXX 1A5C XXXX 1A9C XXXX 1ADC XXXX 1B1C XXXX 1B5C XXXX 1B9C XXXX 1BDC pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 389 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.7: RXQUE Dequeue Registers These registers are used to retrieve the event at the head of the corresponding receive queue. These registers are used to retrieve the event at the head of the corresponding receive queue. The length of an RXQUE Dequeue Register is 64 bits if Size of Event is set in its corresponding RXQUE Properties Register; otherwise, the length is 32 bits. Length Type Address 32 or 64 bits Read Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000000' This is a read only register, and all writes will be ignored. Events are only returned when the diagnostic bit is reset in the control register, otherwise zero will be returned. XXXX 1820 XXXX 1860 XXXX 18A0 XXXX 18E0 XXXX 1920 XXXX 1960 XXXX 19A0 XXXX 19E0 XXXX 1A20 XXXX 1A60 XXXX 1AA0 XXXX 1AE0 XXXX 1B20 XXXX 1B60 XXXX 1BA0 XXXX 1BE0 Receive Queues (RXQUE) Page 390 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.8: RXQUE Enqueue Registers These registers are used to enqueue user events at the tail of the corresponding receive queue. The length of a RXQUE Enqueue Register is 64 bits if Size of Event is set in its corresponding RXQUE Properties Register; otherwise, the length is 32 bits. Length Type 32 or 64 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'00000000' All reads result in zero. RXQUE should be enabled to do this. XXXX 1828 XXXX 1868 XXXX 18A8 XXXX 18E8 XXXX 1928 XXXX 1968 XXXX 19A8 XXXX 19E8 XXXX 1A28 XXXX 1A68 XXXX 1AA8 XXXX 1AE8 XXXX 1B28 XXXX 1B68 XXXX 1BA8 XXXX 1BE8 pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 391 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.9: RXQUE Next Lower Bound Registers These registers specify the next lower bound of the corresponding system receive queue data structure. See RXQUE System Receive Queues on page 380 for instruction about managing system receive queues. The length of the RXQUE Next Lower Bound Register is the same as the length of the RXQUE Lower Bound Register. See RXQUE Lower Bound Registers on page 382 for conditions which determine the length. Length Type 32 or 64 bits Read/Write Queue 0 Queue 1 Queue 2 Queue 3 Queue 4 Queue 5 Queue 6 Queue 7 Queue 8 Queue 9 Queue 10 Queue 11 Queue 12 Queue 13 Queue 14 Queue 15 Power on Value Restrictions X'0000000000000000' None XXXX 1830 XXXX 1870 XXXX 18B0 XXXX 18F0 XXXX 1930 XXXX 1970 XXXX 19B0 XXXX 19F0 XXXX 1A30 XXXX 1A70 XXXX 1AB0 XXXX 1AF0 XXXX 1B30 XXXX 1B70 XXXX 1BB0 XXXX 1BF0 Receive Queues (RXQUE) Page 392 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.10: RXQUE Last Event Dropped Register This register contains the last event that was dropped. It holds its value until the event dropped status bit is cleared. The length of the RXQUE Last Event Dropped Register is 64 bits if Size of Dropped Event is set in the RXQUE Status Register; otherwise, the length is 32 bits. Length Type Address Power On Value Restrictions 32 or 64 bits Read/Write XXXX 1C10 X'0000000000000000' None 13.11: RXQUE Timestamp Register Used to specify the current timestamp measured using the timestamp pre-scaler ticks. It counts based on the value in the RXQUE Timestamp Pre-Scaler Register. It can be read or written at any time. It is cleared when the pre-scaler register is written. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1C30 X'00000000' None 13.12: RXQUE Timestamp Pre-Scaler Register Used to specify the time interval of each timestamp timer tick. This register determines the number of 15 ns intervals between timestamp timer ticks. The value in the register plus one is the number of 15 ns intervals between timestamp timer ticks. So, the default value of '0' means that the timestamp timer ticks every 15 ns. If a value of four is placed in this register, the timestamp timer ticks every 75 ns (5 x 15 ns). Length Type Address Power On Value Restrictions 16 bits Read/Write XXXX 1C38 X'00000000' None pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 393 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.13: RXQUE Timestamp Shift Register This register determines the number of bits that the timestamps are shifted. For example, if a value of '0' is placed in this register, then the timestamp is not shifted, and the low order seven bits are lost. If a value of `2' is placed in this register, then the timestamps are shifted two places and only the low order five bits of the timestamp are lost. This allows the user to control what portion of the timestamp is lost due to the low order event bits. Length Type Address Power On Value Restrictions 3 bits Read/Write XXXX 1C3C X'00000002' None 13.14: RXQUE Event Routing Registers Used to specify which receive queue different types of events should be routed to. These registers contain the receive queue that different types of events should be routed to. See Event Summary and Routing Information on page 367 for event type mappings. Length Type Address 3 bits Read/Write Event Tx Complete XXXX 1C40 Event Counter Overflow XXXX 1C44 Event Error Event POOLS Status Event ABR Power on Value Restrictions X'00000000" None XXXX 1C48 XXXX 1C54 XXXX 1C58 Receive Queues (RXQUE) Page 394 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.15: RXQUE Event Latency Timer Register Used to specify the event latency time interval. This register is specified in 15 ns intervals. When a new event is placed on an rxq, the event latency timer is started (if not already started). When this timer expires, the event latency timer expired status bit is set, and the timer is stopped. The status bit must be reset before the timer is started again. Every time the status register (or prioritized status) is accessed, the timer is stopped. If this register is written while the timer is running, the new value takes effect immediately. If this register is set to '0', the latency timer does not run. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 1C20 X'00000000' None pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 395 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.16: RXQUE Queues Status Register Indicates the status for all receive queues. Length Type Address Power On Value Restrictions Queue 15 Queue 14 64 bits Read only XXXX 1D40 X'0000000000000000' This is a read only register Queue 13 Queue 12 Queue 11 Queue 10 Queue 9 Queue 8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 22 32 Queue 7 Bit(s) 63-60 59-56 55-52 51-48 47-44 43-40 39-36 35-32 31-28 27-24 23-20 19-16 15-12 11-8 7-4 3-0 Queue 6 Name Queue 5 Queue 4 Queue 3 Queue 2 Description Queue 1 Queue 0 Statue-nibble for queue 15 Statue-nibble for queue 14 Statue-nibble for queue 13 Statue-nibble for queue 12 Statue-nibble for queue 11 Statue-nibble for queue 10 Statue-nibble for queue 9 Statue-nibble for queue 8 Statue-nibble for queue 7 Statue-nibble for queue 6 Statue-nibble for queue 5 Statue-nibble for queue 4 Statue-nibble for queue 3 Statue-nibble for queue 2 Statue-nibble for queue1 Statue-nibble for queue 0 For each 4-bit range, bit encoding is as follows: 3 Reserved Reserved 2 Head valid This is set when the head is valid for the queue. If this bit is set, then a deque operation should complete successfully. 1 Threshold exceeded This is set when the queue-length register equals or exceeds the value in the queue-threshold register. 0 Queue Full/Empty This is set when the queue-length register is equal to the queue-maximum-length register. When the direction of the queue is reversed, this bit is set when the queue is empty. Receive Queues (RXQUE) Page 396 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 13.17: RXQUE Interrupt Enable Registers Used to specify which status register bits should be used to generate interrupts. Each mask register is used to drive a different RXQUE status bit in intst. The different masks and status bits allow two RXQUE interrupts on both the interrupt A and B pins. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See RXQUE Status and Enabled Status Registers on page 398 for the bit descriptions. Length Type Address 32 bits Clear/Set Enable 1 Enable 2 Power on Value Restrictions Enable 1 - 2 None XXXX 1A80 and C84 XXXX 1C88 and C8C X'00000000' pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 397 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.18: RXQUE Status and Enabled Status Registers This register contains the status bits used to relay RXQUE status information. The enabled version of these registers provides a version of the status register that is masked with the corresponding interrupt enable register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address 32 bits Clear/set (None) Read only (Enable 1 - 2) None Enable 1 Enable 2 Power on Value Restrictions None and enable 1 - 2 XXXX 1CA0 and CA4 1CB0 XXXX 1CB4 X'00000000' Only bits 26 down to 23 are writable. The RXQUE Enabled Status Registers are read only. Int 1 Status or PCORE Normal Int Status Int 2 Status or PCORE Critical Int Status Any Queue's Threshold Exceeded General Purpose Timer Status Event Latency Timer Expired Any Queue's Head Valid Reserved Any Queue Full/Empty Size of Dropped Event Event Dropped Reserved Reserved Status-Multiplexer Output for Queues 15-0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 Name General Purpose Timer Status 9 8 7 6 5 4 3 2 1 0 Description This is a mirror of the general purpose timer status bit in interrupt status. When read from the PCI bus, this bit indicates if there is status other than RXQUE staInt 1 Status or PCORE Normal Int tus and general purpose timer status in the [TBD] using [TBD] as a mask. When read Status from the PCORE polling interface, the mask used is the [TBD]. When read from the PCI bus, this bit indicates if there is status other than RXQUE staInt 2 Status or PCORE Critical Int tus and general purpose timer status in the [TBD] using [TBD] as a mask. When read Status from the PCORE polling interface, the mask used is the [TBD]. Reserved Sequence-Error in 64-Bit Register-Access Reserved Reserved When this bit is set, the event latency timer has expired. This indicates that new events are waiting to be processed on some queue(s) and the queue has not been processed for a period equal to the latency timer. This bit must be reset to re-enable the event latency timer. When this bit is set, at least one event has been dropped. RXQUE Last Event Dropped Register contains the event that was dropped. 29 28-27 26 25 Event Latency Timer Expired 24 Event Dropped Receive Queues (RXQUE) Page 398 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Name 0 32 bits 1 64 bits This bit does not generate interrupts. Reserved IBM Processor for Network Resources Description 23 22-19 18 17 16 15-0 Size of Dropped Event Reserved Any Queue's Head Valid Any Queue's Threshold Exceeded Any Queue Full/Empty 15-0: Status-Multiplexer Output for Reports either "Head Valid," "Threshold Exceeded," or "Queue Full/Empty" according Queues 15-0 to the setting of the Status-Multiplexer-Control field in the RXQUE Properties Register. pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 399 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.19: RXQUE Control Register Used to set RXQUE modes. See Note on Set/Clear Type Registers on page 93 for more details on addressing. This register contains the mode bits that specify how RXQUE is to operate. Length Type Address Power On Value Restrictions 32 bits Clear/Set XXXX 1C00 and C04 X'00000300' None Enable Chip Overflow Events Enable swap words on PCI Always Route Error Events Enable swap bytes on PCI Receive Bad Frames Assume 64-bit PCI Assume 32-bit PCI Timestamp Mode Inhibit Enqueues Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30-12 11 10 9 8 Reset FIFO Reserved Assume 64-bit PCI Assume 32-bit PCI Enable swap words on PCI Enable swap bytes on PCI This bit is automatically set at power-on. This bit is automatically set at power-on. Name 9 8 7 6 5 4 3 2 1 Description When this bit is set, the internal FIFO is flushed, and this bit is reset. The result is this bit will always be read as a '0'. This bit can only be set in diagnostic mode. Reserved. 7 Always route error events When this bit is set, all error events are routed to the error queue even if rx bad frames (bit2) is turned on. When cleared, error events are only routed to the error queue if rx bad frames is turned off. This bit allows the user to keep bad frames in time sequence with good frames or to route them to the error queue. The clear state of this bit is code compatible with previous versions of the processor. When set, the chip level counter overflow events are surfaced. When this bit is set, RXQUE will use Packet Memory instead of Control Memory to store the event queues. When this bit is set, the enq state machine will not accept any new enq requests. This should be used in extreme cases as it holds off all enqueues indefinitely. When this bit is set, timestamp events are inserted before each real event. The timestamps correspond to when the event happened on chip. When this bit is off, timestamps can still be read from the timestamp register. The timestamps would correspond to when the event was dequeued in this scenario. 6 5 4 Enable chip overflow events Memory select Inhibit enqueues 3 Timestamp mode Receive Queues (RXQUE) Page 400 of 676 pnr25.chapt05.01 August 14, 2000 Diagnostic Mode 0 BCACH Advice Memory Select Reset FIFO IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description When this bit is set, bad frame events (all error events), will be received in the normal rxq defined in the LCD. All buffers are not freed, and the packet address is raised in the event data. When this bit is reset, bad frame events are routed to the rxq specified by the Error Event Receive Queue Register. All packet based events will carry the LC address in the event data instead of the packet address. All buffers are freed back to POOLS. Note: This bit should only be changed sparingly because it changes the way packets are freed and what is surfaced in an event (LCD vs. frame ptr). It should really only be changed when the receive side is inactive. This bit, when set, allows RXQUE to give BCACH cache fill advice based on events that are dequeued. When this bit is set or when the chip is disabled, the RXQUE entity is in diagnostic mode and primitive execution is disabled. 2 Receive bad frames 1 0 BCACH advice Diagnostic mode Debugging Register Access This section is a very brief documentation of access that has been put in for the internal registers of RXQUE. These addresses need not be written or read during normal operations. 13.20: RXQUE RXQ State Machine Variable Register Main state variable for RXQUE processing state machine. Length Type Address Power On Value Restrictions 4 bits Read/Write XXXX 1E80 X'00000000' None 13.21: RXQUE RXQ ENQ State Machine Variable Register Main state variable for RXQUE processing state machine. Length Type Address Power On Value Restrictions 3 bits Read/Write XXXX 1E84 X'00000000' None pnr25.chapt05.01 August 14, 2000 Receive Queues (RXQUE) Page 401 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 13.22: RXQUE Enq FIFO Head Ptr Register Used to maintain the enqueue FIFO. Points to the head FIFO entry in the FIFO array. The MSB bit is used to determine if the head is chasing the tail, and is inverted each time the head pointer wraps. Length Type Address Power On Value Restrictions 5 bits Read/Write XXXX 1E88 X'00000000' Can only be written in diagnostic mode. 13.23: RXQUE Enq FIFO Tail Ptr Register Used to maintain the enqueue FIFO. Points to the next free FIFO entry in the FIFO array. The MSB bit is used to determine if the head is chasing the tail, and is inverted each time the tail pointer wraps. Length Type Address Power On Value Restrictions 5 bits Read/Write XXXX 1E8C X'00000000' Can only be written in diagnostic mode. 13.24: RXQUE Enq FIFO Array Holds events waiting to be placed on an rxq. Array is organized as a 16x36 array. To access the upper four bits of each word (holds the receive queue number for event), the array word number should be used as the address. To access the low order 32 bits (the event portion), the array word number times two plus four should be used. For example, address zero accesses the receive queue portion of array word zero, and address four accesses the event portion of the array word zero. Note: The most significant bit is not used. Only the three bits are needed for the receive queue number. Length Type Address Power On Value Restrictions 16 words X 36 bits Read/Write XXXX 1F00-FF8 X'00000000' Can only be read/written in diagnostic mode. When read in non-diagnostic mode, zero is returned. Receive Queues (RXQUE) Page 402 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PHY Level Interfaces Entity 14: The PHY Interface (LINKC) Functional Description LINKC provides the interface between the IBM3206K0424 and either an ATM PHY device or, when the internal framer is selected, a serializer/deserializer device. LINKC is composed of three pieces. LINKX, which contains all the registers described below, is clocked with the same clock as other parts of the chip. LINKT, the transmit logic, is clocked on the transmit clock, which is selected via the Clock Control Register (described in Clock Control Register (Nibble Aligned) on page 516). LINKR, the receive logic, is clocked on the receive clock, which is also selectable via the Clock Control Register. Transmit and receive transfers are synchronized via their respective interface transfer clock. The data path size is 8- or 16-bits wide and is selectable through bit 3 of the control register. The PHY devices that the IBM3206K0424 interfaces to are: * PMC SIERRA PM5346 SUNI LITE FOR SONET STS-3c 155.52 MB/s * UTOPIA 8 or 16 bit interface * PMC SIERRA POS-PHY New features added to LINKC are: * Multi-drop Utopia support * PMC SIERRA POS-PHY interface support Multi-Drop When the IBM3206K0424 is in multi-drop Utopia mode, it supports four external PHY devices. Each port is associated with a configuration. Four configurations are provided so up to four different types of PHYs can be connected to the IBM3206K0424. This allows the user to mix cell and POS-PHY devices on the transmit and/or receive interface. The multi drop PHY devices supported are Utopia Level 2 (cell based) and PMC Sierra POS-PHY (packet/frame based). The IBM3206K0424 will select which PHY device will transfer data next by polling each of the devices to determine which PHYs can transfer data. A round-robin switching scheme is used to determine which PHY has the priority if more then one wants to transmit/receive data. The IBM3206K0424 will switch to a new drop when a cell has been received/transmitted (for a cell-based PHY) or when 64 bytes or EOP has been received/transmitted (for POS-PHY PHYs). The transmit and receive sides of LINK are separately configurable for multi-drop mode (bits 1 and 0 of the global control register). POS-PHY The POS-PHY interface complies with the PMC Sierra POS-PHY Level 2 Specification. The IBM3206K0424 polls each POS-PHY device to determine its status on both the receive and transmit side. It looks to switch to a different port when 64 bytes or EOP (End of Packet) have been transferred between the POS-PHY and itself. The IBM3206K0424 does not support direct status indication or byte-level transfers. Therefore, the PHY must be programmed to always be able to send/receive at least 64 bytes of information. The RMOD signal will only be looked at when REOP is b'1'; at all other times it will be ignored. POS-PHY devices should be configured so that they will only signal they are ready for a transfer if they have 64 bytes free in their receive buffer and 64 bytes or EOP in their transmit FIFO. pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 403 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Moving Cells To and From the IBM3206K0424 Interface Utopia Cell Utopia Cell Utopia Cell Utopia Cell Utopia Cell Data Payload 48 48 48 48 48 Cell 52 53 54 55 56 Cycles for Eight-bit bus 52 53 54 55 56 Cycles for 16-bit bus 26 27 27 28 28 14.1: LINKC Global Control Register This register contains the information which controls the operation of LINKC. These controls affect all configurations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 32 bits Clear/Set XXXX 0B30 AND 34 X'C0000344' None Enable Transmit Side Watchdog Timer Overrride Standard Utopia Cell Length Enable Receive Side Watchdog Timer SERDES External Loopback Mode Transmit Phy Watchdog Timer Receive Phy Watchdog Timer Enable Transmit Multi-Drop 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 Name Enable LINKC Reserved 9 8 7 6 5 4 3 2 Description This bit, when set to '1' will enable LINKC. The default for this bit is '1'. Reserved. When this bit is set, the RX side is allowed to stall. This means that the IBM3206K0424 is allowed to park on a port until the port has data for the IBM3206K0424. This bit should be set if you are talking to a single drop POS-PHY device that doesn't have address pins and the IBM3206K0424 is being run in multi-drop mode. When this bit is set the EMPty signal will be ignored and it is always assumed the PHY has data. The default for this bit is '0'. When this bit is set the Full signal will be ignored and it is always assumed the PHY has room. The default for this bit is '0'. 29 Allow RX side to stall 28 27 Ignore RX Empty signal Ignore TX Full signal The PHY Interface (LINKC) Page 404 of 676 pnr25.chapt05.01 August 14, 2000 Enable Receive Multi-Drop 0 Disable Phy Bus Drivers Ignore Rx Empty Signal Allow Rx Side To Stall Always Transfer Cell Ignore Tx Full Signal Utopia Cell Length Loopback Mode Enable Linkc Reserved Reserved Reserved IBM3206K0424 Preliminary Bit(s) 26 25-21 23-20 Name Always Transfer cell Reserved Transmit PHY WatchDog Timer IBM Processor for Network Resources Description When this bit is set to '1', the TCA (transmit cell available) will be ignored until the current transfer ends. This mode is recommended when talking to a single drop Utopia device. The default for this bit is '0'. Reserved These four bits are the cycles the transmit side (LINKT) will wait before switching to another PHY. If the timer times out, a status bit in LINKC Interrupt/Status Register will be set for the offending PHY. These four bits are the cycles the receive side (LINKR) will wait before switching to another PHY. If the timer times out, a status bit in LINKC Interrupt/Status Register will be set for the offending PHY. This bit, when set to '1', causes LINKT to timeout if the PHY has started to take data but is now unable to take data for the number of cycles determined by the Transmit PHY Watchdog Timer (bits 23-20). The Timer is only valid if the transmit side is in multi-drop mode. This bit, when set to '1', causes LINKR to timeout if the PHY is receiving data and is unable to provide data for the number of cycles determined by the Receive PHY watchdog timer (bits 19-16). The timer is only valid if the receive side of LINKC is in multi-drop mode and the PHY is a Utopia device. This bit, when set to '1', tri-states the drivers of the PHY bus. When set to '0', the drivers are enabled. Reserved When this bit is set, the Receive Side SERDES input will be routed to the Transmit Side SERDES output. These seven bits will define what the Utopia cell length (in bytes) will be if the override standard utopia cell length bit (bit 3) is set to '1'. The upper limit of this register is 64 and the lower limit is one. The default value of these bits is x'0110100'. When this bit is set to '1', the standard utopia cell length (52 or 53 bytes) will be replaced by the value in bits 10-4. This bit will have no affect on PHYs that aren't Utopia and it will disable the HEC generation for any Utopia PHY. This bit set to '1' places the IBM3206K0424 in an internal loop back mode. The PHY interface will be disabled. The clocks to LINKT and LINKR should be set to the same source in the Clock Control Register. This bit is flushed to a '1' after POR. For loopback to work in multi-drop mode the transmit and receive configurations must be the same. When a configuration is set up for Utopia Cell-based transmission the receive and transmit sides should be identical in all ways. These include odd/even parity, data path length, 52-byte cell mode, null cell generation, and HEC generation of null cells. The additional header bytes should be set to '00' when in loopback mode. Please see the tableLegal Loopback Configurations on page 406. Setting this bit will put the transmit side into multi-drop mode. In multi-drop mode the IBM3206K0424 will support four configurations and four unique ports. This bit should not be set if the transmit side is connected to the Internal SONET Framer. Configuration 0 Transmit Control Register will control the transmit interface. If this bit is not set, the IBM3206K0424 is in single drop mode. Setting this bit will put the receive side into multi-drop mode. In multi-drop mode, the IBM3206K0424 will support four configurations and four unique PHY ports. This bit should not be set if the receive side is connected to the Internal SONET Framer. Configuration 0 Receive Control Register will control the receive interface. If this bit is not set, the IBM3206K0424 receive side is in single drop mode. 19-16 Receive PHY WatchDog Timer 15 Enable Transmit Side WatchDog Timer 14 Enable Receive Side WatchDog Timer 13 12 11 Disable PHY Bus Drivers Reserved SERDES External Loopback Mode Utopia Cell Length 10-4 3 Override Standard Utopia Cell Length 2 Loop back mode 1 Enable Transmit Multi-Drop 0 Enable Receive Multi-Drop pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 405 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Legal Loopback Configurations TX Config 0 SONET Utopia Cell Not Used Not Used Not Used Utopia Cell POS-PHY Not Used Not Used Not Used POS-PHY Utopia Cell POS-PHY POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell POS-PHY POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell RX Config 0 SONET Utopia Cell Not Used Not Used Not Used Utopia Cell POS-PHY Not Used Not Used Not Used POS-PHY Utopia Cell POS-PHY POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell POS-PHY POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell TX Config 1 Not Used Not Used Utopia Cell Not Used Not Used Utopia Cell Not Used POS-PHY Not Used Not Used POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell POS-PHY Utopia Cell Utopia Cell RX Config 1 Not Used Not Used Utopia Cell Not Used Not Used Utopia Cell Not Used POS-PHY Not Used Not Used POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell Utopia Cell Utopia Cell POS-PHY Utopia Cell Utopia Cell TX Config 2 Not Used Not Used Not Used Utopia Cell Not Used Utopia Cell Not Used Not Used POS-PHY Not Used POS-PHY POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY Utopia Cell POS-PHY Utopia Cell Utopia Cell POS-PHY Utopia Cell RX Config 2 Not Used Not Used Not Used Utopia Cell Not Used Utopia Cell Not Used Not Used POS-PHY Not Used POS-PHY POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY Utopia Cell POS-PHY Utopia Cell Utopia Cell POS-PHY Utopia Cell TX Config 3 Not Used Not Used Not Used Not Used Utopia Cell Utopia Cell Not Used Not Used Not Used POS-PHY POS-PHY POS-PHY POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY Utopia Cell Utopia Cell Utopia Cell Utopia Cell POS-PHY RX Config 3 Not Used Not Used Not Used Not Used Utopia Cell Utopia Cell Not Used Not Used Not Used POS-PHY POS-PHY POS-PHY POS-PHY POS-PHY Utopia Cell POS-PHY POS-PHY Utopia Cell POS-PHY Utopia Cell Utopia Cell Utopia Cell Utopia Cell POS-PHY The PHY Interface (LINKC) Page 406 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.2: LINKC Configuration 0 Transmit & Receive Control Register This register contains the information which controls the operation of Configuration 0 on the transmit and receive. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value 32 bits Clear/Set XXXX 0B50 and 0B54 X'78016E00' PMC PM5346 SUNI LITE/UTOPIA: 52 Byte Cell Disable HEC Generation on Transmitted Cells Disable HEC Generation on Transmitted Cells Modify byte alignment in 16-bit PHY mode Ignore GFC in Null/Idle Cell Determination Drive RENB Inactive When Not Receiving Unassigned/Idle Cell Reception Disable Limited HEC Checking # of Additional Header Bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 Description Bits 31, 30, and 29 indicates to which PHY the IBM3206K0424's Transmit Config 0 will be interfacing. If the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame-based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Internal SONET(sts-3c)/SDH(STM-1) Framer with SERDES (Serial interface) '111' Reserved Even parity is selected when this bit is cleared. The default value is for odd parity. Parity will always be generated when the IBM3206K0424 is transmitting data. If the PHY doesn't check parity, then don't connect the lines. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(1 -13) to be used for the 16-bit external Tx PHY device, while a '0' will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. Reserved. 31-29 PHY Transmit Device 28 Even/Odd Parity Selection 27 PHY Data Path Size 26-19 Reserved pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 407 of 676 Receive Extra Header Byte 0 Even/Odd Parity Selection Enable Parity Checking Gate RSOC with RCA PHY Transmit Device PHY Receive Device PHY Data Path Size PHY Data Path Size Enable XON/XOFF Parity on all 16 bits 16 bit parity Reserved Reserved Byte Cell IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description These bits indicate the number of additional header bytes that will be read from SEGBUF and added to the beginning of each cell as each is transmitted to the PHY. The bytes are meant to be used for additional routing information. These control bits have no affect in IBM 25 Mb/s PHY mode, and should be set to '0's when in internal SONET/SDH framer mode. If used in conjunction with 52-byte mode, the byte normally containing the cell HEC will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. If 16-bit PHY mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. As a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (LSB is normally padded with zeros so MSB gets truncated). Bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. When set to '1', this bit changes the default byte alignment in 16-bit PHY mode if this register also contains a non-zero value in bits 21-20. See the description of those bits for further details. Preliminary 21-20 Number of Additional Header Bytes 19 Modify byte alignment in 16-bit PHY mode 18-16 18 17 Bits 18-16 only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 31-29 = "011") is selected. If any other device is chosen, these bits will be ignored. 52 Byte Cell Disable HEC Generation on Transmitted Cells When set, the cell sent to the PHY will be 52 bytes. No HEC byte will be sent. If bit 17 is set to '1', X'00' will be placed in the HEC byte of Utopia cells. If bit 17 is set to '0', then the value of LINKC Transmitted HEC Control byte will be sent. If bit 18 is set to '1', then no HEC will be sent and this bit will be ignored. When set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. When set to '0', the IBM3206K0424 will produce two parity bits, one across generation and the lower half of the 16 bits (parity bit 0) and one against the upper (parity bit 1). The default for this bit is '1'. These bits indicate to which PHY the IBM3206K0424's Receive Config 0 will be interfacing. If the configuration's port address is all `1's, then the configuration is unused and the value of the above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame-based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Internal SONET (sts-3c)/SDH(STM-1) Framer with SERDES (Serial Interface) '111' Reserved When set, this bit will enable checking of parity on data from the receive path. The default is parity checking is disabled. The upper bit of the transmit parity is not valid when the internal SONET/SDH Framer has been selected as the receive PHY device. The upper bit of the receive parity is also not valid when the internal SONET/SDH Framer has been selected as the transmit PHY device. This is only a concern if a combination of the internal framer and an external PHY is being used and that external PHY has a 16-bit data interface. In this case, parity cannot be checked/generated on the upper byte. Even parity is selected when this bit is cleared. The default value is for odd parity. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. When this bit is set to '1' in 16-bit mode, parity will be calculated across all 16 bits and checked against FYRPAR(1). When in 8-bit mode with bit 9 set to '0', the parity will be compared against FYRPAR(1). This bit has no affect if receive device is POS-PHY. The default setting of this bit is '1'. 16 Parity on all 16 bits 15-13 PHY Receive Device 12 Enable Parity Checking 11 Even/Odd Parity Selection 10 PHY Data Path Size 9 16 bit parity The PHY Interface (LINKC) Page 408 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 8 7-0 7 6-5 6 Reserved Name Reserved IBM Processor for Network Resources Description Bits 7-0 only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 15-13 = "011") is selected. Otherwise, they are ignored. Bits 2-0 are used to make adjustments to the Utopia interface for compatibility with the Suni-PHD PHY. Byte Cell Reserved Unassigned/Idle Cell Reception When set, the cell received from the PHY will be 52 bytes. No HEC byte will be received. Reserved When set to '1', this bit will enable unassigned/idle cell reception. This should be set to '0' when using the internal SONET Framer. 5 If bit 5 is set to '1', the receive logic will ignore the HEC byte of the header of idle and unassigned cells. Idle is defined as a header of X'00000001' and unassigned is defined as a header of X'0000000n' where n is 'xxx0'. If bit 6 is set to enable unassigned/idle cell reception, all cells will be passed to REASM regardless of how this bit is set. If bit 6 is set to disable unassigned/idle cell reception and this bit is set to '0', the HEC byte of Disable Limited HEC Checking on cells with an apparent idle header will be completely checked before deciding whether Received Idle/Unassigned Cells or not to pass the cell to REASM. If a cell appears to have an unassigned header, HEC bits 7, 6, and 0 will be checked because they are a constant, regardless of the value of bits 3, 2, and 1 of the header. If other HEC bits are bad, REASM will detect the HEC error and discard the cell. If there is a correctable HEC error and the cell is indeed unassigned, an out of range error will occur in REASM. Ignore GFC in Null/Idle Cell Deter- Bit 4, when set, will cause the receive logic to ignore the first four bits of the ATM mination header in determining whether a cell being received is a null or idle cell. Enable XON/XOFF Drive RENB Inactive When Not Receiving Gate RSOC with RCA Receive Extra Header Byte Bit 3, when set, will allow the XON/XOFF bit of the header of a received cell to suspend/continue transmission from the IBM3206K0424's transmit logic for all ports associated with Config 0. When set to '1', this bit forces the receive logic to deactivate RENB when in the idle state. When set to '1', this bit forces the receive logic to see both RSOC and RCA before considering RSOC valid. When set to '1', this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. The extra byte is discarded. 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 409 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.3: LINKC Configuration 1 Transmit & Receive Control Register This register contains the information which controls the operation of Configuration 1 on the transmit and receive. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value 32 bits Clear/Set XXXX 0B58 AND 0B5C X'78016E00' PMC PM5346 SUNI LITE/UTOPIA: 52 Byte Cell Disable HEC Generation on Transmitted Cells Disable HEC Generation on Transmitted Cells Modify byte alignment in 16-bit PHY mode Ignore GFC in Null/Idle Cell Determination Drive RENB Inactive When Not Receiving Unassigned/Idle Cell Reception Disable Limited HEC Checking # of Additional Header Bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 Description Bits 31, 30, and 29 indicates to which PHY the IBM3206K0424's Transmit Config 1 will be interfacing. If the configuration's port address is all ones, then the configuration is unused and the value of the above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved Even parity is selected when this bit is cleared. The default value is for odd parity. Parity will always be generated when the IBM3206K0424 is transmitting data. If the PHY doesn't check parity, then don't connect the lines. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. Reserved 31-29 PHY Transmit Device 28 Even/Odd Parity Selection 27 PHY Data Path Size 26-19 Reserved The PHY Interface (LINKC) Page 410 of 676 pnr25.chapt05.01 August 14, 2000 Receive Extra Header Byte 0 Even/Odd Parity Selection Enable Parity Checking Gate RSOC with RCA PHY Transmit Device PHY Receive Device PHY Data Path Size PHY Data Path Size Enable XON/XOFF Parity on all 16 bits 16 bit parity Reserved Reserved Byte Cell IBM3206K0424 Preliminary Bit(s) 18-16 Name IBM Processor for Network Resources Description These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 31-29 = "011") is selected. If any other device is chosen these bits will be ignored. The value of bits 21-20 indicates the number of additional header bytes that will be read from SEGBUF and added to the beginning of each cell as each is transmitted to the PHY. The bytes are meant to be used for additional routing information. These control bits have no affect in IBM 25 Mb/s PHY mode, and should be set to '0's when in internal SONET/SDH framer mode. If used in conjunction with 52-byte mode, the byte normally containing the cell HEC will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. If 16-bit PHY mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. As a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (LSB is normally padded with zeros so MSB gets truncated). Bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. Modify byte alignment in 16-bit PHY mode 52 Byte Cell Disable HEC Generation on Transmitted Cells When set to '1', this bit changes the default byte alignment in 16-bit PHY mode if this register also contains a non-zero value in bits 21-20. See the description of those bits for further details. When set, the cell sent to the PHY will be 52 bytes. No HEC byte will be sent. If bit 17 is set to '1', X'00' will be placed in the HEC byte of Utopia cells. If bit 17 is set to '0', the value of LINKC Transmitted HEC Control byte will be sent. If bit 18 is set to '1', then no HEC will be sent and this bit will be ignored. When set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. When set to '0', the IBM3206K0424 produces two parity bits, one across generation and the lower half of the 16 bits (parity bit zero) and one against the upper (parity bit 1). The default for this bit is '1'. Bits 15, 14, and 13 indicate which PHY the IBM3206K0424's Receive Config 1 will be interfacing. If the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved When set, this bit enables checking of parity on data from the receive path. The default parity checking is disabled. The upper bit of the transmit parity is not valid when the internal SONET/SDH Framer has been selected as the receive PHY device. The upper bit of the receive parity is also not valid when the internal SONET/SDH Framer has been selected as the transmit PHY device. This is only a concern if a combination of the internal framer and an external PHY is being used and that external PHY has a 16-bit data interface. In this case, parity cannot be checked/generated on the upper byte. Even parity is selected when this bit is cleared. The default value is for odd parity. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY is eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. When this bit is set to '1' and it is in 16-bit mode, that parity will be calculated across all 16 bits and checked against FYRPAR(1). When in eight-bit mode with bit 9 set to '0', the parity will be compared against FYRPAR(1). This bit has no affect if the receive device is POS-PHY. The default setting of this bit is '1'. 21-20 19 18 17 16 Parity on all 16 bits 15-13 PHY Receive Device 12 Enable Parity Checking 11 Even/Odd Parity Selection 10 PHY Data Path Size 9 16 bit parity pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 411 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 8 7-0 7 6-5 6 Reserved Name Reserved Description Preliminary Bits 7-0 only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 15-13 = "011") is selected. Otherwise, these bits will be ignored. Bits 2-0 are used to make adjustments to the Utopia interface for compatibility with the Suni-PHD PHY. 52 Byte Cell Reserved Unassigned/Idle Cell Reception When set, the cell received from the PHY is 52 bytes. No HEC byte will be received. Reserved When set to '1', this bit will enable unassigned/idle cell reception. This should be set to '0' when using the internal SONET Framer. 5 If bit 5 is set to '1', the receive logic will ignore the HEC byte of the header of idle and unassigned cells. Idle is defined as a header of X'00000001' and unassigned is defined as a header of X'0000000n' where n is 'xxx0'. If bit 6 is set to enable unassigned/idle cell reception, all cells are passed to REASM regardless of how this bit is set. If bit 6 is set to disable unassigned/idle cell reception Disable Limited HEC Checking on and this bit is set to '0', the HEC byte of cells with an apparent idle header will be comReceived Idle/Unassigned Cells pletely checked before deciding whether or not to pass the cell to REASM. If a cell appears to have an unassigned header, HEC bits seven, six, and zero will be checked because they are a constant regardless of the value of bits 3-1 of the header. If other HEC bits are bad, REASM will detect the HEC error and discard the cell. If there is a correctable HEC error and the cell is indeed unassigned, an out of range error will occur in REASM. Ignore GFC in Null/Idle Cell Deter- Bit 4, when set, will cause the receive logic to ignore the first four bits of the ATM mination header in determining whether a cell being received is a null or idle cell. Enable XON/XOFF Drive RENB Inactive When Not Receiving Gate RSOC with RCA Receive Extra Header Byte Bit 3, when set, will allow the XON/XOFF bit of the header of a received cell to suspend/continue transmission from the IBM3206K0424's transmit logic for all ports associated with Config 1. When set to '1', this bit forces the receive logic to deactivate RENB when in the idle state. When set to '1', this bit forces the receive logic to see both RSOC and RCA before considering RSOC valid. When set to '1', this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. The extra byte is discarded. 4 3 2 1 0 The PHY Interface (LINKC) Page 412 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.4: LINKC Configuration 2 Transmit & Receive Control Register This register contains the information which controls the operation of configuration 2 on the transmit and receive. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions PMC PM5346 SUNI LITE/UTOPIA: 52 Byte Cell 32 bits Clear/Set XXXX 0B60 AND 0B64 X'78016E00' Disable HEC Generation on Transmitted Cells Disable HEC Generation on Transmitted Cells Ignore GFC in Null/Idle Cell Determination Modify byte alignment in 16-bit PHY mode Drive RENB Inactive When Not Receiving Unassigned/Idle Cell Reception Disable Limited HEC Checking # of Additional Header Bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 Description Bits 31, 30, and 29 indicate which PHY the IBM3206K0424's Transmit Config 2 will be interfacing. If the configuration's port address is all ones then the configuration is unused and the value above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved Even parity is selected when this bit is cleared. The default value is for odd parity. Parity will always be generated when the IBM3206K0424 is transmitting data. If the PHY doesn't check parity then don't connect the lines. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit allows FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero allows FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. 31-29 PHY Transmit Device 28 Even/Odd Parity Selection 27 PHY Data Path Size pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 413 of 676 Receive Extra Header Byte 0 Even/Odd Parity Selection Enable Parity Checking Gate RSOC with RCA PHY Transmit Device PHY Receive Device PHY Data Path Size PHY Data Path Size Enable XON/XOFF Parity on all 16 bits 16 bit parity Reserved Reserved Byte Cell IBM3206K0424 IBM Processor for Network Resources Bit(s) 26-19 18-16 Reserved Name Reserved Description Preliminary These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 31-29 = "011") is selected. If any other device is chosen these bits will be ignored. The value of bits 21-20 indicate the number of additional header bytes that will be read from SEGBUF and added to the beginning of each cell as each is transmitted to the PHY. The bytes are meant to be used for additional routing information. These control bits have no affect in IBM 25 Mb/s PHY mode, and should be set to '0's when in internal SONET/SDH framer mode. If used in conjunction with 52-byte mode, the byte normally containing the cell HEC will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. If 16-bit PHY mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. As a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (LSB is normally padded with zeros so MSB gets truncated). Bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. Modify byte alignment in 16-bit PHY mode 52 Byte Cell Disable HEC Generation on Transmitted Cells When set to '1', this bit changes the default byte alignment in 16-bit PHY mode if this register also contains a non-zero value in bits 21-20. See the description of those bits for further details. When set, the cell sent to the PHY is 52 bytes. No HEC byte will be sent. If bit 17 is set to '1', X'00' will be placed in the HEC byte of Utopia cells. If bit17 is set to '0', the value of LINKC Transmitted HEC Control byte will be sent. If bit18 is set to '1', then no HEC is sent and this bit will be ignored. When set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. When set to `0', the IBM3206K0424 will produce two parity bits, one across generation and the lower half of the 16 bits (parity bit zero) and one against the upper (parity bit 1). The default for this bit is '1'. Bits 15, 14, and 13 indicate which PHY the IBM3206K0424's Receive Config 2 will be interfacing. If the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved When set, this bit will enable checking of parity on data from the receive path. The default parity checking is disabled. The upper bit of the transmit parity is not valid when the internal SONET/SDH Framer has been selected as the receive PHY device. The upper bit of the receive parity is also not valid when the internal SONET/SDH Framer has been selected as the transmit PHY device. This is only a concern if a combination of the internal framer and an external PHY is being used and that external PHY has a 16-bit data interface. In this case, parity cannot be checked/generated on the upper byte. Even parity is selected when this bit is cleared. The default value is for odd parity. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero allows FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. 21-20 19 18 17 16 Parity on all 16 bits 15-13 PHY Receive Device 12 Enable Parity Checking 11 Even/Odd Parity Selection 10 PHY Data Path Size The PHY Interface (LINKC) Page 414 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description When this bit is set to '1' and it is in 16-bit mode, that parity will be calculated across all 16 bits and check against FYRPAR(1). When in eight-bit mode with bit 9 set to '0', the parity will be compared against FYRPAR(1). This bit has no affect if receive device is POS-PHY. The default setting of this bit is '1'. Reserved 9 16 bit parity 8 7-0 7 6-4 6 Reserved These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 15-13 = "011") is selected. If any other device is chosen, these bits are ignored. Bits two through zero are used to make adjustments to the Utopia interface for compatibility with the Suni-PHD PHY. 52 Byte Cell Reserved Unassigned/Idle Cell Reception When set, the cell received from the PHY is 52 bytes. No HEC byte is received. Reserved When set to '1', this bit will enable unassigned/idle cell reception. This should be set to '0' when using the internal SONET Framer. 5 If bit 5 is set to '1', the receive logic will ignore the HEC byte of the header of idle and unassigned cells. Idle is defined as a header of X'00000001' and unassigned is defined as a header of X'0000000n' where n is 'xxx0'. If bit 6 is set to enable unassigned/idle cell reception, all cells are passed to REASM regardless of how this bit is set. If bit 6 is set to disable unassigned/idle cell reception Disable Limited HEC Checking on and this bit is set to '0', the HEC byte of cells with an apparent idle header will be comReceived Idle/Unassigned Cells pletely checked before deciding whether or not to pass the cell to REASM. If a cell appears to have an unassigned header, HEC bits seven, six, and zero will be checked because they are a constant regardless of the value of bits 3-1 of the header. If other HEC bits are bad, REASM will detect the HEC error and discard the cell. If there is a correctable HEC error and the cell is indeed unassigned, an out of range error will occur in REASM. Ignore GFC in Null/Idle Cell Deter- Bit 4, when set, causes the receive logic to ignore the first four bits of the ATM header mination in determining whether a cell being received is a null or idle cell. Enable XON/XOFF Drive RENB Inactive When Not Receiving Gate RSOC with RCA Receive Extra Header Byte Bit 3, when set, allows the XON/XOFF bit of the header of a received cell to suspend/continue transmission from the IBM3206K0424's transmit logic for all ports associated with Config 2. When set to '1', this bit forces the receive logic to deactivate RENB when in the idle state. When set to '1', this bit forces the receive logic to see both RSOC and RCA before considering RSOC valid. When set to '1', this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. The extra byte is discarded. 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 415 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.5: LINKC Configuration 3 Transmit & Receive Control Register This register contains the information which controls the operation of configuration 3 on the transmit and receive. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions PMC PM5346 SUNI LITE/UTOPIA: 52 Byte Cell 32 bits Clear/Set XXXX 0B68 AND 0B6C X'78016E00' Disable HEC Generation on Transmitted Cells Disable HEC Generation on Transmitted Cells Ignore GFC in Null/Idle Cell Determination Modify byte alignment in 16-bit PHY mode Drive RENB Inactive When Not Receiving Unassigned/Idle Cell Reception Disable Limited HEC Checking # of Additional Header Bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 Description Bits 31, 30, and 29 indicate to which PHY the IBM3206K0424's Transmit Config 3 will be interfacing. If the configuration's port address is all ones then the configuration is unused and the value of the above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved Even parity is selected when this bit is cleared. The default value is for Odd parity. Parity will always be generated when the IBM3206K0424 is transmitting data. If the PHY doesn't check parity then don't connect the lines. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. 31-29 PHY Transmit Device 28 Even/Odd Parity Selection 27 PHY Data Path Size The PHY Interface (LINKC) Page 416 of 676 pnr25.chapt05.01 August 14, 2000 Receive Extra Header Byte 0 Even/Odd Parity Selection Enable Parity Checking Gate RSOC with RCA PHY Transmit Device PHY Receive Device PHY Data Path Size PHY Data Path Size Enable XON/XOFF Parity on all 16 bits 16 bit parity Reserved Reserved Byte Cell IBM3206K0424 Preliminary Bit(s) 26-19 Reserved Name Reserved The value of bits 21-20 indicate the number of additional header bytes that will be read from SEGBUF and added to the beginning of each cell as each is transmitted to the PHY. The bytes are meant to be used for additional routing information. These control bits have no affect in IBM 25 Mb/s PHY mode, and should be set to '0's when in internal SONET/SDH framer mode. If used in conjunction with 52-byte mode, the byte normally containing the cell HEC will not be transmitted and the total number of cells transmitted will be the value of this field plus 52. If 16-bit PHY mode is selected, by default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with the additional header bytes contiguously prepended. As a result, a mode with three additional header bytes cannot be obtained in 53-byte, 16-bit mode (LSB is normally padded with zeros so MSB gets truncated). Bit 3 of this register is therefore provided to adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted with up to three additional router bytes prepended. Modify byte alignment in 16-bit PHY mode When set to '1', this bit changes the default byte alignment in 16-bit PHY mode if this register also contains a non-zero value in bits 21-20. See the description of those bits for further details. IBM Processor for Network Resources Description 21-20 19 18-16 18 17 These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 31-29 = "011") is selected. If any other device is chosen these bits will be ignored. 52 Byte Cell Disable HEC Generation on Transmitted Cells When set, the cell sent to the PHY is 52 bytes. No HEC byte will be sent. If bit 17 is set to '1', X'00' will be placed in the HEC byte of Utopia cells. If bit 17 is set to '0', the value of LINKC Transmitted HEC Control byte will be sent. If bit 18 is set to '1', no HEC is sent and this bit will be ignored. When set, this bit enables the IBM3206K0424 to produce a single parity bit across the 16-bit transmit data bus. When set, the IBM3206K0424 produces two parity bits, one across generation and the lower half of the 16 bits (parity bit 0) and one against the upper (parity bit 1). The default for this bit is '1'. Bits 15, 14, and 13 indicate to which PHY the IBM3206K0424's Receive Config 3 will be interfacing. If the configuration's port address is all ones, then the configuration is unused and the value above bits doesn't matter. '000' Reserved '001' PMC POS-PHY (Frame based Utopia) '010' Reserved '011' PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1) '100' Reserved '101' Reserved '111' Reserved When set, this bit enables checking of parity on data from the receive path. The default parity checking is disabled. The upper bit of the transmit parity is not valid when the internal SONET/SDH Framer has been selected as the receive PHY device. The upper bit of the receive parity is also not valid when the internal SONET/SDH Framer has been selected as the transmit PHY device. This is only a concern if a combination of the internal framer and an external PHY is being used and that external PHY has a 16-bit data interface. In this case, parity cannot be checked/generated on the upper byte. Even parity is selected when this bit is cleared. The default value is for odd parity. This bit, when set to '0', selects a 16-bit wide data path to the PHY device. When set to '1', the data path width to the PHY will be eight bits. This bit has no affect on the internal SONET/SDH framer except if the internal framer has been selected as the Rx PHY device but not as the Tx PHY device. In this case, a '1' on this bit will allow FYTDAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possible to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX framer at the same time. 16 Parity on all 16 bits 15-13 PHY Receive Device 12 Enable Parity Checking 11 Even/Odd Parity Selection 10 PHY Data Path Size pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 417 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description When this bit is set to '1' and it is in 16-bit mode, that parity will be calculated across all 16 bits and checked against FYRPAR(1). When in eight-bit mode with bit 9 set to '0', the parity is compared against FYRPAR(1). This bit has no affect if receive device is POS-PHY. The default setting of this bit is '1'. Reserved Preliminary 9 16 bit parity 8 7-0 7 6-4 6 Reserved These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 15-13 = "011") is selected. If any other device is chosen, these bits are ignored. Bits 2-0 are used to make adjustments to the Utopia interface for compatibility with the Suni-PHD PHY. 52 Byte Cell Reserved Unassigned/Idle Cell Reception When set, the cell received from the PHY is 52 bytes. No HEC byte will be received. Reserved When set to '1', this bit will enable unassigned/idle cell reception. This should be set to '0' when using the internal SONET Framer. 5 If bit 5 is set to '1', the receive logic will ignore the HEC byte of the header of idle and unassigned cells. Idle is defined as a header of X'00000001' and unassigned is defined as a header of X'0000000n' where n is B'xxx0'. If bit 6 is set to enable unassigned/idle cell reception, all cells are passed to REASM Disable Limited HEC Checking on regardless of how this bit is set. If bit 6 is set to disable unassigned/idle cell reception and this bit is set to '0', the HEC byte of cells with an apparent idle header will be comReceived Idle/Unassigned Cells pletely checked before deciding whether or not to pass the cell to REASM. If a cell appears to have an unassigned header, HEC bits 7, 6, and 0 are checked because they are a constant regardless of the value of bits 3-1 of the header. If other HEC bits are bad, REASM detects the HEC error and discards the cell. If there is a correctable HEC error and the cell is indeed unassigned, an out of range error occurs in REASM. Ignore GFC in Null/Idle Cell Deter- Bit 4, when set, causes the receive logic to ignore the first four bits of the ATM header mination in determining whether a cell being received is a null or idle cell. Enable XON/XOFF Drive RENB Inactive When Not Receiving Gate RSOC with RCA Receive Extra Header Byte Bit 3, when set, allows the XON/XOFF bit of the header of a received cell to suspend/continue transmission from the IBM3206K0424's transmit logic for all ports associated with Config 3. When set to '1', this bit forces the receive logic to deactivate RENB when in the idle state. When set to '1', this bit forces the receive logic to see both RSOC and RCA before considering RSOC valid. When set to '1', this bit allows an extra header byte to be accepted at the start of a cell by the receive logic. The extra byte is discarded. 4 3 2 1 0 The PHY Interface (LINKC) Page 418 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.6: LINKC Map Transmit Configurations to Port Addresses This register contains the port address for each of the transmit configurations. If the port address is B"11111" then the configuration is unused. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Port Address for Configuration 3 32 bits Clear/Set XXXX 0B70 AND 0B74 X'1F1F1F1F' None Port Address for Configuration 2 Port Address for Configuration 1 Port Address for Configuration 0 Reserved Reserved Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-29 28-24 23-21 20-16 15-13 12-8 7-5 4-0 Reserved Port Address for Configuration 3. Reserved Port Address for Configuration 2. Reserved Port Address for Configuration 1. Reserved Port Address for Configuration 0. Description 9 8 7 6 5 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 419 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.7: LINKC Map Receive Configurations to Port Addresses This register contains the port address for each of the receive configurations. If the port address is "11111" then the configuration is unused. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Port Address for Configuration 3 32 bits Clear/Set XXXX 0B80 AND 0B84 X'1F1F1F1F' None Port Address for Configuration 2 Port Address for Configuration 1 Port Address for Configuration 0 Reserved Reserved Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-29 28-24 23-21 20-16 15-13 12-8 7-5 4-0 Reserved. Port Address for Configuration 3. Reserved Port Address for Configuration 2. Reserved Port Address for Configuration 1. Reserved Port Address for Configuration 0. Description 9 8 7 6 5 4 3 2 1 0 The PHY Interface (LINKC) Page 420 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.8: LINKC Transmitted HEC Control Byte When the IBM3206K0424 is transmitting to a 53-byte Utopia PHY the HEC byte (byte five of the ATM header) will be sent as x'00', if bit 17 of the transmitting configuration is a '1'. Otherwise the value of the LINKC Transmitted HEC Control Byte Register will be sent. Length Type Address Power On Value Restrictions HEC Byte Value 8 bits Read/Write XXXX 0B04 X'00' None 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Value of the HEC byte to be sent when talking to a 53-byte Utopia PHY. pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 421 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.9: LINKC Interrupt/Status Register This register reports the status of LINKC. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions C3: Two SOP without an EOP 32 bits Clear/Set XXXX 0B10 AND 14 X'00' None C2: Two SOP without an EOP C1: Two SOP without an EOP C0: Two SOP without an EOP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 25-24 23 22 21 20 19 18 17-16 15 14 13 Description 9 8 7 6 5 4 3 2 1 Indicates that Config 3 has seen two SOP in a 64-byte boundary without an EOP. Multiple SOP outside the 64-byte boundary will be passed up, and it's up to the higher levels to deal with this case. Indicates that Config 3 has received a null cell. Indicates a parity error on the upper byte of receive data from the Config 3 PHY. Indicates a parity error on the lower byte of receive data from the Config 3 PHY. Indicates Config 3's receive PHY has stalled out. Indicates Config 3's transmit PHY has stalled out. Reserved Indicates that Config 2 has seen two SOP in a 64-byte boundary without an EOP. Multiple SOP outside the 64-byte boundary will be passed up, and it's up to the higher levels to deal with this case. Indicates that Config 2 has received a null cell. Indicates a parity error on the upper byte of receive data from the Config 2 PHY. Indicates a parity error on the lower byte of receive data from the Config 2 PHY. Indicates Config 2's receive PHY has stalled out. Indicates Config 2's transmit PHY has stalled out. Reserved Indicates that Config 1 has seen two SOP in a 64-byte boundary without an EOP. Multiple SOP outside the 64 byte boundary will be passed up, and it's up to the higher levels to deal with this case. Indicates that Config 1 has received a null cell. Indicates a parity error on the upper byte of receive data from the Config 1 PHY. The PHY Interface (LINKC) Page 422 of 676 pnr25.chapt05.01 August 14, 2000 No Carrier Detect from PHY. 0 C3: Upper Byte Parity Error C3: Lower Byte Parity Error C2: Upper Byte Parity Error C2: Lower Byte Parity Error C1: Upper Byte Parity Error C1: Lower Byte Parity Error C0: Upper Byte Parity Error C0: Lower Byte Parity Error C3: Transmit PHY Stalled C2: Transmit PHY Stalled C1: Transmit PHY Stalled C0: Transmit PHY Stalled C3: Receive PHY Stalled C2: Receive PHY Stalled C1: Receive PHY Stalled C0: Receive PHY Stalled REASM FIFO Overrun C3: Null Cell C2: Null Cell C1: Null Cell C0: Null Cell Reserved Reserved Reserved IBM3206K0424 Preliminary Bit(s) 12 11 10 9-8 7 6 5 4 3 2 1 0 Description Indicates a parity error on the lower byte of receive data from the Config 1 PHY. Indicates Config 1's receive PHY has stalled out. Indicates Config 1's transmit PHY has stalled out. Reserved Indicates that Config 0 has seen two SOP in a 64-byte boundary without an EOP. Multiple SOP outside the 64 byte boundary will be passed up, and it's up to the higher levels to deal with this case. Indicates that Config 0 has received a null cell. Indicates a parity error on the upper byte of receive data from the Config 0 PHY. Indicates a parity error on the lower byte of receive data from the Config 0 PHY. Indicates Config 0's receive PHY has stalled out. Indicates Config 0's transmit PHY has stalled out. REASM FIFO has been overrun. No carrier detect from the PHY. IBM Processor for Network Resources pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 423 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.10: LINKC Interrupt Enable Register This register enables the LINKC interrupt to INTST. When a bit is set in this register and the corresponding bit is set in the Interrupt Status Register, the LINKC interrupt will be driven. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See the LINKC Interrupt/Status Register on page 422 for the bitwise description of this register. Length Type Address Power On Value Restrictions 8 bits Clear/Set XXXX 0B18 AND 1C X'00' None 14.11: LINKC Prioritized Interrupts Used to access the prioritized encoding of LINKC interrupts. Reading this location will give a decimal number that is the prioritized encoding of bits 7-0 in COMET/PAKIT Status Register (seven being the most significant bit) assuming the corresponding enable bit is on. Length Type Address Power On Value Restrictions 8 bits Read XXXX 0B2C X'00' None The PHY Interface (LINKC) Page 424 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.12: LINKC Transmit State Machine Register This register indicates the state of the transmit sequencer. Length Type Address Power On Value Restrictions Unassigned Transmit 6 bits Read/Write XXXX 0B24 X'0' None 5 4 Bit(s) 5-3 2-0 3 2 1 0 Description Unassigned cell state machine. Transmit state machine. 14.13: LINKC Receive State Machine Register This register indicates the state of the receiver sequencer. Length Type Address Power On Value Restrictions 2 bits Read/Write XXXX 0B28 X'0' None Bit(s) 1-0 Receive state machine. Description pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 425 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 14.14: LINKC LAN Address Register If using an IBM built adapter that utilizes CRISCO, this register contains the ROM level in bits 63-48 and the LAN address of the adapter in bits 47-0. The lower address selects bits 63-32 and the higher address selects bits 31-0. Length Type Address Power On Value Restrictions 64 bits Write/Read XXXX 0B38 AND 3C X'AAAA55555555AAAA' None 14.15: LINKC Canonical LAN Address Register This register contains the same data as the LINKC LAN Address Register except each byte is bit reversed. This allows the user to obtain the LAN address in canonical format. Length Type Address Power On Value Restrictions 64 bits Read XXXX 0B08 AND 0C X'5555AAAAAAAA5555' None The PHY Interface (LINKC) Page 426 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 14.16: LINKC Passed TX Data Register The bits in this register are passed over PHY transmit data I/O 15-8 when using an eight bit wide PHY data bus. Length Type Address Power On Value Restrictions 8 bits Read/Write XXXX 0B40 X'00' None Bit(s) Name Description Pass to I/O line FYTDAT(15 down to 8), except in the case of the internal SONET/SDH framer. When the internal SONET/SDH framer is selected as the Rx PHY device, signals FYTDAT(15 down to 13) are used as the Rx HDLC interface, unless a 16-bit wide external Tx PHY is also selected, then they are used as data lines. 7-0 Passed to FYTDAT(15 down to 8) pnr25.chapt05.01 August 14, 2000 The PHY Interface (LINKC) Page 427 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 15: Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data This entity controls the signals of the NPBUS. The PHY registers are accessible to the processor by way of the address space of the IBM3206K0424. In addition, the operation of the front end is affected by the NPBUS Status Register. This entity also contains the CRISCO processor which can initialize chip registers at boot time by reading a data stream from EPROM which specifies the address of registers and data values to which the registers are to be initialized. In general, the data stream consists of a series of single-byte instruction operation codes, followed by an address and data values. 15.1: NPBUS Control Register This register is used to report PHY level hardware errors and interrupts. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 29 bits Clear/Set XXXX 2000 and 004 X'0002010' None Remove Internal SONET Framer from reset state Access Internal SONET Framer register space Enable Hardware Error to Disable PHY Enable PHY Data Bus Parity Detection Invert Interrupt Inputs and PHY reset Disable driving the NP address over the ENSTATE(47 - 32) pins Enable PHY Addr/Data Multiplexing Reboot serial/parallel EPROM +UTP/-STP Interface Select Enable Carrier Detect LED PHY Bus Interface Type Force a PHY logic reset External EPROM Type 2 1 Status LED 4 Flashing Status LED 3 Flashing Status LED 2 Flashing Status LED 1 Flashing Status LED 4 Toggle Status LED 3 Toggle Status LED 2 Toggle Status LED 1 Toggle Enable the front end PB0PHY2 Control Status LED 4 On Status LED 3 On Status LED 2 On Status LED 1 On 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Bit(s) Name 14 13 12 11 10 9 8 7 6 5 4 3 Description 28 This bit set to '1' will enable the ALE1, ALE2, and ALE3 control lines for PHY and ParEnable PHY Addr/Data multiplex- allel EPROM accesses so that additional address bytes can be latched for up to ing 24Meg of addressing. Since there is an access speed penalty for this, the default is a '0' for this function. Status LED 4 Toggle When this bit is set, the state of bit 19 of this register will be toggled by repeatedly setting bit 19. 27 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data pnr25.chapt05.01 August 14, 2000 Page 428 of 676 Reserved 0 IBM3206K0424 Preliminary Bit(s) 26 25 24 23 22 21 20 19 18 17 16 15 Name Status LED 3 Toggle Status LED 2 Toggle Status LED 1 Toggle Status LED 4 Flashing Status LED 3 Flashing Status LED 2 Flashing Status LED 1 Flashing Status LED 4 On Status LED 3 On Status LED 2 On Status LED 1 On +UTP/-STP Interface Select Disable driving the NP address over the ENSTATE(47 - 32) pins Enable Carrier Detect LED Enable PHY Data Bus Parity Detection Enable 16 data bit mode for PHY reg accesses IBM Processor for Network Resources Description When this bit is set, the state of bit 18 of this register will be toggled by repeatedly setting bit 18. When this bit is set, the state of bit 17 of this register will be toggled by repeatedly setting bit 17. When this bit is set, the state of bit 16 of this register will be toggled by repeatedly setting bit 16. When set to '1', this bit will flash status indicator LED 4. Bit 19 of the register will override this bit. When set to '1', this bit will flash status indicator LED 3. Bit 18 of the register will override this bit. When set to '1', this bit will flash status indicator LED 2. Bit 17 of the register will override this bit. When set to '1', this bit will flash status indicator LED 1. Bit 16 of the register will override this bit. When set to '1', this bit will turn on status indicator LED 4. When set to '1', this bit will turn on status indicator LED 3. When set to '1', this bit will turn on status indicator LED 2. When set to '1', this bit will turn on status indicator LED 1. This bit controls a chip output pin to switch high or low and can be used to select different PHY interfaces, etc. When this bit is off, or a logical `0', the chip output is high, or a logical `1'. For debug reasons, the driven of the address for EPROM and PHY fetches can be turned off with this bit. When set to '1', this bit allow indicator LED 1 to reflect the status of Carrier Detect. This is a chip input. When set to '1', if a parity error occurs on the PHY Data bus during a PHY register access, bit 1 of the NPBUS Status Register will be set. When this bit is '1', the upper eight bits of a 16-bit PHY data (bits 15-8) bus will be transferred over 47- 40 bits of the ENSTATE chip I/O bus. 14 13 12 11 10 When this bit is '0', the external PHY register space can be accessed through PHY 1 Registers or PHY 2 Registers. Also, the SONET Framer register space can be accessed through the EPROM access registers, NPBUS EPROM Address/Command Access Internal SONET Framer Register and NPBUS EPROM Data Register. By providing the byte framer address register space in memory mapped (see Sonet Framer Core (FRAMR Chiplet Address Mapping) on page 525) in the mode NPBUS EPROM Address/Command Register, the byte data can be read or written from the NPBUS EPROM Data Register. When this bit is set to '1', the internal SONET framer registers can be accessed (see Sonet Framer Core (FRAMR Chiplet Address Mapping) on page 525). The full offset range for this access is X'2100' to X'2FFF'. PHY Bus Interface Type When this bit is '0', PHY access speed is 200 ns (SUNI-like interface). When a '1', access requires an acknowledge input response. This is to support a UTOPIA-like micro-processor interface. Allows bit 4 (Master enable) of the INTST Control Register to reset bit 4 of this register (Disables Front End logic). This function assumes that bit 4 of the INTST Control Register has already been enabled and that either a hardware or software event has turned the bit off. This bit will restart the external serial or parallel EPROM initialization code. This bit powers up to a zero and keeps the internal SONET Framer in reset mode. Setting this bit to a 1 will enable normal operation. 9 8 Enable Hardware Error to Disable PHY Reboot serial/parallel EPROM Remove Internal SONET Framer from reset state 7 6 pnr25.chapt05.01 August 14, 2000 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data Page 429 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) Name Description Force a PHY logic reset. Before any software reset, turn this bit on and off for the PHY specified amount of time. If the IBM ATM-TC (25 Mbps ENDEC) is used, this bit will power-up to an active reset (since the input to the ENDEC is positive reset). This bit must then be turned off for normal operation. Enable the front end. When this bit is '0', no data will be transmitted to or received from the PHYs or the IBM3206K0424. See bit 8 for more information on control of this bit. Encoded control for the PB0PHY2 output pin. The enabled of PIBSELO overrides these bits and is controlled by PCINT Cascade Control Register. X'0' Enable PB0PHY2 pin X'1' Enable PBDATAP pin and its detection of valid parity. X'2' Enable MPMDSEL pin X'3' Reserved This bit will set at reset time as to what type of EPROM is detected. When set, a serial EPROM has been detected. When a '0', parallel EPROM is assumed (or none at all). This will also indicate from what type of device a PCI ROM access will retrieve VPD data. When set to '1', this bit is used for speeding up sim time for the serial EPROM. It will change the time period for the serial EPROM clock from 10 s to 85 ns. Preliminary 5 Do PHY Reset 4 Enable 3-2 PB0PHY2 Control 1 External EPROM Type 0 Reduce Serial EPROM clock Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data pnr25.chapt05.01 August 14, 2000 Page 430 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources 15.2: NPBUS Status Register This register is used to report PHY level hardware errors and interrupts. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions Parallel EPROM Access Complete 7 bits Clear/Set XXXX 2028 and 02C X'x1', where x is determined by which type of CRISCO IPL EPROM is used None Serial EPROM Access Complete Internal SONET Framer interrupt 6 5 Bit(s) 6 4 3 2 1 CRISCO Execution Complete 0 Name Description The requested action to the parallel EPROM has been completed. (See NPBUS EPROM Address/Command Register on page 433). The requested action to the serial EPROM has missed an acknowledge sequence while trying to complete the action. (See NPBUS EPROM Address/Command Register on page 433). The requested action to the serial EPROM has been completed. (See NPBUS EPROM Address/Command Register on page 433). The internal Framer has signaled an interrupt. This bit indicates that an interrupt occurred on PHY 1. When set to '1', a data parity was detected over the PHY Data eight-bit bus. Parity checked is odd. External serial/parallel EPROM initialization has run and is completed. Serial EPROM Access Failed Parallel EPROM Access Complete 5 Serial EPROM Access Failed 4 3 2 1 0 Serial EPROM Access Complete Internal SONET Framer interrupt Interrupt PHY1 PHY Data Bus Parity Error CRISCO Execution Complete pnr25.chapt05.01 August 14, 2000 PHY Data Bus Parity Error Interrupt PHY1 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data Page 431 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 15.3: NPBUS Interrupt Enable Register This register is used to mask bits from the NPBUS Status Register and potentially generate interrupts to the control processor. When both a bit in this register and the corresponding bit in the NPBUS Status Register are set, the NPBUS status bit will be set in INTST Interrupt Source. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See NPBUS Status Register on page 431 for the bit descriptions. Length Type Address Power On Value Restrictions 6 bits Clear/Set XXXX 2008 and 00C X'00' None Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data pnr25.chapt05.01 August 14, 2000 Page 432 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources 15.4: NPBUS EPROM Address/Command Register Used to accessed a maximum of 2K external serial EPROM or 16 Meg of parallel EPROM or the Sonet Framer Core. This register is used access bytes from the external EPROM or the Sonet Framer Core. Length Type Address Power On Value Restrictions More bytes to Read/Write Serial EPROM 32 bits Read/Write XXXX 2010 X'00000100' None Execute Parallel EPROM Access Execute Serial EPROM Access Framer Access: Not read/Write Execute Sonet Framer Access Not Read/write Reserved EPROM/Extended PHY Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-30 29 28 27 Reserved Framer Access: Not read/Write Execute Sonet Framer Access Execute Parallel EPROM Access More bytes to Read/Write Serial EPROM Not Read/Write Execute Serial EPROM Access Name Reserved. 9 8 7 6 5 4 3 2 1 0 Description This bit set to '1' will cause a write function to the Sonet Framer Core. This bit set to '0' will cause a read function to the Sonet Framer Core. This bit will start a read or write function to the Sonet Framer Core. This bit will auto reset after the command is issued. This bit will start a read or write function to the parallel EPROM. This bit will auto reset after the command is issued. This bit set to '1' will help speed up sequential accesses to the serial EPROM. If writing, there is a limit as to how many bytes can be written before the serial EPROM write buffer is full. Typical range is from two to eight bytes, depending on the device. This bit set to '1' will cause a write function to the serial/parallel EPROM. This bit set to '0' will cause a read function to the serial/parallel EPROM. This bit will start a read or write function to the serial EPROM. This bit will auto reset after the command is issued. This holds the address field that will be used to address the serial/parallel EPROM. It is also where the 15 - 8 address bits will be held if addressing a PHY with more addressability than eight bits. 26 25 24 23-0 EPROM/Extended PHY Address pnr25.chapt05.01 August 14, 2000 Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data Page 433 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 15.5: NPBUS EPROM Data Register Used to accessed a maximum of 2K external serial EPROM or 16 Meg of parallel EPROM. Length Type Address Power On Value Restrictions Reserved 32 bits Read/Write XXXX 2018 X'00000000' None Read Data Reserved Write Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 23-16 15-8 7-0 Reserved Read Data Reserved Write Data Name Reserved. 9 8 7 6 5 4 3 2 1 0 Description Holds the data that was read back from the serial/parallel EPROM. Reserved. Holds the data that is destined to be written to the serial/parallel EPROM. 15.6: PHY 1 Registers This address range provides access to the PHY 1 hardware. The details of the registers can be found in the specific publication for the PHY hardware. Length Type Address Power On Value Restrictions 15.7: PHY 2 Registers This address range provides access to the PHY 2 hardware. It should be noted that not all applications of IBM3206K0424 will use this access port. The details of the registers can be found in the specific publication for the PHY hardware. Length Type Address Power On Value Restrictions 256 Doublewords (only lowest eight bits valid) Read/Write XXXX 2800 - BFF Reference the PHY-specific publication. Reference the PHY-specific publication. 256 Doublewords (only lowest eight bits valid) Read/Write XXXX 2400 - 7FF Reference the PHY-specific publication. Reference the PHY-specific publication. Nodal Processor Bus Interface (NPBUS)/CRISCO Processor for Register Initialization from EPROM Data pnr25.chapt05.01 August 14, 2000 Page 434 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources Hardware Protocol Assist Entities Entity 16: On-chip Checksum and DRAM Test Support (CHKSM) Functional Description The CHKSM entity has two functions: First, it is capable of initializing and/or testing packet and Control Memory; second, it can perform TCP checksums (Two's complement, 16-bit sum with "end-around-carry"). 16.1: CHKSM Base Address Register The CHKSM Base Address Register indicates the starting address of a test operation or checksum calculation. The base address can be set up with any alignment and valid address. This register increments with each read or write to memory. On a test mode error, the register holds the address of the 64-bit word which was read in error. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0A00 X'00000000' Can only be written when CHKSM is not enabled (see EE bit in CHKSM Control Register on page 440) pnr25.chapt05.01 August 14, 2000 On-chip Checksum and DRAM Test Support (CHKSM) Page 435 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 16.2: CHKSM Read/Write Count Register The CHKSM Read/Write Count Register indicates the count of remaining bytes of a checksum operation. This register keeps track of how many bytes remain in the current checksum operation and is decremented with each read or write operation. Any length can be set in the 30 lower significant bits. The upper two bits of this register can be written when starting a checksum operation instead of writing the control register. Length Type Address Power On Value Restrictions 32 bits Read/Write XXXX 0A04 X'00000000' Can only be written when CHKSM is not enabled (see EE bit in CHKSM Control Register on page 440) ST-CK CL-IP Remaining Bytes 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 Name ST-CK Description 9 8 7 6 5 4 3 2 1 0 Start a checksum operation. When this bit is written, bits 0 and 1 in the control register are set, and a checksum operation is started. This should only be done when the rest of the control register bits are already set up. (That is, memory select, invert checksum,...) When this bit is written, it will clear the CHKSM TCP/IP Checksum Data Register. This is the same as writing a '1' to bit 6 of the CHKSM Control Register. 30 CL-IP On-chip Checksum and DRAM Test Support (CHKSM) Page 436 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 16.3: CHKSM TCP/IP Checksum Data Register The CHKSM TCP/IP Checksum Data Register collects the 16-bit, two's complement, end-around-carry sum of the bytes. The source data is zero padded if it starts/ends on an odd byte boundary. The CHKSM TCP/IP Checksum Data Register collects the 16-bit, two's complement, end-around-carry sum of the bytes. It can be seeded with an initial value. If it is not cleared before running a checksum, the previous value will act as a seed. This register can be cleared when starting a checksum operation by writing the CLIP bit in the CHKSM Control Register or by writing upper bits of CHKSM Read/Write Count Register. See CHKSM Control Register on page 440) for description of how to get/set current checksum alignment. Length Type Address 16 bits Read/Write Normal sum Inverted sum Swapped sum Inverted swapped sum Power On Value Restrictions X'0000' Can only be written when CHKSM is not enabled (see EE bit in CHKSM Control Register on page 440) XXXX 0A08 XXXX 0A0c XXXX 0A34 XXXX 0A38 16.4: CHKSM Ripple Base Register This register is used as base of a ripple pattern when in test mode. This register forms the base for a ripple pattern. Each consecutive byte will be incremented by one or eight in the pattern. The ripple mode must be set in the Control Register to use this feature. The value of this register will change during the test operation. If a write and compare operation are being performed, this register needs to be setup again for the second operation. Length Type Address Power On Value Restrictions 8 bits Read/Write XXXX 0A14 X'00' Can only be written when CHKSM is not enabled (see EE bit in CHKSM Control Register on page 440) pnr25.chapt05.01 August 14, 2000 On-chip Checksum and DRAM Test Support (CHKSM) Page 437 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 16.5: CHKSM Ripple Limit Register This register is used to determine when the ripple base register overflows to zero. This register forms the compare value for the ripple base register. When the value of the ripple base register is greater than or equal to this register, the base register will overflow to zero. For example, when this register is set to four, the ripple base register would count from zero through four if counting by one. When set to 0x00, no overflows to zero occur. For example, when the ripple value is 0xff, and you are counting by eight, the next value would still be seven. If counting by one, then the next value would be zero. This register should be written before the ripple base. Length Type Address Power On Value Restrictions 8 bits Read/Write XXXX 0A10 X'ff' Can only be written when CHKSM is not enabled (see EE bit in CHKSM Control Register on page 440) 16.6: CHKSM Interrupt Enable Register Used to specify which status register bits should be used to generate interrupts. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See CHKSM Control Register on page 440) for the bit descriptions. Length Type Address Power On Value Restrictions 12 bits Clear/Set XXXX 0A20 and 24 X'ffe' None On-chip Checksum and DRAM Test Support (CHKSM) Page 438 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 16.7: CHKSM Status Register Used to relay CHKSM status information. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 12 bits Clear/Set XXXX 0A18 and 1c X'01' The count zero bit is not writable. TE1 -- Test Error MSW TE0 -- Test Error LSW 1 LCK -- Comet Lock TEX -- Test Error in Byte 7-0 11 10 Bit(s) 11-4 3 2 1 0 9 8 7 6 5 4 Name 3 2 CZ -- Count Zero 0 Description When these bits are set, the checksum has determined that a read comparison error was encountered in the corresponding byte. Byte 0 is bits 63 - 56 in a 64-bit long word. When this bit is set, the checksum has determined that COMIT has ceased operation for some reason, or a virtual error was detected. When this bit is set, checksum has determined that a read comparison error was encountered in the most significant 32-bit word. When this bit is set, the checksum has determined that a read comparison error was encountered in the least significant 32-bit word. This bit is set when the terminal count of an operation is reached. TEX -- Test Error in Byte 7-0 LCK -- Comet Lock TE1 -- Test Error MSW TE0 -- Test Error LSW CZ -- Count Zero pnr25.chapt05.01 August 14, 2000 On-chip Checksum and DRAM Test Support (CHKSM) Page 439 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 16.8: CHKSM Control Register The various bits in this register control the mode in which the checksum entity operates. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power On Value Restrictions 13 bits Clear/Set XXXX 0A28 and 2c X'00' None ET -- Enable TCP Checksum Updates 1 SW-SUM -- Swap Checksum 12 11 10 bit(s) 9 8 7 6 5 4 3 2 Name EE -- Enable Entity CHKSM 0 Description When this bit is set, the CHKSM TCP/IP Checksum Data Register is set to 0xffff when it is cleared. When this bit is cleared, the CHKSM TCP/IP Checksum Data Register is set to '0'. This option should be used if the TCP/IP checksum should never be set to '0' (0xffff is `0' also). When this bit is set, the internal checksum alignment is exposed for reading/writing. For writes, bit 16 of the write data is used to set the internal alignment. For reads, the alignment is exposed in bit 16 or bit 0 depending on the value of the HI-LO bit in this register. This can be useful if doing non-consecutive multiple part check sums (need to preserve alignment between chunks). When this bit is cleared, the internal checksum aliment is not exposed. It is always cleared when the CL-IP bit in this register is set. Normally, the internal alignment is calculated and maintained across consecutive check sums. When this bit is set, the checksum data register data is placed in the most significant 16 bits of the 32-bit value read. When this bit is cleared, the checksum data register data is placed in the least significant 16 bits of the 32-bit value read. This bit does not affect how writes to the checksum data register occur; the data from the least significant 16 bits is always used. When this bit is set, the checksum data register data is byte-swapped when read. When this bit is cleared, the checksum data register data is read normally. There are also new checksum data register addresses that can be read that do the same thing as this control bit. This bit is depreciated. When this bit is set, the checksum data register data is inverted when read. When this bit is cleared, the checksum data register data is read normally. There are also new checksum data register addresses that can be read that do the same thing as this control bit. This bit is depreciated. IN-SUM -- Invert Checksum EX-AL -- Expose Alignment RP-ADD -- Ripple Addend CL-FF -- Clear to All Ones RW -- R/-W Test Mode MS -- Memory Select HI-LO -- Hi Lo Word 12 CL-FF -- Clear to All Ones 11 EX-AL -- Expose Alignment 10 HI-LO -- Hi Lo Word 9 SW-SUM -- Swap Checksum 8 IN-SUM -- Invert Checksum On-chip Checksum and DRAM Test Support (CHKSM) TM -- Test Mode CL-IP -- Clear IP RP -- Ripple Page 440 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary bit(s) 7 Name RP-ADD -- Ripple Addend IBM Processor for Network Resources Description When this bit is set, the ripple base register counts up by one. When this bit is cleared, the ripple base register counts up by eight. When this bit is written, it will clear the CHKSM TCP/IP Checksum Data Register and itself. The result of this will be that this bit will never be read as a '1'. The internal alignment is also cleared. When this bit is set, a ripple pattern will be used in both the read and write test modes. The ripple pattern is used instead of the constant test pattern. When this bit is reset, the constant test pattern is used for the test mode data. When this bit is set, all CHKSM memory accesses are to the Control Memory. When this bit is cleared, all CHKSM memory accesses are to the Packet Memory. When this bit is set, the entity will take the data that is read and compare it to the test/ripple pattern. When this bit is reset, the checksum entity will write data using the test/ripple pattern to the DRAM. When this bit is set, the entity will take the data that is read and compare it to the test/ripple pattern, or will write data using the test/ripple pattern to the DRAM depending on the setting of the RW bit. In both cases, the reading or writing will continue until either an error is encountered or the CHKSM Read/Write Count Register counts down to '0'. When this bit is reset, the checksum entity will operate as described by the other bits. Test and CHKSM modes are mutually exclusive, and test mode takes precedence. When this bit is set, the entity will collect the TCP checksum in the CHKSM TCP/IP Checksum Data Register. When this bit is reset, the CHKSM TCP/IP Checksum Data Register will not be changed by data that is read from the DRAM. Test and CHKSM modes are mutually exclusive, and test mode takes precedence. When this bit is set, the entity will run as specified. When this bit is reset, the entity will not run. 6 CL-IP -- Clear IP 5 RP -- Ripple 4 MS -- Memory Select 3 RW -- R/-W Test Mode 2 TM -- Test Mode 1 ET -- Enable TCP Checksum Updates 0 EE -- Enable Entity CHKSM Debugging Register Access 16.9: CHKSM Internal State Internal state of checksum. Note: This register should not be written unless specifically directed to do so by IBM technical support. Length Type Address Power On Value Restrictions 3 bits Read/Write XXXX 0A3c X'00000000' None pnr25.chapt05.01 August 14, 2000 On-chip Checksum and DRAM Test Support (CHKSM) Page 441 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Software Use of CHKSM This section outlines some ways CHKSM can be set up and used. Test Mode Possible Patterns In test mode, a 64-bit pattern is written/compared to/with memory. There are several different patterns that can be used: Constant Test Pattern Ripple Pattern with increment of 1 When in test mode, and the RP bit is cleared, the CHKSM Ripple Base Register is replicated eight times to form a 64-bit pattern. When in test mode and the RP bit is set and RP-ADD is set and CHKSM Ripple Limit Register is set to '0', a 64-bit pattern is generated using the CHKSM Ripple Base Register as a base. For example, if the CHKSM Ripple Base Register is set to '1', the following pattern is generated: 0102030405060708 0203040506070809 030405060708090a 0405060708090a0b ... Ripple Pattern with increment of 8 When in test mode and the RP bit is set and RP-ADD is cleared and CHKSM Ripple Limit Register is set to '0', a 64-bit pattern is generated using the CHKSM Ripple Base Register as a base. For example, if the CHKSM Ripple Base Register is set to '1', the following pattern is generated: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 191a1b1c1d1e1f20 ... Ripple Pattern with Ripple Limit Each of the above ripple patterns can also make use of the CHKSM Ripple Limit Register. By setting this register, the user can control when the ripple pattern rolls over to zero. For example, when the CHKSM Ripple Limit Register is set to three in increments by one mode the ripple pattern looks like: 0102030405060708 0203040506070809 030405060708090a 0001020304050607 0102030405060708 0203040506070809 030405060708090a ... Similarly, when the CHKSM Ripple Limit Register is set to ten, in increment-by-eight mode, the ripple pattern looks like: 0102030405060708 090a0b0c0d0e0f10 1112131415161718 0001020304050607 ... On-chip Checksum and DRAM Test Support (CHKSM) Page 442 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Initializing Packet/Control Memory The following list shows the steps to use CHKSM to initialize Packet or Control Memory: * Make sure CHKSM is in diagnostic mode, and other mode bits are reset * * * * Set the start address by writing the base address Set up the read/write count with number of bytes to initialize Set up the test pattern register (ripple pattern register) with pattern to use Set up the Control Register to enable test mode, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized * Now busy wait until operation is done (or set up Interrupt Enable Register and wait for interrupt) Testing Packet/Control Memory The following list shows the steps to use CHKSM to test packet or Control Memory: * First initialize memory with a pattern using above sequence * Make sure CHKSM is in diagnostic mode, and other mode bits are reset * Set the start address by writing the base address * Set up the read/write count with number of bytes to test (same as initialization value) * The test pattern register (ripple pattern register) already contains the pattern * Set up the Control Register to enable test mode, turn on RW bit, enable checksum entity, and set the memory select bit correctly based which memory is to be initialized * Now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt) * When done, check the status register for any errors Using Ripple Pattern Generation/Checking in Packet/Control Memory The procedures to use the ripple pattern generation and checking are the same as using test write/read modes. The only difference is that the use ripple pattern mode bit must be set and the ripple pattern base register must be set up. Running a TCP/IP Checksum in Packet/Control Memory The following list shows the steps to use CHKSM to generate/verify a TCP/IP checksum: * Make sure CHKSM is in diagnostic mode (not enabled) * Set the start address by writing the base address * Set up the read/write count with number of bytes to run checksum over, and set the upper two bits of the read/write count register. Writing these upper two bits assumes other mode bits are set correctly (that is, memory bank select). * Now busy wait until operation is done (or set up interrupt Enable register and wait for interrupt) pnr25.chapt05.01 August 14, 2000 On-chip Checksum and DRAM Test Support (CHKSM) Page 443 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 17: Processor Core (PCORE) PCORE contains the on board processor and its local subsystems. The primary intent is to run Available Bit Rate(ABR) control software and user application code such as protocol termination/assist code. DCR Interface The Device Control Register (DCR) interface is a special processor bus to access local registers. These include serial port registers and various other registers. Interrupt Controller This logic manages the interrupts that are passed on to the Cobra Core. There are two levels of interrupt for the core: Critical Interrupts and Normal Interrupts. Interrupts can be taken from both on chip and off chip sources. PCORE has a variety of interrupt source and enable registers. Bridge-Address Translation Cobra Core can access a variety of memory subsystems. Facilities are provided that allow multiple subsystem accesses. Processor address space is translated into target memory system addresses. For the most part, this allows the processor to be unaware of target memory address space considerations while running mainline code. OCM SRAM OCM is provided for the use of the processor. Typical access time to the OCM is a single cycle, the same as for cache. Address translation facilities have been added to make more efficient use of this memory via additional and extended BAT registers. Control Memory Control Memory can be accessed by the processor. This memory may be mapped into the processor space in a number of different ways. Packet Memory Packet memory can be accessed by the processor. This memory may be mapped into the processor space in a number of different ways. Packet memory space also includes the virtual memory space of the IBM3206K0424. PCI Master Interface-External The processor can access the PCI bus through this interface. Parts of PCI space are mapped into processor space. There are a number of different ways that this can be mapped into processor space. Processor Register Space This access mode of the PCI master interface allows access to the internal IBM3206K0424 registers. This access is handled internally and does not affect the external PCI bus. Processor Core (PCORE) Page 444 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Address Translation Examples TBD Cobra Structure Cobra Core Data Side LSU DCACH DMMU PPOCM (D-Side) pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 445 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Cobra Core Instruction Side IMMU PPOCM (I-Side) BPU ICACH Cobra Core "Glossy" Description The Cobra Core is a 32-bit PowerPC RISC embedded controller. It is fully compatible with the PowerPC User Instruction Set Architecture. Details about the exact instruction set are described below. The Cobra Core has a PowerPC instruction execution complex, separate 32k instruction and data caches, separate instruction and data 604-style MMUs (not supported this pass), and 401-style interrupts, timers and debug facilities. The Cobra Core has a direct connection to 96k of on-chip memory which can be used for both instruction and data storage, as well as interfaces to the IBM3206K0424's PCI and register buses and both of the IBM3206K0424's memory controllers. The DCR bus provides fastand private access to specific performance-sensitive registers. Features Instruction Execution * Compatible with PowerPC User Instruction Set Architecture (UISA) * Separate Branch, Condition Register, Integer, and Load/Store units for super-scalar execution * Support for limited out-of-order execution * Dispatches/Executes up to 2/4 instructions per clock cycle * Four stage pipeline allowing single cycle execution for most instructions * 32x32-bit general purpose registers (GPRs) * Single cycle loads and stores * Byte, halfword, word, and string accesses to any byte alignment supported in hardware * Hardware multiply and divide (multiply up to 10 cycles, divide up to 32 cycles) * No FPU hardware - FPU instructions result in interrupts Processor Core (PCORE) Page 446 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Timers * 32-bit decrementer * 64-bit time base * Programmable and fixed interval timers * Watchdog timer Cobra Core Exceptions * Two priority levels - Normal - uses SRR0/1 (603) - Critical - uses SRR2/3 (401 extension) * Exception Types - System Reset (boot vector) - Machine Check - Data Storage Interrupt - Instruction Storage Interrupt - External - Alignment - Trap - Invalid Opcode - Privilege Violation - Floating Point Unavailable - Decrementer - System Call - Trace - System Management (603) - Programmable Interval Timer (401) - Fixed Interval Timer (401) - Watch Dog Timer (401) - Critical Interrupt (401) - Debug Interrupt (401) pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 447 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Optional Architecture Extensions * Programmable boot address (system interrupt vector) * Interrupt enhancements - Individually re-locatable interrupts - Individually programmable interrupt level (normal/critical) Caches * 32-byte cache lines (eight words/line) * Four-way set associative write back 32k instruction and data caches Memory Management * Real Flat Address Mode supported Interrupt Controller * Two interrupt levels external to COBRA: normal and critical * Three-way interrupts - From IBM3206K0424 to COBRA - From COBRA to PCI - From PCI to COBRA Debug Support * PowerPC JTAG debugger support (401 RiscWatch) * 401 debug instructions * Serial Port Debugger support * PCI Debug access to JTAG debug facilities Interfaces On-Chip Memory * 96k of on-chip memory * Can be used simultaneously by instruction and data accesses * OCM Basic DMA controller provides bulk data moves to/from OCM IBM3206K0424 Registers * Read/Write access to the IBM3206K0424 register bus * Some critical registers are mapped to COBRA Core DCR register space PCI Bus * Read/Write master access to PCI Bus * Currently no actual streaming/bursting supported * Pseudo bursting supported (multiple back to back single transfers) * Interrupt sink * No arbitration supported (we are not a complete bridge) Comet/Pakit Memory * Able to use both memory controllers for both instruction and data accesses Processor Core (PCORE) Page 448 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Performance * 133 MHz operating frequency * Performance estimates unavailable Instruction Set Instruction Set (with 401 as a base) * Supports ALL 401 instructions with the following additions/subtractions: * Added from 603 - mfsr, mfsrin, mtsr, mtsrin, tlbie, tlbld, tlbli, tlbsync (Note: virtual memory not supported this pass) - mftb (for 603 style time base support) * Removed from 401 - dcread, icread (replaced with SPR access to the caches) - Changed mfspr, mtspr (to accommodate new SPRs) Instruction Set (with 603 as a base) * Supports ALL 603 instructions with the following additions/subtractions * Added from 401 - dccci, icbt, iccci, mfdcr, mtdcr, rfci, wrtee, wrteei * Removed from 603 - fXXXXX, lfXXX, stfXXX, mffXXX (floating point instructions), - eciwx, ecowx (PowerPC I/O addressing not supported - only memory space addressing) - Changed mfspr, mtspr (to accommodate new SPRs) Cobra Instruction Overview Cobra Core supports all of the instructions in either the PowerPC 603 User's Manual (MPR603UMU-01,MPC603UM/AD) or the Power PC 401 Core User's Manual (v0.07 1/28/978) with the following changes. If an instruction does not exist in both user's manuals, it is described below. pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 449 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Cobra Instruction Changes Instruction(s) dccci, icbt, iccci mfdcr, mtdcr rfci, wrtee, wrteei mfsr, mfsrin, mtsr, mtsrin mftb tlbie tlbsync mfbus, mtbus dcread, icread dcba tlbre, tlbsx(.), tlbwe eciwx, ecowx fxxxxx lfd, lfdu, lfdux, lfdx, lfs, lfsu, lfsux, lfsx mffs, mffsb0, mffsb1, mffsf, mffsfi stfd, stfdu, stfdux, stfdx, stfiwx, stfs, stfsu, stfsux, stfsx tlbld, tlbli Source 401 401 401 603 603 603 603 Cobra Core 401 405 405 603 603 603 603 603 603 Added for cache management Added for DCR bus support Added for 40x interrupt support Added for 60x MMU support (not supported this pass) Added for 60x style time base support Added for 60x MMU support (not supported this pass) Added for 60x compatibility, acts as a no-op Added - See Appendix: New instructions Removed - cache layout is different Not Supported - 405 only instruction Removed - 40x style MMU not supported Removed - only memory space addressing supported Removed floating point support Removed floating point support Removed floating point support Removed floating point support Removed - 603 style MMU support, may add next pass Description Cobra Facilities Overview The following registers are patterned after the registers in either the PowerPC 603 User's Manual (MPR603UMU-01,MPC603UM/AD) or the Power PC 401 Core User's Manual (v0.07 1/28/978). Differences between the two implementations and the Cobra Core implementations are detailed below. The registers are split into these functional groupings: Machine Control/Status Registers, Branch Control Registers, Debug Control Registers, Special Purpose Facilities, Interrupt and Exception Registers, Timer Registers, Cache Control Registers, and Translation Control Registers. Source Key: * BOTH - same bit definitions as 603 and 401 * 401 - same bit definitions as 401 * 603 - same bit definitions as 603 * PPC - same bit definitions as general Power PC architecture * COBRA - COBRA Configuration Processor Core (PCORE) Page 450 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Machine Control/Status Registers Register SPR Name Number cr hid0 ear msr xer NA 1023 282 NA 1 Source BOTH POR value X'00 00 00 00' Notes COBRA X'00 00 00 FC' 603 COBRA X'00 00 00 40' BOTH X'00 00 00 00' Machine Check Enable - set bits off/ set bits on Not Supported, writes ignored, reads as zeros. mchk-on 688/689 COBRA X'00 00 00 00' pvr 287 COBRA X'10 10 00 00' Branch Control Registers Register SPR Name Number ctr lr 9 8 Source BOTH BOTH POR value X'00 00 00 00' X'00 00 00 00' Notes Debug Register SPR Name Number dabr dac1 dbcr dbdr dbsr iabr iac1 1013 1014 1010 1011 1008 1010 1012 Source PPC 401 401 401 401 603 401 X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' Not implemented, use IAC1 POR value Not implemented, use DAC1 Notes Special Purpose Facilities Register SPR Name Number sprg0 sprg1 sprg2 sprg3 sprg4-7 sprg4-7 272 273 274 275 Source BOTH BOTH BOTH BOTH POR value X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' Read/Write Read Only Notes 276-279 COBRA X'00 00 00 00' 68-71 COBRA X'00 00 00 00' pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 451 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Interrupt and Exception Registers Register SPR Name Number dar dear dsisr esr evpr srr0 srr1 srr2 srr3 19 19 18 980 982 26 27 990 991 Source 603 401 603 401 401 BOTH BOTH 401 401 X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' When HID0(27) = 0 (603 mode), upper 16 bits act as status; the lower 16 bits are set from the MSR. When HID0(27) = 1 (401 mode), all bits are set from the MSR. Behaves like srr0; used for critical level interrupts. Behaves like srr; used for critical level interrupts. Only MCI, PIL, PPR, PTR, DST, and PFEU bits implemented POR value X'00 00 00 00' Same as dar with different address Notes Timer Registers Register SPR Name Number dec pit tbhi tblo tbhu tblu tbl tbu tbl tbu tcr tsr 22 987 988 989 972 973 284 285 268 269 986 984 Source 603 401 401 401 401 401 603 603 603 603 401 401 POR value X'FF FF FF FF' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' Upper half of 64-bit time base register. R/W, privileged spr. Lower half of 64-bit time base register. R/W, privileged spr. Upper half of 64-bit time base register. R-only, non-privileged spr. Lower half of 64-bit time base register. R-only, non-privileged spr. Same as tblo, but write only Same as tbhi, but write only tbr (not spr) same as tblu tbr (not spr) same as tbhu Notes Processor Core (PCORE) Page 452 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Cache Control Registers Register SPR Name Number dccr dlcr dtwf iccr ilcr itwf cdcbr dcwr icdbdr 1018 917 919 1019 916 918 983 954 979 Source 401 POR value X'00 00 00 00' Bits 0-15 correspond to target tags 0-15, enabling auto data cache line locking Bits 0-15 correspond to target tags 0-15, enabling target word first data cache fills Notes COBRA X'00 00 00 00' COBRA X'00 00 00 00' 401 X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' 401 401 401 Bits 0-15 correspond to target tags 0-15, enabling auto instruction cache line locking Bits 0-15 correspond to target tags 0-15, enabling target word first instruction cache fills Not implemented Not implemented Not implemented Translation Registers Register SPR Name Number sdr1 sgr sler stt0 stt1 stt2 stt3 sr0-15 dbat0u dbat0l dbat1u dbat1l dbat2u dbat2l dbat3u dbat3l dbat4u dbat4l dbat5u dbat5l 25 53 55 912 913 914 915 NA 536 537 538 539 540 541 542 543 568 569 570 571 Source 603 401 401 COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' 603 603 603 603 603 603 603 603 603 X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass POR value X'00 00 00 00' X'00 00 00 00' Notes Not Supported - translation disabled this pass Has no affect this pass. All storage is non-guarded. Not Supported - writes ignored, reads as '0' When IR=0 or DR=0, these registers are used to assign target tags to instruction or data memory accesses. The mapping is stt0(0:3) = 0x00000000 - 0x07FFFFFF through stt3(28:31) = 0xF8000000 - 0xFFFFFFFF. COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 453 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Translation Registers (Continued) Register SPR Name Number dbat6u dbat6l dbat7u dbat7l ibat0u ibat0l ibat1u ibat1l ibat2u ibat2l ibat3u ibat3l ibat4u ibat4l ibat5u ibat5l ibat6u ibat6l ibat7u ibat7l 572 573 574 575 528 528 530 531 532 533 534 535 560 561 562 563 564 565 566 567 Source POR value Notes Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass Not Supported - translation disabled this pass COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' 603 603 603 603 603 603 603 603 X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' Exception Vector Override Registers Register SPR Name Number evc-off evc-on evov-off evov-on evr-mc evr-dsi evr-isi evr-ex1 evr-aln evr-inv evr-prv evr-trp evr-fpu 700 701 702 703 720 721 722 723 724 725 726 727 728 Source POR value Notes See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. pnr25.chapt05.01 August 14, 2000 COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' Processor Core (PCORE) Page 454 of 676 IBM3206K0424 Preliminary IBM Processor for Network Resources Exception Vector Override Registers (Continued) Register SPR Name Number evr-dec evr-sc evr-trc evr-smi evr-pit evr-fit evr-wdt evr-ex2 evr-dbg 729 730 731 732 733 734 735 752 753 Source POR value Notes See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. See Cobra Core Exceptions on page 447. COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' COBRA X'00 00 00 00' Internal Debug Access Address Map Unit Bpu Internals Reg Internals Lsu Internals Fxu Internals ICache Internals Immu Internals DCache Internals Dmmu Internals Reserved X'000' - X'07F' X'080' - X'0FF' X'100' - X'17F' X'180' - X'1BF' X'1C0' - X'1FF' X'200' - X'2BF' X'2C0' - X'2FF' X'300' - X'3BF' X'3C0' - X'3FF' Debug Bus Address Range Cobra Specific Register Definitions For most of the registers named above, either a 40x or 60x spec will give the bit definition. There are a few registers which are different enough that they are described in detail below. pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 455 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.1: Hardware Implementation Detail 0 Register (HID0) Enables caches and controls architecture specific functionality. This register controls whether Cobra Core acts as a 40x or 60x series processor and allows the different features of each architecture to be individually selected. Length Type Address Power on Reset value 32 bits Read/Write 1023 X'00 00 00 FC' (40x mode) X'80 00 00 00' - Alternative value (60x mode suggested value) Restrictions Allow Data Machine Checks to be Imprecise Disable Instruction/CR-logical-op Pairing Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 Name No-Op Touch Instructions Reserved Disable decrementer 9 8 7 6 5 4 3 2 1 Description 0 = touch instructions work; 1 = touch instructions disabled Reserved When '0', the decrementer register is a free running countdown register which causes a decrementer interrupt when it decrements through '0'. When `1', the decrementer register does not decrement. When '0', lmw/stmw instructions to non-word aligned addresses cause alignment interrupts (60x mode). When '1', lmw/stmw instructions never cause alignment interrupts (40x mode). When '0', interrupts cause srr1/3 to receive interrupt codes in bits 0:15, and MSR contents in bits 16:31. Likewise, rfi/rfci restore bits 16:31 of srr1/3 to the MSR. When '1', interrupts cause srr1/3 to receive MSR contents in bits 0:31. Likewise, rfi/rfci restore bits 0:31 of srr1/3 to the MSR. Status is stored in ESR register regardless. 28 Disable alignment interrupts on lmw/stmw 27 SRR1/3 Style Processor Core (PCORE) Page 456 of 676 pnr25.chapt05.01 August 14, 2000 Enable Checkstop on Machine Check 0 Disable Instruction/Branch Pairing Disable Instruction Pipelining Disable Conditional Dispatch No-Op Touch Instructions Instruction Cache Enable Disable Decrementer Disable Decrementer Debug Mode Select Data Cache Enable IP/EVPR Override SRR1/3 Style WE Enable Reserved IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description When '1', EVPR contents are used as the upper 16 bits of the exception vector, regardless of the value of MSR(IP). When '0', MSR(IP) determines the upper 16 bits of the exception vector. HID0(IPO=26) MSR(IP=25) Exception Vector 0 0 0x0000vvvv 0 1 0xFFF0vvvv 1 0xeeeevvvv Note: eeee = EVPR register contents, vvvv = exception vector offset (for example, 0700) A '0' enables the BE and SE bits of the MSR to function as a 60x, a '1' enables the MSR(DE) bit as a 40x. Note: All 40x debug facilities (IAC, DAC, etc.) are disabled when in 60x mode. Enables the MSR(WE) bit to cause a 40x style WE. 0 = disabled, 1 = enabled Reserved 0 = disable, 1 = enable 0 = disable, 1 = enable 1 = disable, 0 = enable 26 IP/EVPR Override 25 24 23-18 17 16 15 14 13 12 11 10-1 Debug Mode Select WE Enable Reserved Data Cache Enable Instruction Cache Enable Disable Instruction/CR-logical-op Pairing Disable Instruction/Branch Pairing 1 = disable, 0 = enable Disable Conditional Dispatch Disable Instruction Pipelining 1 = disable, 0 = enable 1 = disable, 0 = enable Allow Data Machine Checks to be Setting this to '1' will result in a very small performance gain, at the expense of accuImprecise racy in the SRR0/2 of a machine check. Reserved Reserved When '1', a machine check which occurs when MSR(ME)=0 will cause the hardware to freeze, maintaining much of the state of the machine. When '0', the processor will attempt to continue execution when a machine check occurs when MSR(ME)=0. When MSR(ME)=1 and a machine check occurs, a machine check exception is taken regardless of the setting of this bit. 0 Enable Checkstop on Machine Check pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 457 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.2: Machine State Register (MSR) Controls the run time state of the Cobra Core. Length Type Address Power on Reset value Restrictions 32 bits Read/Write Accessible via the mtmsr/mfmsr instructions X'00 00 00 40' None 603 BE / 401 DE 603/401 ME 603/401 PR 603/401 EE 603/401 FP Reserved Reserved Reserved Reserved Reserved Reserved Reserved 401 WE 603 DR 401 CE 603 SE 603 RI 603 IR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 603 RI Reserved Reserved 603 DR 603 IR IP Reserved Reserved 603 BE / 401 DE 603 SE Reserved Name IP Reserved 9 8 7 6 5 4 3 2 1 0 Description Unimplemented (603/401 LE). Cobra Core doesn't support Little Endian execution. Recoverable Interrupt. This bit is cleared when an exception is taken. Reserved Reserved Translation is not supported. Do not set this bit. Translation is not supported. Do not set this bit. In combination with HID0(IPO = 26), this bit determines the upper 16 bits of an exception vector. See Hardware Implementation Detail 0 Register (HID0) on page 456 for full details. Reserved Unimplemented (603 FE1). Cobra Core doesn't support floating point. If HID0(25) = 0 this is 603 BE otherwise it is 401 DE. If HID0(25) = 0 this is 603 SE otherwise it is a read/write bit with no affect. Unimplemented (603 FE0). Cobra Core doesn't support floating point. Enables Machine Check Exceptions. If this bit is '1', a machine check will cause a machine check exception to occur. If this bit is '0', a machine check will cause Cobra Core to halt execution (if HID0(0) = 1), or the machine check will be ignored (if HID0(0) = 0). If FP=0, all floating point instructions cause a floating point disabled interrupts. If FP=1, all floating point instructions cause illegal instruction interrupts. Privilege Instruction Restricted. If this bit is '1', attempting to execute a privileged (supervisor) instruction will result in a privilege violation exception. If this bit is '0', all instructions may be executed normally. External Interrupt Enable. Used to mask off non-critical level exceptions. Unimplemented (603 ILE) Cobra Core doesn't support Little Endian execution. 19 603/401 ME 18 603/401 FP 17 16 15 603/401 PR 603/401 EE Reserved Processor Core (PCORE) Page 458 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description Enables critical level exceptions. Critical level exceptions are higher priority than normal exceptions. Any exception can be assigned critical level in Cobra Core. This bit can only mask off exceptions programmed to be critical level through other Cobra Core facilities. By default, no exception is critical level. Note: The 60x doesn't have the concept of critical level exceptions. The 40x has both critical level exceptions and a critical interrupt. The critical interrupt is just a second external interrupt. In the 40x, specific exceptions were hard wired to be critical level, and the rest were hard wired to be normal level. If HID0(24) = 0, this is a r/w bit with no affect (603 POW), otherwise it is the (401 WE) bit. When this bit is set, the processor halts operation until this bit is cleared (via an interrupt). Reserved 14 401 CE 13 12-0 401 WE Reserved pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 459 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.3: Exception Status Register (ESR) When an exception occurs, this register is updated to indicate which condition caused the exception. If an exception vector can only be reached by one exception, this register is cleared. Length Type SPR Address Power on Reset value Restrictions 32 bits Read/Write 980 X'00 00 00 00' None DST Data Storage PFEU Program PPR Program PTR Program PIL Program Reserved Reserved Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-14 13 12-9 8 7 6 5 4 3-1 0 Reserved PFEU Program Reserved DST Data Storage Reserved PTR Program PPR Program PIL Program Reserved MCI Name Reserved 9 8 7 6 5 4 3 2 1 Description Floating point enabled, but instruction unimplemented exception. Reserved A store instruction or (dcbz/dcbi) caused the data exception. Reserved Program - Trap Instruction Exception Program - Privileged Instruction Exception Program - Illegal Instruction Exception Reserved Machine Check - Instruction Processor Core (PCORE) Page 460 of 676 pnr25.chapt05.01 August 14, 2000 MCI 0 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.4: Machine Check Enable Register (MCHK) When an exception occurs, this register is updated to indicate which condition caused the exception. If an exception vector can only be reached by one exception, this register is cleared. Length Type SPR Address Power on Reset value Restrictions Reported SPR Multiple Data Returned Machine Check Reported SPR Multiple Ack Returned Machine Check 32 bits Clear/Set 688/689 X'00 00 00 00' None Enable SPR Multiple Data Returned Machine Check Enable SPR Multiple Ack Returned Machine Check Reported LSU No Valid Instruction Machine Check Enable LSU No Valid Instruction Machine Check Reported Instruction Machine Check Reserved Reserved Reserved Enable Instruction Machine Check Reported Data Machine Check Enable Data Machine Check Reserved Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27-25 24 23 22-16 15 14 13 12 11-9 Reported SPR Multiple Ack Returned Machine Check Reported SPR Multiple Data Returned Machine Check Reserved Reported LSU No Valid Instruction Machine Check Reserved Reported Data Machine Check Reported Instruction Machine Check Reserved Enable SPR Multiple Ack Returned Machine Check Enable SPR Multiple Data Returned Machine Check Reserved Enable LSU No Valid Instruction Machine Check Reserved Name 9 8 7 6 5 4 3 2 1 0 pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 461 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 8 7 6-0 Enable Data Machine Check Enable Instruction Machine Check Reserved Name Preliminary Processor Core (PCORE) Page 462 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PCORE Register Definitions 17.5: PCORE Control Register The PCORE Control Register provides control information about PCORE operations. This is the PCORE control register. It is used to control operation. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions Control Memory Access Priority High on Latency Timer Max Crossing 32 bits Clear/Set XXXX 4000 and 004 X'00 0E 40 09' Caution must be used when asserting some of the bits during operation. Packet Memory Access Priority High on Latency Timer Max Crossing Control Memory Access Priority High on Write FIFO Full Packet Memory Access Priority High on Write FIFO Full DCache Virtual Memory Error Normal/Critical Interrupt FDMA Virtual Memory Error Normal/Critical Interrupt Target Access Dead Man Timer Master Disable Control Memory Write Around FIFO Disable Packet Memory Write Around FIFO Disable PCI Master Write Around FIFO Disable Cobra Hold Most Recent Event Status Memory Lock Normal/Critical Interrupt JTAG Hold Most Recent Error Status Control Memory Access Priority High Serial Port Transmit Interrupt Priority Packet Memory Access Priority High Auto Ack on Hang or Error Detected Serial Port Receive Interrupt Priority Boot Time System Reset Exception PCI Master Wait on Writes Enable Disable Lock PCORE on Error 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-30 29 Reserved Clear Instruction Cache Name Reserved 9 8 7 6 5 4 3 2 1 Description This bit will cause the instruction cache to clear itself to a known state. It will also cause the processor to be in stop state when this happens. It will be cleared when the cache has finished. This bit will cause the data cache to clear itself to a known state. It will also cause the processor to be in stop state when this happens. It will be cleared when the cache has finished. This bit will put the SPR Access Machine into a reset state, so it should be used by setting and then clearing. 28 Clear Data Cache 27 SPR State Machine Abort pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 463 of 676 Diagnostic/Operational Mode 0 SPR State Machine Abort Clear Instruction Cache Cobra Core Run State 64 Bit DCR Primitives Lock Arbit on Error Clear Data Cache Reserved Reserved IBM3206K0424 IBM Processor for Network Resources Bit(s) 26 Name Control Memory Access Priority High on Latency Timer Max Crossing Control Memory Access Priority High on Write FIFO Full Control Memory Access Priority High Packet Memory Access Priority High on Latency Timer Max Crossing Packet Memory Access Priority High on Write FIFO Full Packet Memory Access Priority High Lock Arbit on Error PCI Master Write Around FIFO Disable Packet Memory Write Around FIFO Disable Control Memory Write Around FIFO Disable Reserved Disable Xfer Abort on Pseudo Core Reset Description When set, Control Memory accesses will switch to high priority when the Control Memory latency counter crosses the high priority crossover register value. When set, Control Memory accesses will switch to high priority when the Control Memory write around FIFO is full. When set, Control Memory accesses will be at high priority always. When set, Packet Memory memory accesses will switch to high priority when the Packet Memory latency counter crosses the high priority crossover register value. When set, Packet Memory accesses will switch to high priority when the Packet Memory write around FIFO is full. When set, Packet Memory accesses will be at high priority always. When set to '1', will cause a lock command to be issued to arbit to halt the memory subsystem. Disables the write around buffer for PCI Master. When enabled, write data from either the ICACH or DCACH is buffer through this FIFO on writes. Disables the write around buffer for Packet Memory. When enabled, write data from either the ICACH or DCACH is buffer through this FIFO on writes. Enables the write around buffer for Control Memory. When enabled write data from either the ICACH or DCACH is buffer through this FIFO on writes. Reserved When this bit is written to '1', transfer aborts on Pseudo resets are disabled; when '0', the core master state machines will be put into idle. Preliminary 25 24 23 22 21 20 19 18 17 16-15 15 14 13 JTAG Hold Most Recent Error Sta- When this bit is written to '0', the JTAG error status register will free run. When set to tus '1' it will hold the most recent error status. Cobra Hold Most Recent Event Status When this bit is written to '1', Cobra Core hold it most recent internal event status. When set to '0' it will free run. When this bit is written to '0', PCORE will not auto ack on hang or error. This may leave the processor in a totally stuck state. However corrupted information may be stopped from entering the processor. When set to '1' and hang or error conditions manifest reads may return garbage and write data may be lost BUT the processor should not be stopped cold. When this bit is written to '0', PCORE will treat an IBM3206K0424 virtual memory write error as a critical interrupt. When it is '1', this condition will be treated as a normal interrupt. 12 Auto Ack on Hang or Error Detected 11 FDMA Virtual Memory Error Normal/Critical Interrupt 10 When this bit is written to '0', PCORE will treat an IBM3206K0424 virtual memory write DCache Virtual Memory Error Norerror as a critical interrupt. When it is '1', this condition will be treated as a normal intermal/Critical Interrupt rupt. Memory Lock Normal/Critical Interrupt 64 Bit DCR Primitives Target Access Dead Man Timer Master Disable When this bit is written to '0', PCORE will treat memory locked as a critical interrupt. When it is '1', this condition will be treated as a normal interrupt. When set, the three DCR primitives work in 64-bit mode. In this mode, the first access to the primitive register is to the upper 32 bits. The second reference is to the lower 32 bits. The second access triggers the completion of the operation at the destination. When set, this will disable all of the Target Access Dead Man Timers: PCI Master, Control Memory, Packet Memory, IBM3206K0424 Registers and DCR. 9 8 7 6 Serial Port Receive Interrupt Prior- When set, this will cause a the receive interrupt to be a Critical Interrupt. When not set, ity it is a regular interrupt. Processor Core (PCORE) Page 464 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) 5 Name Serial Port Transmit Interrupt Priority IBM Processor for Network Resources Description When set, this will cause a the transmit interrupt to be a Critical Interrupt. When not set, it is a regular interrupt. 4 When set, this will cause the PCI access machine to wait until the data is actually conPCI Master Wait on Writes Enable firmed written to the device. Normally, this bit is set to off since it decreases performance when enabled. Boot Time System Reset Exception Disable Lock PCORE on Error Cobra Core Run State When set, this bit will issue a system boot reset exception to the Cobra Core Processor. It is reset by the Cobra Core Processor after it has received the system reset exception. When this bit is set and an error occurs and the corresponding lock enable bit is set PCORE will lock. This state is equivalent to being in diagnostic mode. When set, this will place the Cobra Core into run state. When not set, the processor will quiesce and hold at idle. When set, PCORE is in diagnostic mode. When cleared, PCORE is in operational mode. When in diagnostic mode, state machines are held in idle. If they are already active, when they next go to idle they will hold there. 3 2 1 0 Diagnostic/Operational Mode pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 465 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.6: PCORE Reset Control Register The PCORE Reset Control Register provides control information about PCORE reset operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 4000 and 004 X'00 0E 00 09' Caution must be used when asserting some of the bits during operation. Enable Pseudo Core Resets for Watch Dog Timer Core Resets Enable Pseudo Core Resets for JTAG Core Resets Enable Pseudo Core Resets for Cobra Core Reset Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5 4 3 2 1 0 Reserved Enable Pseudo Core Resets for Cobra Core Reset Enable Pseudo Core Resets for JTAG Core Resets Enable Pseudo Core Resets for Watch Dog Timer Core Resets Disable All Cobra Core Resets Disable All JTAG Resets Disable All Watch Dog Timer Resets Name Reserved 9 8 7 6 5 4 3 2 1 Description When this bit is written to '0', Cobra Core resets are converted to chip resets. When this bit is written '1', a pseudo core reset is issued instead. When this bit is written to '0', Cobra Core resets are converted to chip resets. When this bit is written '1', a pseudo core reset is issued instead. When this bit is written to '0', Cobra Core Watch Dog Timer core resets are converted to chip resets. When this bit is written '1', a pseudo core reset is issued instead. When this bit is written to '1', all Cobra Core resets are disabled. When this bit is written to '1', JTAG resets are disabled. When this bit is written to '1', Watch Dog Timer resets are disabled. Processor Core (PCORE) Page 466 of 676 pnr25.chapt05.01 August 14, 2000 Disable All Watch Dog Timer Resets 0 Disable All Cobra Core Resets Disable All JTAG Resets IBM3206K0424 Preliminary IBM Processor for Network Resources 17.7: PCORE Status Register The PCORE Status Register provides status information about PCORE operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 4008 and 00C X'00 00 80 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. Instruction Side Machine Check Condition Detected EControl Memory Hang Condition Data Side Machine Check Issued Packet Memory Hang Condition Serial Port Receive Interrupt PCI Master Hang Condition 1 Data Side Machine Check Instruction Side Machine Serial Port Xmit Interrupt DCR Bus Primitive Hang Register Hang Condition Packet Memory Virtual OCM Interrupt Proxy Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-14 13 12 11 10 Reserved Data Side Machine Check Condition Detected Instruction Side Machine Check Condition Detected Data Side Machine Check Issued Instruction Side Machine Check Issued Packet Memory Virtual Write Failure OCM Interrupt Proxy DCR Bus Primitive Hang Condition Serial Port Xmit Interrupt Serial Port Receive Interrupt Name Reserved 9 8 7 6 5 4 3 2 Description A Data Side Machine Check Condition was detected but not necessarily sent to the Cobra Core. An Instruction Side Machine Check Condition was detected but not necessarily sent to the Cobra Core. A machine check has been issued to the Cobra Core due to a Data Side PCORE error. A machine check has been issued to the Cobra Core due to an Instruction Side PCORE error. When this is set, a virtual write has failed to virtual memory. Either a NAK was returned during the write or while holding for error checking after the write. In either case, it indicates the required storage to complete the operation was not available. When set, OCM is indicating an interrupt condition. One of the DCR primitive accesses has timed out. When the serial port surfaces a Xmit Interrupt it will be reflected here. When the serial port surfaces a Receive Interrupt, it will be reflected here. 9 8 7 6 5 pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 467 of 676 PCORE Locked 0 IBM3206K0424 IBM Processor for Network Resources Bit(s) 4 3 2 1 0 Name Packet Memory Hang Condition Control Memory Hang Condition Register Hang Condition PCI Master Hang Condition PCORE Locked Description Packet memory interface Dead Man Timer has expired. Control Memory interface Dead Man Timer has expired. Register interface Dead Man Timer has expired. PCI Master interface Dead Man Timer has expired. This bit is set when locking is enabled; an error has occurred and the lock mask bit is set that matches the error. Preliminary 17.8: PCORE User Status Register The PCORE User Status Register provides user-defined status information about PCORE software operations. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Clear/Set X'200 and 201' X'00 00 00 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. User Defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 User defined Name Reserved 9 8 7 6 5 4 3 2 1 0 Description Processor Core (PCORE) Page 468 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.9: PCORE Cobra Core External Status Register The PCORE Cobra Core External Status Register provides Cobra Core-defined status information about PCORE. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Clear/Set X'202 and 203' X'00 00 00 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. Data Side Packet Memory Virtual Write Error Normal Interrupt Data Side Packet Memory Virtual Write Error Critical Interrupt FDMA Packet Memory Virtual Write Error Normal Interrupt FDMA Packet Memory Virtual Write Error Critical Interrupt Memory Controller Locked Non-Critical Interrupt Memory Controller Locked Critical Interrupt Reserved Serial Port Transmit Non-Critical Interrupt Serial Port Receive Non-Critical Interrupt Serial Port Transmit Critical Interrupt Serial Port Receive Critical Interrupt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-14 13 12 11 10 9 8 Reserved FDMA Packet Memory Virtual Write Error Critical Interrupt FDMA Packet Memory Virtual Write Error Normal Interrupt Data Side Packet Memory Virtual Write Error Critical Interrupt Data Side Packet Memory Virtual Write Error Normal Interrupt Name Reserved 9 8 7 6 5 4 3 2 1 Description This occurs when the Packet Memory controller returns an error on a packet virtual memory write and the FDMA-side is accessing and this condition is set as critical. This occurs when the Packet Memory controller returns an error on a packet virtual memory write and the FDMA-side is accessing this condition is set as normal. This occurs when the Packet Memory controller returns an error on a packet virtual memory write and the D-side is accessing and this condition is set as critical. This occurs when the Packet Memory controller returns an error on a packet virtual memory write and the D-side is accessing this condition is set as normal. Memory Controller Locked Critical This occurs when the memory controller is locked and this condition is set as critical. Interrupt Memory Controller Locked Non-Critical Interrupt This occurs when the memory controller is locked and this condition is set as non-critical. pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 469 of 676 External Non-Critical Interrupt 0 Internal Non-Critical Interrupt External Critical Interrupt Internal Critical Interrupt IBM3206K0424 IBM Processor for Network Resources Bit(s) 7 6 5 4 3 2 1 0 Name Serial Port Receive Critical Interrupt Serial Port Receive Non-Critical Interrupt Serial Port Transmit Critical Interrupt Serial Port Transmit Non-Critical Interrupt Internal Critical Interrupt Internal Non-Critical Interrupt External Critical Interrupt External Non-Critical Interrupt Description This occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. This occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. This occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. This occurs when the serial controller has a transmit interrupt and the corresponding critical interrupt enable is on in the control register. This occurs when a bit in the IBM3206K0424 primary status register is set and the corresponding critical interrupt enable is on. This occurs when a bit in the IBM3206K0424 primary status register is set and the corresponding non-critical interrupt enable is on. This occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. This occurs when an off chip interrupt is received and the non-critical enable for off chip interrupts is set. Preliminary Processor Core (PCORE) Page 470 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.10: PCORE Cobra Core External Machine Check Status Register The PCORE Cobra Core External Machine Check Status Register provides Cobra Core machine check status information about PCORE. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Clear/Set X'25C and 25D' X'00 00 00 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. Instruction Control Memory Locked Error 1 Instruction Packet Memory Locked Error 0 FDMA Control Memory Locked Error FDMA Packet Memory Locked Error FDMA Packet Memory Locked Error FDMA Packet Virtual Memory Error Data Control Memory Locked Error Data Packet Memory Locked Error Data Packet Virtual Memory Error Instruction Illegal Tag Access 8 7 6 5 4 3 Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 29 28 27 26 25 25-21 21 20 20 Name PCI Master Access Error Control Memory Locked Packet Memory Locked FDMA Packet Virtual Memory Error FDMA PCI Master Error FDMA Control Memory Locked Error FDMA Packet Memory Locked Error Reserved DCR Register Error FDMA Packet Memory Locked Error Data Register Error 9 Description This occurs when the PCI Master Machine returns an error and no requestor currently owns the machine. This occurs when Packet Memory is in a locked state. This occurs when Packet Memory is in a locked state. This occurs when Packet Memory indicates a write error during access of a virtual buffer. This occurs when a PCI master access has an error returned while the data path is accessing it. This occurs when Control Memory locks while the data path is actively accessing it. This occurs when Packet Memory locks while the data path is actively accessing it. Reserved. This occurs when a fatal error, typically a hang, occurs on a DCR register timeout. This occurs when Packet Memory locks while the data path is actively accessing it. This occurs when a fatal error, typically a hang, occurs on an IBM3206K0424register timeout. pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 471 of 676 Instruction PCI Master Error 2 PCI Master Access Error Control Memory Locked FDMA PCI Master Error Packet Memory Locked Data PCI Master Error DCR Register Error IBM3206K0424 IBM Processor for Network Resources Bit(s) 19 18 17 16 15-4 3 Name Data Packet Virtual Memory Error Data PCI Master Error Data Control Memory Locked Error Description This occurs when Packet Memory indicates a write error during access of a virtual buffer. This occurs when a PCI master access has an error returned while the data path is accessing it. This occurs when Control Memory locks while the data path is actively accessing it. Preliminary Data Packet Memory Locked Error This occurs when Packet Memory locks while the data path is actively accessing it. Reserved Instruction Illegal Tag Access Reserved. This occurs when the Instruction side specifies the register space or OCM for the instruction source via the Icache. Since there are no physical connections, these accesses can not occur. This occurs when PCI master access has an error returned while the instruction path is accessing it. This occurs when Control memory locks while the instruction path is actively accessing it. 2 1 0 Instruction PCI Master Error Instruction Control Memory Locked Error Instruction Packet Memory Locked This occurs when Packet Memory locks while the instruction path is actively accessing Error it. Processor Core (PCORE) Page 472 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.11: PCORE JTAG Debug Control Register The PCORE JTAG Debug Control Register enables the JTAG port or a PCI interface processor debugger to control the processor core. Length Type Address Power on Reset value Restrictions Freeze Timers while Stopped 32 bits Read/Write XXXX 4200 X'00 00 00 00' None Reset Control Unconditional Debug Event Stop Processor Block Folding Single Step Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31 30 Name Stop Processor Block Folding 9 8 7 6 5 4 3 2 1 0 Description This bit forces the processor to halt execution. The processor normally dispatches two instructions at a time. Setting this bit forces instruction dispatches to be serialized. Setting this bit when the processor is stopped causes the processor to execute one or two instructions depending on the value of bit 30. This bit automatically clears itself after one cycle. These bits potentially generate one of three resets depending on their value. They automatically reset to B'00' after one cycle. The bits decode as follows: '00' No reset '01' Core reset '10' Chip reset '11' System reset This bit generates an interrupt to the processor. It automatically resets to B'0' after one cycle. This bit freezes the state of all timers in the core if the processor is stopped. Reserved. 29 Single Step 28-27 Reset Control 26 25 24-0 Unconditional Debug Event Freeze Timers while Stopped Reserved pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 473 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.12: PCORE JTAG Debug Status Register The PCORE JTAG Debug Status Register returns core status. Length Type Address Power on Reset value Restrictions 32 bits Read Only XXXX 4204 X'00 00 00 00' None Illegal/Privileged/Trap Instruction Exception Return from Critical Interrupt Instruction Return from Interrupt Instruction Instruction Side Machine Check Instruction Side TLB Miss Instruction Side Interrupt Instruction Stuff Overrun 1 Processor Wait State Data Side TLB Miss Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Bit(s) 31-14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Name Reserved. Description Instruction Side Interrupt Data Side TLB Miss Instruction Side TLB Miss Reserved Protection Error Alignment Error Illegal/Privileged/Trap Instruction Exception System Call Return from Interrupt Instruction Return from Critical Interrupt Instruction Instruction Side Machine Check Processor Wait State Instruction Stuff Overrun Processor Stopped The processor is in a wait state. The debug port has attempted to insert an instruction into the processor via the JTAG Instruction Stuff Buffer (JISB) and it was not accepted by the processor. The instruction must be reloaded into the JISB. Reserved. Processor Core (PCORE) Page 474 of 676 pnr25.chapt05.01 August 14, 2000 Processor Stopped 0 Protection Error Alignment Error System Call Reserved IBM3206K0424 Preliminary IBM Processor for Network Resources 17.13: PCORE JTAG Instruction Stuff Buffer The PCORE JTAG Instruction Stuff Buffer is used to insert an instruction into the processor for execution. Length Type Address Power on Reset value Restrictions 32 bits Read/Write XXXX 4208 X'00 00 00 00' None User Defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Instruction Name 9 8 7 6 5 4 3 2 1 0 Description Instruction to be passed from the JTAG/PCI debug interface to the core GPRs. pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 475 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.14: PCORE JTAG Debug Data Register The PCORE JTAG Debug Data Register enables passing data between the JTAG/PCI debug port and the general purpose registers of the processor core. Length Type Address DCR Address Power on Reset value Restrictions 32 bits Read/Write XXX 420C TBD X'00 00 00 00' None User Defined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Data Name 9 8 7 6 5 4 3 2 1 0 Description Data to be passed to/from the JTAG/PCI debug interface to the core GPRs. Processor Core (PCORE) Page 476 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.15: PCORE Cobra Core Boot Address The PCORE Cobra Core Boot Address provides Cobra Core its boot time address. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write XXXX 4018 X'FF F0 01 00' None This is the PCORE register. It is used to provide the address that is used to fetch the first instruction. Disable EVPR/IP override HID/MSR on Boot 9 8 7 6 5 4 3 2 1 Description This is the address the processor will use at boot time. Override MSR settings on System Reset Exception to use all of the PCORE Cobra Core Boot Address. Reserved. Boot Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-2 1 0 Boot Address Disable EVPR/IP override HID/MSR on Boot Reserved Name pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 477 of 676 Reserved 0 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.16: PCORE Cobra Core Access Priority Control Register The PCORE Cobra Core Access Priority Control Register provides Cobra Core defined status information about PCORE. It is used to control the order and priority of access to the various memory subsystems that the Cobra Core has access to. It is to be set up at initialization time an not dynamically changed. Length Type DCR Address Power on Reset value Restrictions 28 bits Read/Write XXXX 401C X'01 E4 E4 E4' For each controller accessed, the values cannot be duplicated. That is, all the priorities to a given target subsystem must be unique. Write Around FIFO - Control Memory Access Priority Write Around FIFO - Packet Memory Access Priority 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 27-26 25 24 23-22 21-20 19-18 17-16 15-14 Reserved ICache Register Access Priority DCache Register Access Priority FDMA - Packet Memory Access Priority DCache - Packet Memory Access Priority ICache - Packet Memory Access Priority Name Reserved 9 8 7 6 5 4 3 2 1 Write Around FIFO - PCI Master Access Priority 0 pnr25.chapt05.01 August 14, 2000 DCache - Control Memory Access Priority DCache - Packet Memory Access Priority ICache - Control Memory Access Priority ICache - Packet Memory Access Priority FDMA - Control Memory Access Priority FDMA - Packet Memory Access Priority DCache - PCI Master Access Priority Description This sets the priority into the IBM3206K0424 register port. Zero is low priority; one is high priority. This sets the priority into the IBM3206K0424 register port. Zero is low priority; one is high priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. Write Around FIFO - Packet Memory Access This sets the priority of access to Packet Memory. Zero is the lowest priority; Priority three is the highest priority. FDMA - Control Memory Access Priority This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. Processor Core (PCORE) Page 478 of 676 ICache - PCI Master Access Priority FDMA - PCI Master Access Priority DCache Register Access Priority ICache Register Access Priority Reserved IBM3206K0424 Preliminary Bit(s) 13-12 11-10 9-8 7-6 5-4 3-2 1-0 Name DCache - Control Memory Access Priority ICache - Control Memory Access Priority Write Around FIFO - Control Memory Access Priority FDMA - PCI Master Access Priority DCache - PCI Master Access Priority ICache - PCI Master Access Priority IBM Processor for Network Resources Description This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. This sets the priority of access to Packet Memory. Zero is the lowest priority; three is the highest priority. Write Around FIFO - PCI Master Access Pri- This sets the priority of access to Packet Memory. Zero is the lowest priority; ority three is the highest priority pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 479 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.17: PCORE Transaction Dead Man Timer Value Registers These registers are used to load timers that count to zero from the value loaded in this register. The maximum wait for an I/O transaction is about 2ms when this is set to X'FFFF'. The value of this register is written into the corresponding timer after the transaction is initiated with the target. It continues to then count down until the target responds or zero is reached in the timer. When the timer reaches zero, a status bit is set and action can be taken from there. Length Type Address 16 bits Read/Write PCI Master Dead Man Timer Value IBM3206K0424 Register Dead Man Timer Value Control Memory Dead Man Timer Value Packet Memory Dead Man Timer Value DCR Primitive Access Dead Man Timer Value Power on Reset value Restrictions X'FFFF' None XXXX 4020 XXXX 4024 XXXX 4028 XXXX 402C XXXX 40F8 Processor Core (PCORE) Page 480 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.18: PCORE High Priority Access Timer Value Registers These registers are used to load timers that count to zero from the value loaded in this register. The maximum wait for an I/O transaction is about 2ms when this is set to X'FFFF'. The value of this register is written into the corresponding timer after the transaction is initiated with the target. It will continue to then count down until the target responds or zero is reached in the timer. When the timer reaches zero, a status bit is set and action can be taken from there. Length Type Address 16 bits Read/Write Control Memory Dead Man Timer Value Packet Memory Dead Man Timer Value Power on Reset value Restrictions X'FFFF' None TBD TBS 17.19: PCORE Transaction Dead Man Timer Register These timers are used to time transactions that are valid but the target does not respond right away. The timer counts on a 7.5 ns time base. The maximum wait for an I/O transaction is about 2ms when the timer counts down from X'FFFF'. This timer counts down to zero from the values set in the value register. When zero is reached, the transaction is considered broken and the request will be acknowledged back to the requestor. Length Type Address 16 bits Read PCI Master Dead Man Timer Value XXXX 40E0 IBM3206K0424 Register Dead Man Timer Value XXXX 40E4 Control Memory Dead Man Timer Value Packet Memory Dead Man Timer Value DCR Primitive Access Dead Man Timer Value Power on Reset value Restrictions X'FFFF' None XXXX 40E8 XXXX 40EC XXXX 40F0 17.20: PCORE IBM3206K0424 Shadow Status Register This register is used to shadow the INTST Interrupt Source. The purpose of this register is to allow polling for IBM3206K0424 interrupts without having to use the PCI bus. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'208' X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 481 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.21: PCORE IBM3206K0424 Packet Last Write with Error Address This register is used to shadow the INTST Interrupt Source. The purpose of this register is to store the address associated with the previous virtual write error. Length Type Address Power on Reset value Restrictions 32 bits Read X'260' X'00 00 00 00' None 17.22: PCORE IBM3206K0424 RXQUE Master Status Register This register is used to shadow the RXQUE Master Status Register. The purpose of this register is to allow fast access to RXQUE's Master Status Register without having to use the regular register interface. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'20F' X'00 00 00 00' None 17.23: PCORE IBM3206K0424 RXQUE Enabled Status Register 1 This register is used to shadow the RXQUE Enabled Status Register 1. The purpose of this register is to allow fast read access of the RXQUE Enabled Status Register 1 without having to use the normal IBM3206K0424 register interface. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'250' X'00 00 00 00' None Processor Core (PCORE) Page 482 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.24: PCORE IBM3206K0424 RXQUE Enabled Status Register 2 This register is used to shadow the RXQUE Enabled Status Register 1. The purpose of this register is to allow fast read access of the RXQUE Enabled Status Register 2 without having to use the normal IBM3206K0424 register interface. Length Type Address Power on Reset value Restrictions 32 bits Read X'251' X'00 00 00 00' None 17.25: PCORE IBM3206K0424 RXQUE Upper Queues Status Register This register is used to shadow the RXQUE Upper Queues Status Register. The purpose of this register is to allow fast read access of the RXQUE Upper Queues Status Register without having to use the normal IBM3206K0424 register interface. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'252' X'00 00 00 00' None 17.26: PCORE IBM3206K0424 RXQUE Lower Queues Status Register This register is used to shadow the RXQUE Lower Queues Status Register. The purpose of this register is to allow fast read access of the RXQUE Lower Queues Status Register without having to use the normal IBM3206K0424 register interface. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'253' X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 483 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.27: PCORE DMAQS Master Status Register This register is used to shadow the DMAQS Master Status Register. The purpose of this register is to allow fast read access of the DMAQS Master Status Register without having to use the normal IBM3206K0424 register interface. Length Type Address Power on Reset value Restrictions 32 bits Read X'257' X'00 00 00 00' None 17.28: PCORE DMAQS Enabled Status Register This register is used to shadow the DMAQS Master Status Register. The purpose of this register is to allow fast read access of the DMAQS Master Status Register without having to use the normal IBM3206K0424 register interface. Length Type Address Power on Reset value Restrictions 32 bits Read X'25B' X'00 00 00 00' None 17.29: PCORE RXQUE Queue Length Registers The PCORE RXQUE Queue Length Registers provide event enqueue queue lengths to the Cobra Core. Reads from this address will return event queue lengths from RXQUE. Length Type Address Power on Reset value Restrictions 32 bits Read/Write X'220' - X'22F' X'00 00 00 00' None Processor Core (PCORE) Page 484 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.30: PCORE DMAQS Queue Length Registers The PCORE DMAQS Queue Length Registers provide DMAQS queue lengths to the Cobra Core. Reads from this address will return DMAQS queue lengths from DMAQS. Length Type Address Power on Reset value Restrictions 32 bits Read/Write X'254' - X'256' X'00 00 00 00' None 17.31: PCORE Interrupt Enable Register This register is used to enable bits from the PCORE Status Register and potentially generate interrupts to the control processor. When both a bit in this register and the corresponding bit(s) in the PCORE Status Register are set, the PCORE interrupt to PCINT will be enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See PCORE Status Register on page 467 for the bit descriptions. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 4010 and 014 X'00 00 80 00' None 17.32: PCORE User Interrupt Enable This register is used to enable an interrupt based on bits from the corresponding PCORE User Status Register and potentially generate interrupts to the control processor. When both a bit in this register and the corresponding bit(s) in the [TBD] register are set, the PCORE status bit(s) will be set in the corresponding PCORE User Status Register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See PCORE User Status Register on page 468 for the bit descriptions. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set X'204 and 205' X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 485 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.33: PCORE Cobra Core Interrupt Enable Register This register is used to enable bits from the PCORE Cobra Core External Status Register and generate interrupts to the Cobra Core processor. When both a bit in this register and the corresponding bit(s) in the PCORE Cobra Core External Status Register are set, the Cobra Core interrupt to the Cobra Core core will be enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See PCORE Status Register on page 467 for the bit descriptions. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set X'206' - X'207' X'00 00 00 00' None 17.34: PCORE Cobra Core External Machine Check Enable Register This register is used to enable bits from the PCORE Cobra Core External Machine Check Status Register and generate machine checks to the Cobra Core processor. When both a bit in this register and the corresponding bit(s) in the PCORE Cobra Core External Machine Check Status Register are set, the requisite Cobra Core Machine Check to the Cobra Core core will be enabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. See PCORE Status Register on page 467 for the bit descriptions. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set X'25E' - X'25F' X'00 00 00 00' None 17.35: PCORE Error Lock Enable Register The PCORE Error Lock Enable Register provides the ability to halt PCORE when the corresponding status bit in the status register is set and locking is enabled. When a bit in this register corresponds to a bit that is set in the status register, the state machines in PCORE will be held in idle state until the lock is disabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 4030 and 034 X'00 00 FE 9F' None Processor Core (PCORE) Page 486 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.36: PCORE User Error Lock Enable Register The PCORE User Error Lock Enable Register provides the ability to halt PCORE when the corresponding status bit in the User Status Register is set and locking is enabled. When a bit in this register corresponds to a bit that is set in the Status Register, the state machines in PCORE will be held in idle state until the lock is disabled. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type Address Power on Reset value Restrictions 32 bits Clear/Set XXXX 4038 and 03C X'FF FF FF FF' None 17.37: PCORE RXQUE Event Interface Enqueue Register The PCORE RXQUE Event Interface Enqueue Register provides event enqueue interface for the Cobra Core. Writes to this address will enqueue an event to an RXQUE queue. Length Type Address Power on Reset value Restrictions 32 bits Read/Write X'230 - X'23F' X'00 00 00 00' None Bit(s) 31-7 6-0 Event Data Name User Defined Event Data TBD Processor Event Signature Description Event Signature 17.38: PCORE DMAQS DMA Enqueue Register The PCORE DMAQS DMA Enqueue Register provides DMAQS enqueue interface for the Cobra Core. Writes to this address will enqueue an event to an RXQUE queue. Length Type Address Power on Reset value Restrictions 32 bits Read/Write X'258 - X'25A' X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 487 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.39: PCORE RXQUE Event Interface Deque Register The PCORE RXQUE Event Interface Deque Register provides event deque interface for the Cobra Core. Reads from this address return an event. Length Type Address Power on Reset value Restrictions 32 bits Read X'240 - X'24F' X'00 00 00 00' None 17.40: PCORE Cobra SPR Read Data Access Register The PCORE Cobra SPR Read Data Access Register stores the data from the requested Cobra facility on a read. These are message passing facilities. They are used for inter-device communication. These facilities, with their control register bits, allow for either interrupt or polling-based message passing from the Cobra Core to a PCI bus device. Length Type Address Power on Reset value Restrictions 32 bits Read Only XXXX 4040 X'00 00 00 00' None 17.41: PCORE Cobra SPR Write Data Access Register This register stores the data from the PCIrequested Cobra facility on a read. These are message passing facilities. They are used for inter-device communication. These facilities with their control register bits, allow for either interrupt or polling-based message passing from the Cobra Core to a PCI bus device. Length Type Address Power on Reset value Restrictions 32 bits Write Only XXXX 40F4 X'00 00 00 00' None Processor Core (PCORE) Page 488 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.42: PCORE Cobra SPR Access Address Register This is the PCORE SPR Access Address Register. It is used to access the internal facilities in Cobra. This includes SPR/DCR and Debug facilities. The address is for a facility and represents a four-byte access. Length Type Address Power on Reset value Restrictions Address Type 32 bits Read/Write XXXX 4044 X'80 00 00 00' None Reserved Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) Name 9 8 7 6 5 4 3 2 1 0 Description These bits describe the address type. `00' Reserved `01' SPR Access `10' DCR Access `11' Register/Debug Access Reserved Address of Target Register. 31-30 Address Type 29-10 9-0 Reserved Address pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 489 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.43: PCORE Address Translation Offset Address Facilities The PCORE Address Translation Offset Address Facilities provides the offset that is added to the Cobra Real Address to create the target subsystem address. When an address is issued from the Cobra Core core it is accompanied by four target translation bits. The translation bits indicate which translation facility is to be used to translate the processor "real" physical address into a target system actual address. This grouping provides for the offset addresses for each target memory system. The offset is added to the Cobra Real Address to create the target system address. The following is a list of targets, each with their own translation facilities. '0000' '0001' '0010' '0011' '0100' '0101' '0110' '0111' '1000' '1001' '1010' '1011' '1100' '1101' '1110' '1111' OCM (Translation provided for in the MMUs) Packet Memory View 0 Packet Memory View 1 Packet Memory View 2 IBM3206K0424 Registers Control Memory View 0 Control Memory View 1 Control Memory View 2 PCI Master Access (Non IBM3206K0424) View 0 PCI Master Access (Non IBM3206K0424) View 1 PCI Master Access (Non IBM3206K0424) View 2 PCI Master Access (Non IBM3206K0424) View 3 Control/Packet View 0 Control/Packet View 1 Control/Packet View 2 Control/Packet View 3 PCORE Address Translation Offset Address Facilities: Length Type Address 32 bits Read/Write Packet Memory Offset View 0 Packet Memory Offset View 1 Packet Memory Offset View 2 IBM3206K0424 Registers Offset View 0 Control Memory Offset View 0 Control Memory Offset View 1 Control Memory Offset View 2 PCI Master Offset View 0 PCI Master Offset View 1 XXXX 4048 XXXX 404C XXXX 4050 XXXX 4054 XXXX 4058 XXXX 405C XXXX 4060 XXXX 4064 XXXX 4068 Processor Core (PCORE) Page 490 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources PCI Master Offset View 2 (R)pratbAa./Pci Master Offset View 3 (R)pratbBa./Control/Packet Memory Offset View 0 (R)pratbCa./Control/Packet Memory Offset View 1 (R)pratbDa./Control/Packet Memory Offset View 2 (R)pratbEa./Control/Packet Memory Offset View 3 Power on Reset value Restrictions X'00000000' None XXXX 406C 17.44: PCORE PCI 64 Bit Address Translation Facilities The PCORE PCI 64 Bit Address Translation Facilities provide the upper thirty-two bits of address in 64-bit addressing mode. When an access is issued to the PCI Master Interface in 64-bit addressing mode, these registers are used to create the upper 32 bits of the 64-bit address. Length Type Address/Storage Unit 32 bits Read/Write Upper 32 Address Bits PCI Master View 0 Upper 32 Address Bits PCI Master View 1 Upper 32 Address Bits PCI Master View 2 Upper 32 Address Bits PCI Master View 3 Power on Reset value Restrictions X'00000000' None XXXX 4084 XXXX 4088 XXXX 408C XXXX 4090 pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 491 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.45: PCORE PCI Master Target Tag Controls The PCORE PCI Master Target Tag Controls contains the control for each PCI Tag/View. This register contains bits for each of the four PCI Master Views. Length Type DCR Address Power on Reset value Restrictions Assume 64 bit Xfer View 3 Assume 32 bit Xfer View 3 32 bits Read/Write XXXX 40FC X'06 06 06 06' None Assume 64 bit Xfer View 2 Assume 32 bit Xfer View 2 Assume 64 bit Xfer View 1 Assume 32 bit Xfer View 1 Assume 64 bit Xfer View 0 Assume 32 bit Xfer View 0 2 1 Transfer Type View 3 Transfer Type View 2 Transfer Type View 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-30 29 28 27 26 Reserved Swap bytes View 3 Swap Words View 3 Assume 64 bit Xfer View 3 Assume 32 bit Xfer View 3 Name Reserved 9 8 7 6 5 4 3 Transfer Type View 0 0 Swap Words View 3 Swap Words View 2 Swap Words View 1 Description When set, this bit tells the PCI Master Logic to do byte swapping. When set, this bit tells the PCI Master to do word swapping. When set, this bit tells the PCI Master Logic to assume a 64-bit data access. When set, this bit tells the PCI Master Logic to assume a 32-bit data access. These bits indicate the transaction type. '00' Config Cycle '01' I/O Cycle '1-' Memory Cycle Reserved When set, this bit tells the PCI Master Logic to do byte swapping. When set, this bit tells the PCI Master to do word swapping. When set, this bit tells the PCI Master Logic to assume a 64-bit data access. When set, this bit tells the PCI Master Logic to assume a 32-bit data access. These bits indicate the transaction type. '00' Config Cycle '01' I/O Cycle '1-' Memory Cycle Reserved When set, this bit tells the PCI Master Logic to do byte swapping. When set, this bit tells the PCI Master to do word swapping. When set, this bit tells the PCI Master Logic to assume a 64 bit data access. pnr25.chapt05.01 August 14, 2000 25-24 Transfer Type View 3 23-22 21 20 19 18 Reserved Swap bytes View 2 Swap Words View 2 Assume 64 bit Xfer View 2 Assume 32 bit Xfer View 2 17-16 Transfer Type View 2 15-14 13 12 11 Reserved Swap bytes View 1 Swap Words View 1 Assume 64 bit Xfer View 1 Processor Core (PCORE) Page 492 of 676 Swap Words View 0 Swap bytes View 3 Swap bytes View 2 Swap bytes View 1 Swap bytes View 0 User Defined Reserved Reserved Reserved IBM3206K0424 Preliminary Bit(s) 10 Name Assume 32 bit Xfer View 1 IBM Processor for Network Resources Description When set, this bit tells the PCI Master Logic to assume a 32 bit data access These bits indicate the transaction type. '00' Config Cycle '01' I/O Cycle '1-' Memory Cycle Reserved When set, this bit tells the PCI Master Logic to do byte swapping. When set, this bit tells the PCI Master to do word swapping. When set, this bit tells the PCI Master Logic to assume a 64 bit data access. When set, this bit tells the PCI Master Logic to assume a 32 bit data access. These bits indicate the transaction type '00' Config Cycle '01' I/O Cycle '1-' Memory Cycle 9-8 Transfer Type View 1 7-6 5 4 3 2 Reserved Swap bytes View 0 Swap Words View 0 Assume 64 bit Xfer View 0 Assume 32 bit Xfer View 0 1-0 Transfer Type View 0 pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 493 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.46: PCORE Last Packet Address Register The PCORE Last Packet Address Register is the last address to the Packet Memory bus at the time of the hang condition. When the system locks up, this register holds the last Packet Memory address that was or is currently being presented to the Packet Memory subsystem. Length Type Address Power on Reset value Restrictions 32 bits Read XXXX 4094 X'FF FF FF FC' None 17.47: PCORE Last Control Address Register The PCORE Last Control Address Register is the last address to the Control Memory bus at the time of the hang condition. When the system locks up, this register holds the last Control Memory address that was or is currently being presented to the Control Memory subsystem. Length Type Address Power on Reset value Restrictions 32 bits Read XXXX 4098 X'FF FF FF FC' None 17.48: PCORE Last PCI Lower Address Register The PCORE Last PCI Lower Address Register is the last address to the PCI bus at the time of the hang condition. When the system locks up, this register holds the last PCI bus address that was or is currently being presented to the Control Memory subsystem. Length Type Address Power on Reset value Restrictions 32 bits Read XXXX 409C X'FF FF FF FC' None Processor Core (PCORE) Page 494 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.49: PCORE Last Register Address Register The PCORE Last Register Address Register is the last address to the PCI bus at the time of the Hang Condition. When the system locks up, this register holds the last PCI bus address that was or is currently being presented to the Control Memory subsystem. Length Type Address Power on Reset value Restrictions 32 bits Read XXXX 40A0 X'FF FF FF FC' None 17.50: PCORE SRAM Base Address The SRAM Base Address register is used to select the base address of the 4K byte window to access the SRAM. Length Type Address Power on Reset value Restrictions 32 bits (17:12) Active Read/Write XXXX 40A4 X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 495 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.51: PCORE Read Data Transfer Buffers The PCORE Read Data Transfer Buffers hold the read data that is being transferred from one of the target subsystems and the Cobra Core. Eight bytes are buffered on the interfaces except for the IBM3206K0424 register interface which buffers four bytes. Length Type Address 32 bits Read PCI Upper Read Data Transfer Buffer PCI Lower Read Data Transfer Buffer Packet Upper Read Data Transfer Buffer Packet Lower Read Data Transfer Buffer Control Upper Read Data Transfer Buffer Control Lower Read Data Transfer Buffer XXXX 40A8 XXXX 40AC XXXX 40B0 XXXX 40B4 XXXX 40B8 XXXX 40BC IBM3206K0424 Register Space Read Data Transfer XXXX 40C0 Buffer Power on Reset value Restrictions X'00000000' None 17.52: PCORE Write Data Transfer Buffers The PCORE Write Data Transfer Buffers hold the data that is being transferred between the Cobra Core and one of the target subsystems. Eight bytes can be stored for each target subsystem, with the exception of the IBM3206K0424 Register Target which holds just four bytes. Length Type Address 32 bits Read PCI Upper Write Data Transfer Buffer PCI Lower Write Data Transfer Buffer Packet Upper Write Data Transfer Buffer Packet Lower Write Data Transfer Buffer Control Upper Write Data Transfer Buffer Control Lower Write Data Transfer Buffer XXXX 40C4 XXXX 40C8 XXXX 40CC XXXX 40D0 XXXX 40D4 XXXX 40D8 IBM3206K0424 Register Space Write Data Transfer XXXX 40DC Buffer Power on Reset value Restrictions X'00000000' None Processor Core (PCORE) Page 496 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.53: PCORE Polling Register The PCORE Polling Register provides status information to PCORE about IBM3206K0424 operations. It allows PCORE to poll specific IBM3206K0424 status without using PCI bus bandwidth. Length Type DCR Address Power on Reset value Restrictions 32 bits Read X'20E' X'00 00 00 00' During normal operations, if a status bit is cleared, it will be reset if the condition that is causing it is still present. Control Memory Locked Packet Memory Locked Memory Locked Virtual Lock 1 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-5 4 3 2 1 0 Reserved Memory Locked Control Memory Locked Packet Memory Locked Virtual Lock Arbit Lock Name Reserved. Memory is locked. Control Memory is locked. Packet Memory is locked. VIMEM is the locker of memory. Arbit is the locker of memory. 9 8 7 6 5 4 3 2 Description 17.54: PCORE Integer Input Rate Conversion Register This register is the integer input port for the rate conversion logic. An integer rate is placed in this register. The on board logic converts it to an ABR rate format. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write X'20B' X'00 00 00 00' None pnr25.chapt05.01 August 14, 2000 Processor Core (PCORE) Page 497 of 676 Arbit Lock 0 IBM3206K0424 IBM Processor for Network Resources Preliminary 17.55: PCORE ABR Output Rate Register This register is the output port of the rate conversion logic. An integer rate was placed in the Integer Input Register. The logic converts it to an ABR rate and places the result in this register. Length Type DCR Address Power on Reset value Restrictions 16 bits Read X'20C' X'00 00' None 17.56: PCORE Debug States Control This register serves as the PCORE control for external debug states. The INTST Debug states control for the address range desired must be set to select these PCORE state bits. If that is done, then this register acts to select the four ranges. See bit descriptions below. Length Type Address Power on Reset value Restrictions Entity State Mux Control 4 (Hardware debug) 32 bits Read/Write XXXX 431C X'0000 0000' None Entity State Mux Control 3 (Hardware debug) Entity State Mux Control 2 (Hardware debug) Entity State Mux Control 1 (Hardware debug) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 23-16 15-8 Name Entity State Mux Control 4 (Hardware debug) Entity State Mux Control 3 (Hardware debug) Entity State Mux Control 2 (Hardware debug) 9 8 7 6 5 4 3 2 1 0 Description Select of these bits allows internal state machines, counters, etc., to show up on chip outputs ENSTATE(63 down to 48). Selection encoding is the same as mux 1 control. Select of these bits allow internal state machines, counters, etc., to show up on chip outputs ENSTATE(47 down to 32). Selection encoding is the same as mux 1 control. Select of these bits allow internal state machines, counters, etc., to show up on chip outputs ENSTATE(31 down to 16). Selection encoding is the same as mux 1 control. Select of these bits allow internal state machines, counters, etc., to show up on chip outputs ENSTATE(15 down to 0). X'00' Disabled (no transition on outputs) X'01' Select 15-0 states X'40'-X'FF' Reserved 7-0 Entity State Mux Control 1 (Hardware debug) Processor Core (PCORE) Page 498 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 17.57: PCORE Debug States Config This register serves as the PCORE configuration for external debug states. The INTST Debug states control for the address range desired must be set to select these PCORE state bits. If that is done, then this register acts to select the characteristics according to the bit descriptions below. Length Type DCR Address Power on Reset value Restrictions Bpu Config (1-0) Lsu Selector(1) Lsu Selector(0) 2 1 8 bits Read/Write XXXX 4320 X'00' None Reg Selector 7 6 Bit(s) 7 6 5-4 3-2 1 0 5 4 3 Name LSU selector(1) Reg selector Bpu Config (1-0) Reserved Lsu selector(0) Fxu selector TBD TBD TBD Reserved TBD TBD Fxu Selector 0 Description pnr25.chapt05.01 August 14, 2000 Reserved Processor Core (PCORE) Page 499 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 18: PowerPC On-Chip Memory (PPOCM) Entity The PPOCM entity is comprised of several SRAM arrays that provide a xxxK memory that may be used by the internal processor or by the IBM3206K0424. Also included in PPOCM is a DMA controller that the processor may use to do bulk data moves between the SRAM arrays and Control Memory, Packet Memory, or memory on an external PCI device. The PPOCM arrays will subsequently referred to as on-chip memory and the three external memories (control, packet, PCI) just mentioned will subsequently be referred to collectively as off-chip memory. DMA Controller The DMA controller moves data in eight byte aligned, eight byte portions. In real addressing mode, up to 64K bytes may be transferred at once. In virtual addressing mode, there are more restrictions. The DMA must remain within the virtual 4K page for both the PPOCM array address and the off-chip memory address. 18.1: PPOCM Control Register This register contains information which controls the functions of the entity. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write 100 AND 01 X'00000000' None DMA Read Not Write 2 1 DMA Blocking Mode Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-4 Reserved Name Rserved 9 8 7 6 5 4 3 Description 3-2 DMA Blocking Mode These bits control how non-DMA accesses to PPOCM are handled while a DMA is in progress. They are encoded as follows: '00' Non-DMA PPOCM accesses are held off until the DMA is complete. '01' Non-DMA PPOCM accesses are held off only if the requester is attempting to use an array that will be involved in the DMA. '10' Reserved '11' Reserved Setting this bit will indicate the DMA being set up is to transfer data from off-chip memory into PPOCM. Clearing this bit indicates the DMA should transfer data from PPOCM to off-chip memory. 1 DMA Read Not Write PowerPC On-Chip Memory (PPOCM) Entity Page 500 of 676 pnr25.chapt05.01 August 14, 2000 Start DMA 0 IBM3206K0424 Preliminary Bit(s) 0 Start DMA Name IBM Processor for Network Resources Description Setting this bit initiates the DMA operation. This bit will automatically clear when the DMA is completed. 18.2: PPOCM Status Register This register contains status information that can be used to generate interrupts. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write 102 AND 03 X'00000000' None On-Chip Address Virtual Mode Page Violation Off-Chip Address Virtual Mode Page Violation DMA Beyond Bounds of On-Chip Memory Real Addressing Mode Length Error Virtual Mode Length Error Addressing Mode Error Zero Length DMA Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-9 8 7 6 5 4 3 2 Reserved Zero Length DMA DMA Beyond Bounds of On-Chip Memory On-Chip Address Virtual Mode Page Violation Off-Chip Address Virtual Mode Page Violation Virtual Mode Length Error Real Addressing Mode Length Error Addressing Mode Error Name Reserved 9 8 7 6 5 4 3 2 1 Description This bit, set to '1', indicates that a DMA with a length of zero was attempted. This bit, set to '1', indicates that the on-chip address plus the DMA length yields a value that exceeds the address pace of the on-chip memory. This bit, set to '1', indicates that the on-chip virtual address provided to PPOCM in combination with the DMA length results in a virtual page cross. This bit, set to '1', indicates that the off-chip virtual address provided to PPOCM in combination with the DMA length results in a virtual page cross. This bit, set to '1', indicates that a virtual address mode DMA was started and the value in the DMA length register is greater than 4K. This bit, set to a '1,' indicates that a real address mode DMA was started and the value in the DMA length register is greater than 64K. This bit, set to a '1,' indicates that the off-chip memory and on-chip address written to the DMA address registers must be either both real or both virtual. pnr25.chapt05.01 August 14, 2000 PowerPC On-Chip Memory (PPOCM) Entity Page 501 of 676 Complete 0 Timeout IBM3206K0424 IBM Processor for Network Resources Bit(s) 1 0 Timeout Complete Name Description This bit, set to a '1,' indicates that the DMA timer expired. This bit, set to a '1,' indicates that the DMA completed. The other bits in this register being a '0' will indicate a good completion. Preliminary 18.3: PPOCM Interrupt Enable Register This register enables the bits of the Status Register to generate an interrupt. The bits of this register correspond to the bits of the status register. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write 104 AND 05 X'00000000' None 18.4: PPOCM DMA Off-Chip Effective Address Register This register provides the DMA controller the effective address of the off-chip portion of the DMA. Length Type DCR Address Power on Reset value Restrictions 32 bits Read/Write 106 X'00000000' None Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-3 2-0 Reserved Reserved Name Reserved Reserved 9 8 7 6 5 4 3 2 1 0 Description PowerPC On-Chip Memory (PPOCM) Entity Page 502 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 18.5: PPOCM DMA On-Chip Effective Address Register This register provides the DMA controller the effective address of the on-chip portion of the DMA. Length Type DCR Address Power on Value Restrictions 32 bits Read/Write 107 X'00000000' None Reserved Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-3 2-0 Reserved Reserved Name Reserved Reserved 9 8 7 6 5 4 3 2 1 0 Description pnr25.chapt05.01 August 14, 2000 PowerPC On-Chip Memory (PPOCM) Entity Page 503 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 18.6: PPOCM DMA Length Register This register provides the DMA controller the length of the DMA. The maximum DMA length in real addressing mode is X'00010000' (64K). The maximum DMA length in virtual addressing mode is X'00001000' (4K). Length Type DCR Address Power on Value Restrictions 32 bits Read/Write 108 X'00000000' None Reserved DMA Length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 16-0 Reserved DMA Length Name Reserved 9 8 7 6 5 4 3 2 1 0 Description Only bits 16-3 are writable as DMAs are done only in eight-byte segments. 18.7: PPOCM DMA Timeout Timer Register This register is compared to a timer that begins running when bit 0 of the control register is set to '1'. When the timer reaches the value in this register, the DMA is terminated and a status bit is set. The default value of X'FFFFFF' results in a timeout value of 125 ms. Length Type DCR Address Power on Value Restrictions Reserved 32 bits Read/Write 109 X'00FFFFFF' None DMA Length 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-24 23-0 Reserved DMA Length Name Reserved DMA timeout value 9 8 7 6 5 4 3 2 1 0 Description PowerPC On-Chip Memory (PPOCM) Entity Page 504 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 19: RS-232 Interface Logic (RS-232) The RS232 entity provides a means by which an external debugger and the processor core can communicate. The RS-232 operates a one-or four-byte wide basis. RS-232 Interface Logic Registers 19.1: RS-232 Control Register This register controls the operation of the RS-232 logic. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'210' AND 211' X'00000000' None Force DSR Active Internal Force CTS Active Internal Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-10 9 8 7 6 5 4 3 2 Reserved Byte Wide Mode Internal Wrap Mode Force RTS Active Force DSR Active Internal Force CTS Active Internal Stop Bits Parity Enable Odd/Even Parity Name Reserved 9 8 7 6 5 4 3 2 1 Description This bit set to '1' makes the port operate in byte-wide mode. When a transmit is started, only bits 7-0 of the transmit buffer are sent. A receive interrupt is generated whenever a byte is received. This bit set to '1' connects the transmit data stream to the receive data stream. This bit set to '1' forces RTS to be driven active, regardless of what the transmit state machine is doing. This bit set to '1' forces DSR internal to RS-232 to appear active, regardless of the DSR input's state. This bit set to '1' forces CTS internal to RS-232 to appear active, regardless of the CTS input's state. This bit set to '1' indicates the port should use two stop bits. This bit set to '0' indicates the port should use one stop bit. This bit set to '1' enables parity. If parity is enabled, this bit, set to '1', sets the parity type to odd. This bit set to '0' sets the parity type to even. pnr25.chapt05.01 August 14, 2000 RS-232 Interface Logic (RS-232) Page 505 of 676 RS-232 Port Enable 0 Internal Wrap Mode Force RTS Active Byte Wide Mode Odd/Even Parity Transmit Start Parity Enable Stop Bits IBM3206K0424 IBM Processor for Network Resources Bit(s) 1 0 Transmit Start RS-232 Port Enable Name Description This bit set to '1' initiates the transmission of what is in the transmit buffer. This bit is cleared by hardware when the transmission is complete. This bit set to '1' enables the RS-232 port. Preliminary 19.2: RS-232 Status Register This register controls the operation of the RS-232 logic. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'212 AND 213' X'00000000' None Transmit Complete Receive Complete 0 Framing Error Overrun Error 2 DSR Inactive CTS Inactive Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-7 6 5 4 3 2 1 0 Reserved DSR Inactive CTS Inactive Transmit Complete Framing Error Overrun Error Parity Error Receive Complete Name Reserved 9 8 7 6 5 4 3 Description This bit set to '1' indicates DSR has gone inactive. This bit set to '1' indicates CTS has gone inactive. This bit set to '1' indicates the current transmission has completed. This bit set to '1' indicates a framing error has been detected. This bit set to '0' indicates four bytes were received before the previous (one-byte mode) or four bytes (four-byte mode) had been read from the receive buffer. This bit set to '1' indicates a parity error has been detected. This bit set to '1' indicates data from a clean reception is in the receive buffer. RS-232 Interface Logic (RS-232) Page 506 of 676 pnr25.chapt05.01 August 14, 2000 Parity Error 1 IBM3206K0424 Preliminary IBM Processor for Network Resources 19.3: RS-232 Interrupt Enable Register This register contains bits corresponding to the bits in the RS-232 status register. If a bit in this register is set and the corresponding bit is set in the RS-232 status register, an interrupt is generated. Bits six through four generate a transmit interrupt and bits three through zero generate a receive interrupt. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power On Value: Restrictions 7 bits Read/Write X'214 AND 215' X'00000000' None 19.4: RS-232 Transmit Buffer This register contains the data to be sent over the RS-232 connection. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'216' X'00000000' None Transmit Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 Name Transmit Data Description 9 8 7 6 5 4 3 2 1 0 Data to be sent over link. Only bits 7-0 are sent in byte mode. The other bits are shifted, so the user can write all four bytes at once and just set the transmit bit four times. pnr25.chapt05.01 August 14, 2000 RS-232 Interface Logic (RS-232) Page 507 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 19.5: RS-232 Receive Buffer This register contains the data received over the RS-232 connection. Once this buffer is full, software has four byte receive times minimum to read it before an overrun condition can occur. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'217' X'00000000' None Receive Data 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit(s) 31-0 Name Receive Data Description Data received over the link. Only bits 7-0 are valid in byte mode. 19.6: RS-232 Baud Rate Register This register contains the value used to determine the baud rate. The value to place in this register can be determined by this formula: BaudRate = 133MHz/(8*(Baud Rate Register + 1)). Length Type DCR Address Power On Value Restrictions 16 bits Read/Write X'218' X'00000000' None Reserved Baud Rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 Name Reserved Reserved Suggested values: X'120' - 56600 X'1B0' - 38400 X'240' - 28800 X'360' - 19200 Description 9 8 7 6 5 4 3 2 1 0 15-0 Baud Rate RS-232 Interface Logic (RS-232) Page 508 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 19.7: RS-232 CTS/DSR Glitch Timer Rate This register contains the number of (baud rate/8) clocks CTS/DSR must be active/inactive before the state of CTS/DSR is considered valid. Transitions of shorter duration are assumed to be glitches. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'219' X'00000020' None Reserved Glitch Timer Rate 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-16 15-0 Name Reserved Glitch Timer Rate Reserved Description 9 8 7 6 5 4 3 2 1 0 19.8: RS-232 Reset Register This register resets the port. See Note on Set/Clear Type Registers on page 93 for more details on addressing. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'21A and 21B' X'00000000' None Reset 9 8 7 6 5 4 3 2 1 0 Description Reserved This bit set to '1' resets the port. The port will remain reset until this bit is cleared. RS-232 Interface Logic (RS-232) Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-1 0 Name Reserved Reset pnr25.chapt05.01 August 14, 2000 Page 509 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 19.9: RS-232 Error Forcing Register This register can be used by diagnostics in a wrap environment (external or internal) to force frame and parity errors. Overrun errors can be generated by sending four bytes, not reading the receive buffer, and sending four more bytes. Length Type DCR Address Power On Value Restrictions 32 bits Read/Write X'21C' X'00000000' None Force framing error 9 8 7 6 5 4 3 2 1 Description Reserved Setting this bit to a '1' forces the first frame bit to a B'0' on all transmits. Setting this bit to a '0' forces the receive logic to check for the opposite parity the transmit logic is using. Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-2 1 0 Reserved Name Force framing error Force parity error RS-232 Interface Logic (RS-232) Page 510 of 676 pnr25.chapt05.01 August 14, 2000 Force parity error 0 IBM3206K0424 Preliminary IBM Processor for Network Resources Entity 20: Reset and Power-on Logic (CRSET) This entity performs BIST and flush operations. Chip software resets can be controlled by this entity, as well as the chip clock control. Reset and Power-on Logic Registers 20.1: Reset Status Register This register is used to reflect the last type of reset was. A hardware reset will clear software reset status bits, but a software reset will not have an affect on the hardware status bits. Length Type Address POR Value Software Reset Value Restrictions PCI clock frequency change 8 bits Read/Write XXXX 0500 'DB00001' or 'DB00010', where B is the state of the BIST results, and D is the PLL phase detection. 'DB001QQ' or 'DB010QQ', where Q is the state of this bit before the software reset and B is the state of the BIST results. None PLL out-of-phase detect Software Reset/BIST Software Reset PCORE Reset BIST results POR Reset 1 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name PCI clock frequency change PLL out-of-phase detect BIST results PCORE Reset Software Reset Software Reset/BIST POR Reset Reserved 0 Description A value of '1' means that the real time PCI frequency calculator has detected a major change in frequency and has calculated new range bits for the PLL. A value of '1' means that the out-of-phase detector circuit has triggered. This is just an indicator and is normal operation. A value of '1' means that a failure occurred within the BIST checking logic. The PCORE entity has been reset via a software reset request (bit 3 of Software Reset Register). A Software Reset has occurred; the chip was flushed. A Software Reset has occurred; and BIST/flush was run. A POR Hardware Reset that flushed the chip has occurred. Reserved pnr25.chapt05.01 August 14, 2000 Reset and Power-on Logic (CRSET) Page 511 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 20.2: Software Reset Enable Register This register protects the Software Reset Register. If this register is not set, then a reset will not occur. Write a X'B4' to this register to enable software reset. A software reset will clear this register. Length Type Address POR Value Restrictions 8 bits Read/Write XXXX 0504 X'0' None 20.3: Software Reset Register This register generates a scan path flush reset of the chip, or software initiated run of BIST, with the exception of the registers in the reset entity. Length Type Address POR Value Restrictions 4 bit Write Only XXXX 0508 B'0' Writing to this register without first setting the Software Reset Enable Register will have no affect. The register will not be set, thus the order of writing the enable and the software reset is important; the enable must be written first. Additionally, all current operations being performed by the IBM3206K0424 must be terminated before doing a reset operation. A minimum number of enable bits to turn off would be bits four, five, and six in INTST Control Register and bit 2 in PCINT Config Word 1. Total Software Reset 3 2 Bit(s) 3 2 1 Software Reset 0 Name PCORE Processor Reset Total Software Reset Description Writing this bit to a '1' causes the internal processor core to reset. Writing this bit to a '1' causes software reset and will be cleared after the software reset has occurred. The config registers in PCINT will also be put to their reset state. Writing this bit to a '1' causes BIST to run and will be cleared after the software reset has occurred. This function is primarily for pre-loading the BIST registers to get more test coverage. Writing this bit to a '1' causes software reset and will be cleared after the software reset has occurred. The config registers in PCINT will not be affected by this reset. Run BIST Software Reset PCORE Reset 1 0 Reset and Power-on Logic (CRSET) Run BIST Page 512 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 20.4: Memory Type Register This register indicates the type of memory used for control and Packet Memory so that reset hardware will know how to properly preserve it during a reset. Length Type Address POR Value Restrictions Control Memory Type Packet Memory Type 4 bits Read/Write XXXX 050C X'0' None 3 2 Bit(s) 3-2 1-0 1 0 Name Packet Memory Type Control Memory Type Description Decodes the same as bits nine through eight of COMET/PAKIT Control Register on page 186. Decodes the same as bits nine through eight of COMET/PAKIT Control Register on page 186. pnr25.chapt05.01 August 14, 2000 Reset and Power-on Logic (CRSET) Page 513 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 20.5: CRSET PLL Range Debug Used to debug the PPL operation. Length Type Address POR Value 32 bits Read Only XXXX 0518 X'xxxxxxxx' PLL Range bit `1' (A) PLL Range bit `0' (A) PLL Range bit `1' (B) 1 PLL Range bit `0' (B) 0 TBD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-4 3 2 1 0 TBD PLL Range bit `1' (A) PLL Range bit `0' (A) PLL Range bit `1' (B) PLL Range bit `0' (B) Description 9 8 7 6 5 4 3 2 Reset and Power-on Logic (CRSET) Page 514 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 20.6: CRSET Control Register Used to control PCI frequency detection logic. Length Type Address POR Value 13 bits Read/Write XXXX 0510 X'0330' Encoded Control for PLL out-of-phase detection circuitry Disable the frequency change detection interrupt Enable PCORE IBM3206K0424 software reset Disable the out-of-phase detection interrupt Disable delay PCI RST# to the processor 12 11 10 Bit(s) 9 8 7 6 5 4 3 2 Encoded Control for Selecting Clk Speed 1 0 Description Setting this bit to a '1' will disable the function that delays a PCI bus reset to the IBM3206K0424 if a serial EPROM is attached and still busy accessing data from the prior reset. By disabling this function, any PCI requirement to tri-state the I/O drivers would be met, but EPROM initialization information would be lost. Setting this bit to a '1' will enable the PCORE entity to issue an IBM3206K0424 software reset. Setting this bit to a '1' will enable the PCORE entity to issue a processor unit reset. Setting this bit to a '1' will disable using the frequency change detection bit as an interrupt source to INTST. Setting this bit to a '1' will disable using the PLL lock output to make state transitions in the out-of-phase detection logic. These bits determine how much time buffering is allowed before an out-of-phase condition is detected. For a value of '000', a value of about 150 ps buffering is used. For each encoded increment value, an additional 150 ps is added. For example, the default value of three is about 600 ps of buffering. Setting this bit to a '1' will enable bits 2-0 to override the pffcfg(2-0) bits that are strapped at the card level. Enable PCORE processor unit reset Disable PLL lock control Name Disable delay PCI RST# to the IBM3206K0424 Enable PCORE IBM3206K0424 software reset Enable PCORE processor unit reset Disable the frequency change detection interrupt 12 11 10 9 8 7 Disable the out-of-phase detection Setting this bit to a '1' will disable using the out-of-phase detection bit as an interrupt interrupt source to INTST. Disable PLL lock control 6-4 Encoded Control for PLL out-of-phase detection circuitry 3 Enable bits 2-0 pnr25.chapt05.01 August 14, 2000 Enable bits 2-0 Reset and Power-on Logic (CRSET) Page 515 of 676 IBM3206K0424 IBM Processor for Network Resources Bit(s) 2-0 Name Description Preliminary Encoded Control for Selecting Clk These three bits have the same encoding as the chip I/O pffcfg(2-0) bits. Speed 20.7: Clock Control Register (Nibble Aligned) Used to disable clocks for power conservation and provide the Select A Clock function for MPEG and front end support. To change a nibble field in this register, always set it to '0' first, and then to the new value. Length Type Address POR Value Framer Tree Disabled (FRAMR) 29 bits Read/Write XXXX 0520 X'000E5532' Encoded Control for Encoded Transmit Logic Control for Reserved Encoded (LINKT) and Encoded (Encoded ConEncoded Control for Cell MPEG Control for BIST trol for PCORE Memory Clock Opportunity Clocking Logic Sonet Framer (FRAMR) Speed Clock Rate) Control Logic (CELLO) (MPEGT) Encoded Control for Receive Logic (LINKR) and Sonet Framer (FRAMR) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Name Framer Tree Disabled (FRAMR) 9 8 7 6 5 4 3 2 1 0 Bit(s) 28 27-24 23-20 Description When set, this bit will disable the clock tree to the Sonet Framer Logic. Reserved (for Encoded Control for Reserved BIST Clock Rate) Reserved (for Encoded Control for Reserved PCORE Clock Rate) Encoding of bits: X'D' Use an early version of the clock X'E' Use a nominal version of the clock X'F' Use a late version of the clock 19-16 Memory Clock Control 15-12 11-8 Encoded Control for Cell OpportuSame as bits 3-0. nity Logic (CELLO) Encoded Control for MPEG ClockSame as bits 3-0. ing Logic (MPEGT) Encoded Control for Transmit Logic (LINKT) and Sonet Framer (FRAMR) Same as bits 3-0. 7-4 Reset and Power-on Logic (CRSET) Page 516 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary Bit(s) Name IBM Processor for Network Resources Description Below is the encoded value of the bits that select a given clock. Always refer to "Select A Clock" Selection Matrix below for inputs supported for each clock out type. X'0' Turn this clock off. X'1' Use the external MPEG oscillator. X'2' Use the external RX clock. X'3' Use the external TX clock. X'4' Reserved X'5' Use the internal 15 ns clock. Assumes 33 or 66MHz PCI clock. X'6' Use the internal 30 ns clock. Assumes 33 or 66MHz PCI clock. X'7' Use the internal 60 ns clock. Assumes 33 or 66MHz PCI clock. X'8' Use the internal 120 ns clock. Assumes 33 or 66MHz PCI clock. X'9' Use the internal 240 ns clock. Assumes 33 or 66MHz PCI clock. X'A' Use the internal 480 ns clock. Assumes 33 or 66MHz PCI clock. X'B' Use the differential Receiver clock divided by eight. X'C' Use the differential Transmit clock divided by eight. X'D' Use the differential Receiver clock (chopped). X'E' Use the differential high speed receiver clock (divided by 8 and 50% duty cycle). 3-0 Encoded Control for Receive Logic (LINKR) and Sonet Framer (FRAMR) "Select A Clock" Selection Matrix Clock Frequency Base HS RX Rec Diff Osc RX Rec Diff Osc TX/8 Diff Osc RX/8 Diff Osc 480 ns 240 ns 120 ns 60 ns 30 ns 15 ns Reserved TX Osc RX Osc MPEG OSC OFF Control Bits X X X X 15-12 X X X X 11-8 X X X X 7-4 X X X X 3-0 X X X X X X X X X X X X X X X X X X X X X X X X X X CELLO BCO CCO MPEGT BMT CMT X X LINKT(TX) BTX CTX RTX LINKR(RX) BRX CRX RRX X'E' X'D' X'C' X'B' X'A' X'9' X'8' X'7' X'6' X'5' X'4' X'3' X'2' X'1' X'0' Nibble Code pnr25.chapt05.01 August 14, 2000 Reset and Power-on Logic (CRSET) Page 517 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 20.8: CBIST PRPG Results This is the PRPG results register, updated after BIST has run. It is used by the BIST function for chip test. Length Type Address POR Value 32 bits Read/Write XXXX 05B0 X'FFFFFFFF' 20.9: CBIST MISR Results This is the MISR results register, updated after BIST has run. It is used by the BIST function for chip test. Length Type Address POR Value 32 bits Read/Write XXXX 05B4 X'00000000' 20.10: CBIST BIST Rate This register holds a counter value that separates the time between when the A clock and the B clock are launched during BIST. This allows finer tuning to how much power BIST uses versus how much testing gets done within the time allowed. It is used by the BIST function for chip test. Length Type Address POR Value 3 bits Read/Write XXXX 05B8 X'0' 20.11: CBIST PRPG Expected Signature This is the PRPG signature register, which should be written by CRISCO code with the expected value of signature, based on the value in CBIST CYCT Load Value and the clock selected for BIST to run from. It is used by the BIST function for chip test. Length Type Address POR Value 32 bits Read/Write XXXX 05C0 X'FFFFFFFF' Reset and Power-on Logic (CRSET) Page 518 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 20.12: CBIST MISR Expected Signature This is the MISR Signature Register, which should be written by CRISCO code with the expected value of signature, based on the value in CBIST CYCT Load Value and the clock selected for BIST to run from. It is used by the BIST function for chip test. Length Type Address POR Value 32 bits Read/Write XXXX 05C4 X'00000000' 20.13: CBIST CYCT Load Value This register is the loaded value for the CBIST BIST Rate Register. The time for BIST to run can be computed by the following equation: (shift count) (c30 clock2) (cycle time). It is used by the BIST function for chip test. Length Type Address POR Value 18 bits Read/Write XXXX 05C8 X'00005800' pnr25.chapt05.01 August 14, 2000 Reset and Power-on Logic (CRSET) Page 519 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Entity 21: JTAG Interface Logic (CJTAG) The CJTAG entity contains logic to support a test access port (TAP) controller compliant with the IEEE 1149.1-1993 standard. The TAP controller is accessed via the following five pins: TCK Test Clock. All activity of the JTAG interface is clocked via TCK. Events occur on the rising or falling edge of TCK. TCK should have a maximum frequency of 20MHz. Test Mode Select. Test Mode Select is used to control state transitions in the TAP controller. These transitions occur on the rising edge of TCK. The BTR selected for TMS should be one with an internal pullup. Test Data In. Serial data input to the JTAG logic. The BTR selected for TDI should be one with an internal pullup. Test Data Out. Serial data output to the JTAG logic. Test Reset. Asynchronous, minus active reset to the TAP controller. Assertion of this input causes the TAP controller to reset and the JTAG instruction register to load the IDCODE instruction. It is preferable to have TRST be independent of any chip reset. With an independent reset, the JTAG logic can be reset, allowing the chip's state to be examined without having to reset the core logic. The BTR selected for TRST should be one with an internal pullup. TMS TDI TDO TRST The proper operation of these signals and the TAP controller is defined in the IEEE 1149.1-1993 standard. Scanning The TAP controller supports two types of scans: instruction scans and data scans. Instruction scans control the type of operation and select which (if any) scan chains are involved in the operation. Data scans generally clock the data on TDI into the selected scan chain. JTAG Interface Logic (CJTAG) Page 520 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 21.1: Instruction Format The processor's JTAG logic supports 32-bit instructions in one of two formats: the first format uses opcodes compliant with the IEEE standard; the other supports opcodes as defined by the Walnut chip that are compatible but not compliant with the IEEE standard. As an instruction is scanned in, status for the previous instruction is presented on TDO. Odd Parity Instruction OpCode Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-17 16 15-0 Instruction OpCode In compatible mode, this is odd parity over bits 15-0 Reserved Description 9 8 7 6 5 4 3 2 1 0 Reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-6 5 4 3 2 1-0 Reserved Walnut Compliant Mode. Bad Modifier Parity Detected. BIST Running. Reserved Hardwired to '01' as required by IEEE specification. Description 9 8 7 6 5 4 3 2 1 Hardwired to '01' as required by IEEE specification 0 Bad Modifier Parity Detected Walnut Compliant Mode BIST Running pnr25.chapt05.01 August 14, 2000 JTAG Interface Logic (CJTAG) Page 521 of 676 Reserved IBM3206K0424 IBM Processor for Network Resources Preliminary Instructions The following instructions are supported: 21.2: IDCODE Returns a 32-bit identification code when a data scan is performed. The IDCODE has the following structure: Opcode Version Number X'0300XXXX' Part Number Manufacturer 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-28 27-12 11-0 Name Version Number Part Number Manufacturer This is set to X'4' for IBM3206K0424. This is set to X'1D00' for IBM3206K0424. This is set to X'049' for IBM. 9 8 7 6 5 4 3 2 1 0 Description 21.3: SAMPLE/PRELOAD Captures the state of the boundary scan I/O. As the values captured are scanned out, new values can be loaded into the boundary scan latches. This operation will not affect functional operation. Opcode X'0402XXXX' 21.4: EXTEST Drives the values in the boundary scan latches onto their respective I/O. This function can be used in conjunction with SAMPLE/PRELOAD to perform card wire tests. Opcode (Compliant) Opcode (Compatible) X'00000000' X'0600XXXX' 21.5: BYPASS Selects the single bit bypass register for data scans. Opcode (Compliant) Opcode (Compatible) X'FFFFFFFF' X'FFFFXXXX' or X'0000XXXX' JTAG Interface Logic (CJTAG) Page 522 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 21.6: RUNBIST Causes built in self test (BIST) to execute. Opcode X'0770XXXX' 21.7: BIST_RESULTS Returns a 64-bit value when a data scan is performed. Bits 63-32 are the PRPG and bits 31-0 are the MISR from the BIST logic. Opcode X'1F02XXXX' 21.8: WALNUT_MODE This command enables Walnut compatible mode. Opcode X'3000' 21.9: COMPLIANT_MODE This command enables JTAG compliant mode. Opcode X'33010000' 21.10: STOP This command halts the functional clocks of IBM3206K0424 in anticipation of a scan. After the STOP command is scanned in, a data scan that takes the TAP controller through the Capture-DR, Exit1-DR, and Update-DR states should be performed. This will capture the state of the I/O so that they can be held in a known state if a scan command is issued. Opcode X'2002' 21.11: SCAN This command causes TDI to be clocked into the scan chain during a subsequent data scan. The scan out of the scan chain is placed on TDO. This command will not work unless a STOP command is sent down immediately before the SCAN command is issued. Opcode X'0802' pnr25.chapt05.01 August 14, 2000 JTAG Interface Logic (CJTAG) Page 523 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 21.12: SCAN_IN This command causes TDI to be clocked into the scan chain during a subsequent data scan. TDO is forced to '0'. This command will not work unless a STOP command is sent down immediately before the SCAN_IN command is issued. Opcode X'0900' 21.13: SCAN_OUT This command causes the scan out of the scan chain to be placed on TDO. Data is recirculated through the scan chains. TDI is ignored. This command will not work unless a STOP command is sent down immediately before the SCAN_OUT command is issued. Opcode X'0A00' 21.14: Private_RW1 This command is used by RISCWATCH. Opcode X'0500' 21.15: Private_RW2 This command is used by RISCWATCH. Opcode X'0582' 21.16: Private_RW3 This command is used by RISCWATCH. Opcode X'05C0' JTAG Interface Logic (CJTAG) Page 524 of 676 pnr25.chapt05.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Sonet Framer Core (FRAMR Chiplet Address Mapping) FRAMR Chiplet Address Mapping Chiplet Name Reserved ACH_Tx ACH_Rx Reserved OFP_Tx OFP_Rx GPPINT Reserved OT OR GP HT HR Short Name Chiplet Base Address X'000' X'100' X'200' X'300' X'400' X'800' X'C00' X'D00' Chiplet Address Range X'000 - 0FF' X'100 - 1FF' X'200 - 2FF' X'300 - 3FF' X'400 - 7FF' X'800 - BFF' X'C00 - CFF' X'D00 - FFF' Number of Bytes 256 256 256 256 1024 1024 256 768 GPPINT Architecture Overview The General Purpose Processor INTerface (GPPINT) provides direct access to registers located in the GPPINT module; it provides delayed access to registers and counters located in the GppHandler modules of the various chiplets of the SONET core. GPPINT controls the handshaking with the external microprocessor as well as the handshaking with the GppHandlers at the asynchronous chiplet interfaces. Address decoding is done to the chiplet level in GPPINT. In addition, addresses are decoded to the register level for the local GPPINT registers. Reset Register Each chiplet is controlled by one reset bit. At power-on, all reset bits are active and the chiplets are disabled. They can be released by the General Purpose Processor (GPP) only after all global configuration parameters have been set and the clocks to the chiplets have been established. In addition, there are reset bits for the chiplets that do not have their own GppHandler. Interrupt Registers The interrupt register is used as a pointer to the chiplet interrupt registers with pending requests: the clock status error register, and the handshaking error register. An active bit of the interrupt register is reset by removing the cause for the request in the corresponding chiplet or by masking the active IRQ bit(s) in the chiplet; therefore, the interrupt registers (including the pointer) are read only. All interrupt and pointer registers have a corresponding MASK register (R/W). Every unmasked, active interrupt bit causes an active pointer bit. Every unmasked, active pointer bit causes activation of the interrupt signal to the microprocessor. pnr25.chapt06.01 August 14, 2000 GPPINT Architecture Page 525 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Handshaking Error Registers Each bit of the handshaking error registers indicates a locked interface to one of the chiplet GppHandlers. Two additional bits indicate various timeout events. To reset an individual bit of the handshaking error register, the cause for the request must be removed and a one must be written into the bit location of the register (R/W). Reading the register will reset the whole (eight-bit) register if the corresponding "clear-register" option is set in the configuration register. The handshaking error indication register has a corresponding MASK register (R/W). Every unmasked, active handshaking error bit causes activation of the pointer bit in the GPPINT interrupt register. Clock Monitor Status Registers The clock monitor status register bits indicate the loss of a specific chiplet's clock. They are set whenever a difference between the clock test signal and the individual chiplet clock acknowledge signal occurs after one clock monitor test period. To reset an individual bit of the clock monitor status registers, the clock of the corresponding chiplet must be restored and a one must be written into the bit location of the register (R/W). Reading one of the registers will reset the whole (eight-bit) register if the corresponding "clear-register" option is set in the configuration register. The clock monitor status register has a corresponding MASK register (R/W). Every unmasked, active clock monitor status bit causes activation of the pointer bit in the GPPINT register. Local Gppint Configuration Registers There are registers (R/W) for the Clock Monitor Test Period, the Watchdog Timer Period and the "clear-register" option. A read-only register provides the Vital Product Data (VPD). Global Static Configuration Registers These are configuration parameters that are shared by many chiplets or that are needed by chiplets that have no GppHandler. The initial values can be modified by the microprocessor after power-on, but should not be changed later on. All global static configuration registers are R/W. Status Registers These registers provide status information from chiplets that have no GppHandler and are read only. Presently, there is only one status register for the SIM chiplet (PLL lock status). GPPINT Architecture Page 526 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources GPPINT Chiplet Address Mapping Overview: Base Address = x'C00' Register Name RESGP1 ... IRQGP1 ... IRMGP1 ... HShake1 ... HSMask1 ... ClkStat1 ... ClkMask1 ... CMonGP1 WDTGP1 ConfGP1 ... VMD ... GATMCS GCasc GLoopTx GLoopRx GExtRes ... OFPTXGP OFPRXGP1 OFPRXGP2 ... PIMRConf2 ... SIMStat ... Reset register Reserved Chiplet interrupt request register #1 Reserved Chiplet interrupt mask register #1 Reserved Handshaking error register #1 Reserved Handshaking error mask register #1 Reserved Clock status register #1 Reserved Clock status mask register #1 Reserved Clock monitor test period Watchdog Timer Period "Clear-register" option register Reserved Vital Macro Data register Reserved Common ATM/CS static configuration register Common Cascading static configuration register Transmit Loopback static configuration register Receive Loopback static configuration register External clock recovery circuit reset register Reserved OFP_Tx static configuration register OFP_Rx static configuration register #1 OFP_Rx static configuration register #2 Reserved PIM_Rx static configuration register #2 Reserved SIM status register Reserved Description1 Address Offset X'00' X'01 - 0F' X'10' X'11 - 17' X'18' X'19 - 1F' X'20' X'21 - 27' X'28' X'29 - 2F' X'30' X'31 - 37' X'38' X'39 - 47' X'48' X'49' X'4A' X'4B - 4F' X'50' X'51 - 57' X'58' X'59' X'5A' X'5B' X'5C' X'5D - 67' X'68' X'69' X'6A' X'6B - 71' X'73' X'74 - 7E' X'7F' X'80 - FF' R N.A. R/W B'00000000' R/W R/W R/W B'00000000' B'00000000' B'00000000' R/W R/W R/W R/W R/W B'00000000' B'10101010' B'00000000' B'00000000' B'00000000' R B'10000001' R/W R/W R/W B'00000000' B'11111111' B'11111111' R/W B'00000000' R/W B'00000000' R/W B'00000000' R/W B'00000000' R/W B'00000000' R B'00000000' Type R/W Initial Value B'11111111' 1. All registers are of eight-bit width. pnr25.chapt06.01 August 14, 2000 GPPINT Architecture Page 527 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22: GPPINT Register Description 22.1: Chiplet Reset Register (RESGP) The bits of the chiplet reset register control the resetting (enabling/disabling) of complete chiplets. For each bit position: 0 = Reset inactive for this chiplet 1 = Reset active (chiplet is disabled; DEFAULT). Length Type Address Power On Value Reserved 1 0 Description Reset to chiplet ACH_Tx Reset to chiplet ACH_Rx Reset to chiplet OFP_Tx Reset to chiplet OFP_Rx Reset to chiplet PIS_Tx Reset to chiplet PIS_Rx Reserved 8 bits Read/Write C00 X'FF' 7 6 Bit(s) 7 6 5 4 3 2 1-0 5 4 3 Name ResHT ResHR ResOT ResOR TxRPIS RxRPIS Reserved GPPINT Register Description RxRPIS 2 TxRPIS ResOR ResHR ResOT ResHT Page 528 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.2: Chiplet Interrupt and Mask Registers (IRQGP1 (IRMGP1)) The chiplet interrupt request register indicates pending interrupt requests from individual chiplets. An active bit of this register is reset by removing the cause for the request in the corresponding chiplet or by masking the active IRQ bit(s) in the chiplet; therefore, this register is read only. For each bit position: 0 = No chiplet interrupt request pending. 1 = Chiplet has pending interrupt request(s). The chiplet interrupt request mask register bits control the propagation of a chiplet interrupt request to the Sonet Macro Interrupt output pin. The mask registers allow read and write access. For each bit position: 0 = The corresponding interrupt request bit is masked (DEFAULT). 1 = The corresponding interrupt request bit is active (for IRMGP1, the corresponding interrupt request bit activates the Sonet Macro Interrupt). Length Type Address Power On Value Reserved FEIocCS 2 1 8 bits Read C10 X'00' FEIocHS 0 Description IRQ from ACH_Tx IRQ from ACH_Rx IRQ from OFP_Tx IRQ from OFP_Rx Reserved Pending clock status error active Pending handshaking error active 7 6 Bit(s) 7 6 5 4 3-2 1 0 5 IRQOR 4 3 IRQHR IRQOT IRQHT Name IRQHT IRQHR IRQOT IRQOR Reserved FElocCS FElocHS pnr25.chapt06.01 August 14, 2000 GPPINT Register Description Page 529 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22.3: Handshaking Error Indication and Mask Registers (HShake1) The local handshaking error indication register indicates pending handshaking error requests from the GPPINT chiplets. For each bit position: 0 = Normal operation of the corresponding chiplet. 1 = The corresponding chiplet did not deassert its DTACK signal. Exception: The signals TOError and IntError (HShake2(1-0)) have the following meaning: Normal operation GPP deasserts Strobes without waiting for DTACK assertion Watchdog Timeout in REST state Watchdog Timeout in REQ state. An active bit of the handshaking error indication register is reset by removing the cause for the malfunctioning of the chiplet and by writing a one into the corresponding bit position. Reading one register will reset all bits of this register if the "clear-register" option is set in ConfGP1(2). The handshaking error indication mask register bits control the propagation of the GPPINT handshaking error requestof the register HShake1. HSMask1 controls propagation to the signal FElocHS (bit 0 of IRQGP1 register). The mask registers allow read and write access. For each bit position: 0 = The corresponding handshaking error indication bit is masked (DEFAULT). 1 = The corresponding request bit is active (for HSMask1, the corresponding request bit activates signal FElocHS (bit 0 of IRQGP1 register). "Clear-register" option set in ConfGP1(2). Length Type Address Power On Value DTACK from ACH_Rx DTACK from OFP_Rx DTACK from ACH_Tx DTACK from OFP_Tx 8 bits Read/Write C20 X'00' Reserved TOError 2 1 7 6 Bit(s) 7 6 5 4 3-2 1 0 5 4 3 Name DTACK from ACH_Tx stuck at ONE DTACK from ACH_Rx stuck at ONE DTACK from OFP_Tx stuck at ONE DTACK from OFP_Rx stuck at ONE Reserved TOError IntError Reserved IntError 0 Description Time Out Error of the GPP interface (see above) GPP interface error (see above) GPPINT Register Description Page 530 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.4: Clock Monitor Status and Mask Registers (ClkStat1 (ClkMask1)) The clock monitor status register bits indicate the loss of a specific island's clock. They are set whenever a difference between the clock test signal and the individual island's clock acknowledge signal occurs after the clock monitor test period. For each bit position: 0 = Normal operation of the corresponding clock island 1 = The corresponding island clock is lost. An active bit of this register is reset by restoring the clock of the corresponding clock island and by writing a one into the corresponding bit position. Reading one register will reset all bits of this register if the "clear-register" option is set in bit ConfGP1(3). The clock monitor mask register ClkMask1 controls the propagation of active clock monitor status signals. ClkMask1 controls propagation to the signal FElocCS (bit 1 of IRQGP1 register). The mask registers allow read and write access. For each bit position: 0 = The corresponding clock status bit is masked (DEFAULT). 1 = The corresponding clock status bit is active (for ClkMask1, the corresponding bit activates the signal FElocCS (bit 1 of IRQGP1 register). Length Type Address Power On Value Island ACH_Rx Island OFP_Rx Island ACH_Tx Island OFP_Tx 8 bits Read/Write C30 X'00' Reserved 7 6 Bit(s) 7 6 5 4 3-0 5 4 3 2 1 0 Description Island ACH_Tx lost clock Island ACH_Rx lost clock Island OFP_Tx lost clock Island OFP_Rx lost clock Reserved pnr25.chapt06.01 August 14, 2000 GPPINT Register Description Page 531 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22.5: Clock Monitor Test Period Register (CMonGP1) Divider ratio to derive the clock monitor test period from the GPPCLK clock. Clock monitoring is disabled if equal x'00' (DEFAULT). Length Type Address Power On Value CMonGP1 8 bits Read/Write C48 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Number of GPPCLK cycles/test period Name CMonGP1(7-0) 22.6: Watchdog Timer Period Register (WDTGP1) Divider ratio to derive the interface timeout period from the GPPCLK clock. This register is reset to x'FF' whenever a timeout occurs; it has to be reconfigured by a GPP write access. Length Type Address Power On Value WDTGP1 8 bits Read/Write C49 X'FF' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Number of GPPCLK clock cycles per timeout period Name WDTGP1(7-0) GPPINT Register Description Page 532 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.7: GPPINT Local Configuration Registers (ConfGP1) The bits of this local configuration register control the resetting of complete registers upon read access ("clear register" option). For each bit position: 0 = No action upon read access. 1 = The corresponding register is reset upon read access (DEFAULT). Length Type Address Power On Value HShake1 & HShake2 8 bits Read/Write C4A X'FF' ClkStat1 & ClkStat2 Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 1 Reserved 0 Description Reserved Clear-bit for registers ClkStat1 & ClkStat2 Clear-bit for registers HShake1 & HShake2 Clear-bit for register SIMStat Reserved pnr25.chapt06.01 August 14, 2000 SIMStat GPPINT Register Description Page 533 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22.8: Vital Macro Data Register (VPD) This read-only register displays the macro identification. Length Type Address Power On Value Macro Type Version Number 8 bits Read C50 X'01' 7 6 Bit(s) 7-5 4-0 5 4 3 2 1 0 Description Macro type (000) Version number 22.9: Static Configuration Register (GATMCS) Common static configuration data, providing control signals that are distributed to multiple chiplets. Set once by the GPP before the individual chiplets get enabled and not changing during normal operation. Length Type Address Power On Value GATMCSRx 8 bits Read/Write C58 X'00' GATMCSTx 0 Description Reserved ATM cell or CS mode for SDH macro in receive direction: 0 = SDH macro in ATM mode 1 = SDH macro in CS mode Reserved ATM cell or CS mode for SDH macro in transmit direction: 0 = SDH macro in ATM mode, 1 = SDH macro in CS mode Reserved Reserved 7 6 Bit(s) 7-5 4 3-1 0 5 4 3 2 1 Name Reserved GATMCSRx Reserved GATMCSTx GPPINT Register Description Page 534 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.10: GCasc Length Type Address Power On Value GCascRx GCascTx 8 bits Read/Write C59 X'88' 7 6 Bit(s) 5 4 3 2 1 0 Description Defines SDH macros in receive direction: 0001 STS3c 1000 STM1 others reserved Defines SDH macros in transmit direction: 0001 STS3c 1000 STM1 others reserved Name 7-4 GCascRx(7-4) 3-0 GCascTx(7-4) 22.11: GLoopTx Transmit loopback control. For each bit position: 0 = ACH Loopback disabled (DEFAULT). 1 = ACH Loopback enabled. Length Type Address Power On Value TxLpB2 8 bits Read/Write C5A X'00' TxLpB1 0 Description Reserved Loopback #2 control, Tx macro Reserved Loopback #1 control, Tx macro Reserved Reserved 7 6 Bit(s) 7-5 4 3-1 0 5 4 3 2 1 Name Reserved TxLpB2 Reserved TxLpB1 pnr25.chapt06.01 August 14, 2000 GPPINT Register Description Page 535 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22.12: GLoopRx Receive loopback control. For each bit position: 0 = ACH Loopback disabled (DEFAULT). 1 = ACH Loopback enabled. Length Type Address Power On Value 8 bits Read/Write C5B X'00' RxLpB2 2 1 0 Description Reserved Loopback #2 control, Rx macro Name Reserved RxLpB2 Reserved 7 6 Bit(s) 7-1 0 5 4 3 22.13: GExtRes External clock recovery circuit reset signal. Delivered to external circuit (deserializer) via device pins. The active level depends on the external circuit used. Default value at power-on-reset is LOW. Length Type Address Power On Value 8 bits Read/Write C5C X'00' RSTCRec 2 1 0 Description Reserved External recovery reset Name Reserved RSTCRec Reserved 7 6 Bit(s) 7-1 0 5 4 3 GPPINT Register Description Page 536 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.14: OFPTXGP Static configuration data, providing control signals for chiplet OFP_Tx. Set once by the GPP before the individual chiplets are enabled and not changing during normal operation. Length Type Address Power On Value 8 bits Read/Write C68 X'00' CDHC1Tx 0 Description Reserved 0 = AU pointer processing disabled in ATM mode 1 = AU pointer processing enabled in ATM mode Reserved 0 = C1 byte replaced by section trace J1 byte (ITU-T standard) 1 = Old numbering scheme is used. OFPRXGP1 & 2: Static configuration data, providing control signals for chiplets OFP_Rx. Set once by the GPP before the individual chiplets are enabled and not changing during normal operation. Reserved PtrProc 4 Reserved 7 6 Bit(s) 7-5 4 3-1 0 5 3 2 1 Name Reserved PtrProc Reserved SDHC1Tx 22.15: OFPRXGP1 Length Type Address Power On Value 8 bits Read/Write C69 X'00' SDHC1Rx 2 1 0 Description Reserved 0 = The new (ITU-T standard) numbering scheme is used 1 = Old numbering scheme is used Name Reserved SDHC1Rx Reserved 7 6 Bit(s) 7-1 0 5 4 3 pnr25.chapt06.01 August 14, 2000 GPPINT Register Description Page 537 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 22.16: OFPRXGP2 Length Type Address Power On Value A2FRM 3 2 1 0 Description Reserved OFP_Rx RxSoFrm assertion controls: 00 RxSoFrm asserted during 3rd A2 byte 01 RxSoFrm asserted during 1st A2 byte 10 RxSoFrm asserted during 2nd A2 byte 11 RxSoFrm asserted during 3rd A2 byte Name Reserved 8 bits Read/Write C6A X'00' Reserved 7 6 Bit(s) 7-2 1-0 5 4 A2Frm 22.17: PIMRConf2 Static configuration data, providing control signals for chiplets PIM_Tx/PIM_Rx. Set once by the GPP before the individual chiplets are enabled and not changing during normal operation. Length Type Address Power On Value Algo1 3 2 1 0 Description Reserved Selects frame pattern recognition algorithm: 00 All bits checked; maximum four bad frames 01 12 bits checked; only maximum four bad frames 10 All bits checked; maximum five bad frames 11 12 bits checked only; maximum five bad frames Name Reserved 8 bits Read/Write C73 X'00' Reserved 7 6 Bit(s) 7-2 1-0 5 4 Algo1(7-6) GPPINT Register Description Page 538 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 22.18: SIMStat Status register, providing the GPP with information from the SIM chiplet via PIM. Either SIM-internal or external PLL lock status. "Clear-register" option set in ConfGP1(1). Length Type Address Power On Value 8 bits Read C7F N/A Rx_Lock 2 1 0 Description Reserved 0 1 Rx PLL is still in phase aquisition process Rx PLL is enabled and has locked to the incoming data stream incoming data stream Name Reserved Rx_Lock Reserved 7 6 Bit(s) 7-1 0 5 4 3 pnr25.chapt06.01 August 14, 2000 GPPINT Register Description Page 539 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 23: GPPHandler Architecture Overview All GPP handlers for the various chiplets have the following general register structure. GPPHandler Architecture Address Range X'0 - 1' X'2 - 3' X'4 - 2F' X'30' X'31 - 32' X'33 - 37' X'38 - 47' X'48 - 57' Read on the Fly registers Counter enable registers Counters and counter threshold registers Reset register Command registers Event latch registers (was called status) Interrupt registers (addr=int reg, addr-1=int mask reg) Configuration registers Register Function Counter Registers Every counter has an enable bit in the counter enable register (addr 2 or 3), and optionally up to two programmable thresholds. Each counter has an interrupt bit for overflow and up to two interrupt bits for threshold crossing in the counter interrupt registers. For all counters in one handler there is one common 'read-on-the-fly register' that is used to store the higher order bytes to obtain a correct readback value for counters larger than eight bits. Counters are read-only registers; the count enable registers are read/write. Note: COUNTER reading is independent of the counter length, given that a counter has address n as base, reading address n or address n-1 both yield the least significant byte of the counter. Reading address n has no influence on the counter, but reading address n-1 will reset the counter after the read. Reading address n or n-1 will always latch the higher order bytes into the read on the fly register (before the optional automatic reset). Counters can only be read and not written to. For a 16-bit counter, the most significant byte should be read from ROFmid (address 0). For a 24-bit counter, the most significant byte is read from ROFhi (address 1), the next byte from ROFmid (address 0). To completely read a 24-bit counter: first read least significant byte from counter address n or n-1, then read ROFmid and ROFhi (address 0; address 1). Reset Registers Each handler has a two-bit reset register. Bit 0 is the chiplet reset control. This bit is active high after power on reset, causing the chiplet to be disabled. Bit 1 is the chiplet halt signal, which for selected chiplets freezes the state machines for diagnostic purposes. This is a read/write register. Command Registers The optional command register(s) will generate events to the chiplet. When a bit is written high by the microprocessor, it will remain high for one chiplet clock cycle. Therefore, reading back a command register will always read back zeroes. This is a read/write register. GPPHandler Architecture Page 540 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Event Latch Registers The optional event latch register(s) remember one ore more occurances of events that happen in a chiplet. This may be considered as a one-bit saturating counter. Each bit in the register corresponds to an event in the chiplet. Such bits remain high after the event happened until the microprocessor implicitly or explicitly resets the bit. This is configurable: implicit reset is done by writing a high value to the bit that is to be reset. Explicit will reset all bits of one register when the register is read. This is a read/write register. Interrupt Registers When there are counters, user interrupts, or fatal bits in a chiplet, a MAIN INTERRUPT register will be present. Bit 0 always is the fatal interrupt bit, which is set as soon as any of the fatal interrupt events occur. The other bits refer to counters or user interrupt registers to allow easy determination of the interrupt cause. Each Interrupt register has an interrupt MASK register to enable or disable interrupt. After power on Reset, interrupts are disabled. The interrupt registers are the same as the event latch registers, with the addition that when an interrupt register bit is set, and the corresponding mask register bit is set, the interrupt signal to the GPPINT chiplet is activated. The same mechanism to reset the interrupt register bits is used as for the event latch registers. The interrupt MASK registers are only changed by the microprocessor. The interrupt and interrupt mask registers are read/write. Configuration Registers These registers are programmed by the microprocessor with setup information, and are read/write. The first configuration register reserves bit 1 and seven to configure explicit or implicit reset of the event latch registers and interrupt registers respectively (when such registers are present). Register Types F N R I C X S O Read-On-The-Fly register (auto-generated) Counter register Reset register Interrupt register (auto-generated) Configuration register Control or mask register (auto-generated) Status (event latch) register Command register pnr25.chapt06.01 August 14, 2000 GPPHandler Architecture Page 541 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary ATM Cell Handler Architecture : Transmit Direction ACH_Tx GPP Handler Address Mapping Base Address = x'100' Register Name ROFmid ROFhi CntEn1 ACBC IUC ACBE ACBETh11 RESET STAT1 IUCSTAT1 MainIRQ M_MainIRQ CntrIRQ1 M_CntrIRQ1 CELLTENABLE ACBTXTHRPAE HEADERBYTE1 HEADERBYTE2 HEADERBYTE3 HEADERBYTE4 HEADERBYTE5 PAYLOADBYTE HECENCTRL HECOFFSET HECMASKAND HECMASKOR SDBTXTHRPAF Description Read-on-the-fly register Read-on-the-fly register (MSByte) COUNT ENABLE register Cell counter (read from external FIFO), no threshold Idle/unassigned cell counter, no threshold Corrupted cell error counter2 Threshold register for counter ACBE Default RESET register Status register #1 Status register #2 MAIN INTerrupt register INT MASK register (for MainIRQ) COUNTER INTerrupt register INT MASK register (for CntrIRQ1) Chiplet cofiguration register Programmable almost empty threshold IU-cell header byte 11 IU-cell header byte 21 IU-cell header byte 31 IU-cell header byte 41 IU-cell header byte 51 IU-cell payload byte HEC processing control HEC offset pattern register HEC error corruption mask (AND) HEC error corruption mask (OR) Programmable almost full threshold 2 2 Address Offset X'0' X'1' X'2' X'4/5' X'6/7' 2 2 Type Width F8 F8 X3 N 24 N 24 N8 X8 R2 S8 S2 I2 X2 I4 X4 C6 C7 C8 C8 C8 C8 C8 C8 C7 C8 C8 C8 C6 Initial Value '00000000' '00000000' '000' 'x'000000'' 'x'000000'' '00000000' '10000000' '01' X'8/9'2 X'A' X'30' X'33' X'34' X'38' X'39' X'3A' X'3B' X'48' X'49' X'4A' X'4B' X'4C' X'4D' X'4E' X'4F' X'50' X'51' X'52' X'53' X'54' '00' '0000' '001111' '0001110' '00000000' '00000000' '00000000' '00000001' '01010010' '01101010' '0001100' '01010101' '11111111' '00000000' '110000' 1. Defaults according ITU I.432 2. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. ATM Cell Handler Architecture : Transmit Direction Page 542 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24: ACH Tx Register Description Counter Registers 24.1: ROFmid Read-on-the-fly register, middle significant byte. Length Type Address Power On Value ROFmid 8 bits Read 100 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Read-on-the-fly register, middle significant byte Name ROFmid(7-0) 24.2: ROFhi Read-on-the-fly register, most significant byte. Length Type Address Power On Value ROFhi 8 bits Read 101 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Read-on-the-fly register, most significant byte Name ROFhi(7-0) pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 543 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.3: ACBC Number of cells read from external FIFO (24-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value ACBC(16:23) 8 bits Read 104/105 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description External FIFO cell counter, least significant byte Name ACBC(16:23) 24.4: IUC Number of transmitted idle and unassigned cells (24-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value IUC(16:23) 8 bits Read 106/107 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Idle/unassigned cell counter, least significant byte Name IUC(16:23) ACH Tx Register Description Page 544 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.5: ACBE Number of errors (corrupted cell read from external FIFO). Eight-bit counter overflow leads to an interrupt request. Length Type Address Power On Value ACBE 8 bits Read 108/109 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description External FIFO error counter Name ACBE(7-0) pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 545 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.6: ACBETh11 Threshold for number of errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value ACBETh11 8 bits Read/Write 10A X'80' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for error counter Name ACBETh11(7-0) 24.7: CntEn1 Counter On/Off control register for ACH_Tx. For each bit position: 0 = Counter is disabled. 1 = Counter is enabled. Length Type Address Power On Value EN-ACBE 8 bits Read/Write 102 X'00' EN-ACBC 0 Description Reserved Error counter enable Idle/unassigned cell counter enable Cell counter enable Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved EN-ACBE EN-IUC EN-ACBC ACH Tx Register Description EN-ICU 1 Page 546 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.8: Reset Register (RESET) Reset/Halt chiplet control register. This register is automatically preset to the default value by the reset signal ResHT from the GPPINT. For each bit position: 0 = Reset/Halt not active. 1 = Reset/Halt active. Length Type Address Power On Value 8 bits Read/Write 130 X'01' Reset ACH_Tx 0 Description Reserved Halt (freeze) ACH_Tx chiplet Reset (disable) ACH_Tx chiplet Reserved 7 6 Bit(s) 7-2 1 0 5 4 3 2 pnr25.chapt06.01 August 14, 2000 Halt ACH_Tx 1 ACH Tx Register Description Page 547 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Status Registers 24.9: STAT1 Status register #1 of this chiplet. This is an event latch register. Length Type Address Power On Value cellgenstatus 8 bits Read/Write 133 - RxLpB2Fe TxLpB2Fe TxLpB1Fe acbtxPAE 1 sdbtxPAF sdbtxFF 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name RxLpB2Fe TxLpB2Fe TxLpB1Fe cellgenstatus sdbtxPAF sdbtxFF acbtxPAE acbtxEf Rx Loopback #2 configuration mismatch Tx Loopback #2 configuration mismatch Tx Loopback #1 configuration mismatch 0 = Idle/unassigned cell is transmitted 1 = Cell from external FIFO is transmitted acbtxEf 0 Description Programmable almost full flag from SDB_Tx FIFO full flag from SDB_Tx Programmable almost empty flag from External Transmit FIFO FIFO empty flag from external Transmit FIFO ACH Tx Register Description Page 548 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.10: IUCSTAT1 Status register #2 of this chiplet. This is an event latch register. Length Type Address Power On Value 8 bits Read/Write 134 IUCFErr 2 1 0 Description Reserved Unexpected state transition in FSM Name Reserved IUCFErr Reserved 7 6 Bit(s) 7-1 0 5 4 3 Interrupt Request and Mask Registers 24.11: MainIRQ Register to indicate fatal interrupt events and to point to user IRQ registers with active requests. For each bit position; 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value CntrIRQ1 3 2 1 Name Reserved CntrIRQ1 Fatal Reserved Active request in CntrIRQ1 register Fatal event occured 8 bits Read/Write 138 - Reserved 7 6 Bit(s) 7-2 1 0 5 4 Fatal 0 Description pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 549 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.12: M_MainIRQ Register to mask pending interrupt requests. A masked request will not generate an outgoing IRQ to the GPPINT. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates signal IRQHT1 to GPPINT. Length Type Address Power On Value CntrIRQ1 3 2 1 Name Reserved CntrIRQ1 Fatal Reserved Active request in CntrIRQ1 register Fatal event occured 8 bits Read/Write 139 X'00' Reserved 7 6 Bit(s) 7-2 1 0 5 4 Fatal 0 Description ACH Tx Register Description Page 550 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.13: CntrIRQ1 Register to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-ACBE TH-ACBE 8 bits Read/Write 13A OV-ACBC 0 Description Reserved Threshold overstep error counter Overflow error counter Overflow idle/unassigned cell counter Overflow cell counter Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved TH-ACBE OV-ACBE OV-IUC OV-ACBC pnr25.chapt06.01 August 14, 2000 OV-IUC 1 ACH Tx Register Description Page 551 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.14: M_CntrIRQ1 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-ACBE TH-ACBE 8 bits Read/Write 13B X'00' OV-ACBC 0 Description Reserved Threshold overstep error counter Overflow error counter Overflow idle/unassigned cell counter Overflow cell counter Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved TH-ACBE OV-ACBE OV-IUC OV-ACBC ACH Tx Register Description OV-IUC 1 Page 552 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Configuration Registers 24.15: CELLTENABLE Register to control various modes of operation of this chiplet. Length Type Address Power On Value TxLpB1only TxLpB2only ACBenable AutRst_Sta 1 8 bits Read/Write 148 X'0F' IUCenable 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 Name Reserved TxLpB1only TxLpB2only IUCenable ACBenable AutRst_Sta AutRst_Int Reserved 0 = On the fly monitoring (LpB #1) 1 = Loopback #1 only 0 = On the fly monitoring (LpB #2) 1 = Loopback #2 only 0 = Generation of IUC disabled 1 = Generation of IUC enabled 0 = External FIFO read disabled 1 = External FIFO read enabled AutRst_Int 0 Description 0 = No action on read access 1 = Auto-reset status registers upon read access 0 = No action on read access 1 = Auto-reset interrupt request registers upon read access pnr25.chapt06.01 August 14, 2000 Reserved ACH Tx Register Description Page 553 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.16: ACBTXTHRPAE Threshold for Programmable Almost Empty flag of external FIFO in transmit direction. Length Type Address Power On Value Reserved 8 bits Read/Write 149 X'0E' ACBTXTHRPAE 7 6 Bit(s) 7 6-0 5 4 3 2 1 0 Description Reserved Threshold for PAE flag Name Reserved ACBTXTHRPAE(7-1) 24.17: SDBTXTHRPAF Threshold for Programmable Almost Full flag (SDB_Tx). Length Type Address Power On Value Reserved 8 bits Read/Write 154 X'30' SDBTXTHRPAF 7 6 Bit(s) 7-6 5-0 5 4 3 2 1 0 Description Reserved Threshold for PAF flag Name Reserved SDBTXTHRPAF(7-2) ACH Tx Register Description Page 554 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.18: HEADERBYTE1 Idle/Unassigned cell header byte #1. Default pattern according to ITU I.432. Length Type Address Power On Value HEADERBYTE1 8 bits Read/Write 14A X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell header byte #1 Name HEADERBYTE1(7-0) 24.19: HEADERBYTE2 Idle/Unassigned cell header byte #2. Default pattern according to ITU I.432. Length Type Address Power On Value HEADERBYTE2 8 bits Read/Write 14B X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell header byte #2 Name HEADERBYTE2(7-0) pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 555 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.20: HEADERBYTE3 Idle/Unassigned cell header byte #3. Default pattern according to ITU I.432. Length Type Address Power On Value HEADERBYTE3 8 bits Read/Write 14C X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell header byte #3 Name HEADERBYTE3(7-0) 24.21: HEADERBYTE4 Idle/Unassigned cell header byte #4. Default pattern according to ITU I.432. Length Type Address Power On Value HEADERBYTE4 8 bits Read/Write 14D X'01' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell header byte #4 Name HEADERBYTE4(7-0) ACH Tx Register Description Page 556 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.22: HEADERBYTE5 Idle/Unassigned cell header byte #5. Default pattern according to ITU I.432. Length Type Address Power On Value HEADERBYTE5 8 bits Read/Write 14E X'52' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell header byte #5 Name HEADERBYTE5(7-0) 24.23: PAYLOADBYTE Idle/Unassigned cell payload byte. Length Type Address Power On Value PAYLOADBYTE 8 bits Read/Write 14F X'6A' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description IU-cell payload byte Name PAYLOADBYTE(7-0) pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 557 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.24: HECENCTRL HEC processing control configuration register. Length Type Address Power On Value HECCntlUDF2 1 0 Description Reserved 000 001 010 011 1xx 3 2 SCRenable HECenable Each payload byte is the same (default) Increment payload byte for each ATM cell, start with default after reset Increment each payload byte of a cell; start each cell with default byte Increment each PL byte of a cell; cross cell boundaries; start first cell after reset with default byte Each payload byte is the same 8 bits Read/Write 150 X'0C' SCRenable 4 3 7 6 Bit(s) 7 5 Name 6-4 Payload byte control HECenable 2 Reserved Payload byte control 0 = ATM cell payload scrambling disabled 1 = ATM cell payload scrambling enabled 0 = HEC calculation/manipulation disabled 1 = HEC calculation/manipulation enabled Mode of final HEC manipulation by UDF1 byte after HECOffset, HECMaskAND, HECMaskOR operations: 00 No manipulation 01 HEC XOR UDF1 10 HEC AND UDF1 11 HEC OR UDF1 1-0 HECCntlUDF2 ACH Tx Register Description Page 558 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.25: HECOFFSET HEC offset pattern register for the byte pattern used in the ATM cell header HEC calculation as base offset according to ITU I.432. Length Type Address Power On Value HECOFFSET 8 bits Read/Write 151 X'55' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description HEC offset pattern Name HECOFFSET(7-0) 24.26: HECMASKAND HEC mask pattern register for the byte pattern used in the ATM cell header HEC calculation as dedicated (ANDing) HEC error corruption mask. Length Type Address Power On Value HECMASKAND 8 bits Read/Write 152 X'FF' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description HEC error corruption mask (AND) Name HECMASKAND(7-0) pnr25.chapt06.01 August 14, 2000 ACH Tx Register Description Page 559 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.27: HECMASKOR HEC mask pattern register for the byte pattern used in the ATM cell header HEC calculation as dedicated (ORing) HEC error corruption mask. Length Type Address Power On Value HECMASKOR 8 bits Read/Write 153 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description HEC error corruption mask (OR) Name HECMASKOR(7-0) ACH Tx Register Description Page 560 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources ATM Cell Handler Architecture: Receive Direction ACH_Rx GPP Handler Address Mapping Base Address = x'200' Register Name ROFmid ROFhi CntEn1 FHR IHR EHR1 EHR1Th12 EHR1Th11 BHR BHRTh12 BHRTh11 RESET CMD1 STAT1 MainIRQ M_MainIRQ CntrIRQ1 M_CntrIRQ1 CONF5 CONF6 H1CONF H2CONF H3CONF H4CONF H5CONF CONFC Read-on-the-fly register Read-on-the-fly register (MSByte) COUNT ENABLE register Counter, ATM cells written into external FIFO, no threshold Counter, received Idle cells from OFP, no threshold Counter, detected HEC errors with threshold Threshold reg Byte2 (LSByte) for counter EHR1 Threshold reg Byte1 for counter EHR1 Counter, FIFO full discarded cells: (DiscPAF1=1) AND (TxLpB11=0) with threshold.1 Threshold reg Byte2 (LSByte) for counter BHR Threshold register Byte1 for counter BHR Default RESET register Command register (FIFO reset) Status register MAIN INTerrupt register INTerrupt MASK register (for MainIRQ) COUNTER INTerrupt register INTerrupt MASK register (for CntrIRQ1) Chiplet configuration register Chiplet configuration register (Alpha/Delta) Confirmation bytes to identify idle or unassigned cells. Confirmation bytes to identify idle or unassigned cells. Confirmation bytes to identify idle or unassigned cells. Confirmation bytes to identify idle or unassigned cells. Dummy byte to align Payload in external FIFO External FIFO buffer Almost Full threshold Description Address Offset X'0' X'1' X'2' X'4/5'1 X'6/7'1 X'8/9'1 X'A' X'B' X'C/D'1 X'E' X'F' X'30' X'31' X'33' X'38' X'39' X'3A' X'3B' X'48' X'49' X'4A' X'4B' X'4C' X'4D' X'4E' X'4F' Type Width F8 F8 X4 N 24 N 24 N 16 X8 X8 N 16 X8 X8 R2 O2 S6 I2 X2 I6 X6 C8 C8 C8 C8 C8 C8 C8 C7 '000000' '00000011' '01100101' '00000000' '00000000' '00000000' '00000001' '11010000' '1100000' '00' Initial Value '00000000' '00000000' '0000' 'x'000000'' 'x'000000'' 'x'0000'' '00000001' '10000000' 'x'0000'' '00000001' '10000000' '01' '00' 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 561 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary ACH_Rx Register Description Counter Registers 24.28: ROFmid Read-on-the-fly registers, middle significant byte. Length Type Address Power On Value ROFmid 8 bits Read 200 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Read-on-the-fly register, middle significant byte Name ROFmid(7-0) 24.29: ROFhi Read-on-the-fly registers, most significant byte. Length Type Address Power On Value ROFhi 8 bits Read 201 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Read-on-the-fly register, most significant byte Name ROFhi(7-0) ATM Cell Handler Architecture: Receive Direction Page 562 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.30: FHR Number of ATM cells written into external FIFO (24-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value FHR (16:23) 8 bits Read 204/205 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description ATM cell counter, least significant byte Name FHR(16:23) 24.31: IHR Number of idle cells received from OFP_Rx (24-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value IHR (16:23) 8 bits Read 206/207 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Idle/unassigned cell counter, least significant byte Name IHR(16:23) pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 563 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.32: EHR1 Number of detected HEC errors (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value EHR1 (8:15) 8 bits Read 208/209 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description HEC error counter, least significant byte Name EHR1(8:15) 24.33: EHR1Th11 Threshold for number of HEC cells, most significant byte. Length Type Address Power On Value EHR1Th11 8 bits Read/Write 20B X'80' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for HEC error counter, most significant byte Name EHR1Th11(7-0) ATM Cell Handler Architecture: Receive Direction Page 564 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.34: EHT1Th12 Threshold for number of HEC errors (least significant byte). Threshold overstep leads to an interrupt request. Length Type Address Power On Value EHR1Th12 8 bits Read/Write 207 X'01' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for HEC error counter, least significant byte Name EHR1Th12(7-0) 24.35: BHR Number of discarded cells because of FIFO full condition (16 bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value BHR (8:15) 8 bits Read 20C/20D X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Discarded cell counter, least significant byte Name BHR(8:15) pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 565 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.36: BHRTh11 Threshold for number of discarded cells, most significant byte. Length Type Address Power On Value BHRTh11 8 bits Read/Write 20F X'80' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for discarded cell counter, most significant byte Name BHRTh11(7-0) 24.37: BHRTh12 Threshold for number of discarded cells (least significant byte). Threshold overstep leads to an interrupt request. Length Type Address Power On Value BHRTh12 8 bits Read/Write 20E X'01' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for discarded cell counter, least significant byte Name BHRTh12(7-0) ATM Cell Handler Architecture: Receive Direction Page 566 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.38: CntEn1 Counter On/Off control register for ACH_Rx. For each bit position: 0 = Counter is disabled. 1 = Counter is enabled. Length Type Address Power On Value EN-EHR1 8 bits Read/Write 202 X'00' EN-BHR Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 1 Name Reserved EN-BHR EN-EHR1 EN-IHR EN-FHR Reserved Discarded cell counter enable HEC error counter enable Idle cell counter enable ATM cell counter enable EN-FHR 0 Description pnr25.chapt06.01 August 14, 2000 EN-IHR ATM Cell Handler Architecture: Receive Direction Page 567 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.39: Reset Register (RESET) Reset/Halt chiplet control register. This register is automatically preset to the default value by the reset signal ResHR from the GPPINT. For each bit position: 0 = Reset/Halt not active. 1 = Reset/Halt active. Length Type Address Power On Value 8 bits Read/Write 230 X'01' Reset ACH_Rx 0 Description Reserved Halt (freeze) ACH_Rx chiplet Reset (disable) ACH_Rx chiplet Reserved 7 6 Bit(s) 7-2 1 0 5 4 3 2 24.40: Command Register (CMD1) Command register for this chiplet. Single-cycle active if `1' is written into bit position. Length Type Address Power On Value ACBFIFO 3 2 1 Name Reserved ACBFIFO SDBFIFO Reserved Reset External FIFO Reset SDB_Rx FIFO Halt ACH_Rx 1 8 bits Read/Write 231 X'00' SDBFIFO 0 Description Reserved 7 6 Bit(s) 7-2 1 0 5 4 ATM Cell Handler Architecture: Receive Direction Page 568 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.41: Status Register (STAT1) Status register of this chiplet. This is an event latch register. Length Type Address Power On Value WrFlagPAF 1 8 bits Read/Write 233 - RdFlagEF CellDelO 7 6 Bit(s) 7-6 5-3 5 4 3 2 Name Reserved Reserved State of the cell delineation process : 000 Reset state 001 Hunt state 010 Presync state 100 Sync state SDB FIFO: Read FIFO Empty Flag WrFlagFF 0 Description External FIFO: Write FIFO programmable almost full flag External FIFO: Write FIFO Full flag Reserved CellDelO 2 1 0 RdFlagEF WrFlagPAF WrFlagFF pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 569 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Interrupt Request and Mask Registers 24.42: MainIRQ Register to indicate fatal interrupt events and to point to user IRQ registers with active requests. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value CntrIRQ1 3 2 1 Name Reserved CntrIRQ1 Fatal Reserved Active request in CntrIRQ1 register Fatal event occured 8 bits Read/Write 238 - Reserved 7 6 Bit(s) 7-2 1 0 5 4 Fatal 0 Description ATM Cell Handler Architecture: Receive Direction Page 570 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.43: M_MainIRQ Register to mask pending interrupt requests. A masked request will not generate an outgoing IRQ to the GPPINT. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates signal IRQHR1 to GPPINT. Length Type Address Power On Value CntrIRQ1 3 2 1 Name Reserved CntrIRQ1 Fatal Reserved Active request in CntrIRQ1 register Fatal event occured 8 bits Read/Write 239 X'00' Reserved 7 6 Bit(s) 7-2 1 0 5 4 Fatal 0 Description pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 571 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.44: CntrIRQ1 Register to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-EHR1 TH-EHR1 Reserved OV-BHR 8 bits Read/Write 240 - 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 1 Name Reserved TH-BHR OV-BHR TH-EHR1 OV-EHR1 OV-IHR OV-FHR Reserved Threshold overstep discarded cell counter Overflow discarded cell counter Threshold overstep HEC error counter Overflow HEC error counter Overflow idle cell counter Overflow ATM cell counter OV-FHR 0 Description TH-BHR ATM Cell Handler Architecture: Receive Direction OV-IHR Page 572 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.45: M_CntrIRQ1 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-EHR1 TH-EHR1 Reserved OV-BHR 8 bits Read/Write 241 X'00' 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 1 Name Reserved TH-BHR OV-BHR TH-EHR1 OV-EHR1 OV-IHR OV-FHR Reserved Threshold overstep discarded cell counter Overflow discarded cell counter Threshold overstep HEC error counter Overflow HEC error counter Overflow idle cell counter Overflow ATM cell counter OV-FHR 0 Description TH-BHR pnr25.chapt06.01 August 14, 2000 OV-IHR ATM Cell Handler Architecture: Receive Direction Page 573 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Configuration Registers 24.46: CONF5 Register to control various modes of operation of this chiplet. Length Type Address Power On Value NotDetHecEr NWrToFIFO 8 bits Read/Write 248 X'03' Ndescramb AutRst_Sta 1 WrtCHecE 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name DetStrtOC NWrToFIFO NotDetHecEr WrtCHecE Ndescramb WrIdleC AutRst_Sta AutRst_Int 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Do not detect start of cell Detect start of cell AutRst_Int 0 Description DetStrtOC WrIdleC Write into ACB FIFO Do not write into ACB FIFO; all received cells are discarded Detect ATM cell with HEC errors Do not detect ATM cell with HEC errors Do not write ATM cell with HEC errors Write ATM cell with HEC errors Descramble ATM cell payload Do not descramble ATM cell payload Do not write Idle cell into external FIFO Write Idle cell into ACB FIFO No action on read access Auto-reset status register upon read access No action on read access Auto-reset interrupt request registers upon read access ATM Cell Handler Architecture: Receive Direction Page 574 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.47: CONF6 Register to control ATM cell synchronization in this chiplet. Length Type Address Power On Value Alpha Delta 8 bits Read/Write 249 X'65' 7 6 Bit(s) 7-4 3-0 5 4 3 2 1 0 Description Required number of consecutive false HEC detected to return from SYNC to HUNT state Required number of consecutive good HEC detected to jump from PRESYNC to SYNC state Name Alpha(7-4) Delta(7-4) 24.48: CONFC Threshold for Programmable Almost Full flag of the external FIFO. Length Type Address Power On Value Reserved 8 bits Read/Write 24F X'60' CONFC (7-1) 7 6 Bit(s) 7 6-0 5 4 3 2 1 0 Description Reserved Threshold for PAF flag HEADERBYTE1/2/3/4/5: Idle/Unassigned cell header bytes, default pattern according to ITU I.432. Name Reserved CONFC(7-1) pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 575 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.49: H1CONF Header pattern #1 to identify idle/unassigned cells. Length Type Address Power On Value H1CONF 8 bits Read/Write 24A X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Header byte #1 Name H1CONF(7-0) 24.50: H2CONF Header pattern #2 to identify idle/unassigned cells. Length Type Address Power On Value H2CONF 8 bits Read/Write 24B X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Header byte #2 Name H2CONF(7-0) ATM Cell Handler Architecture: Receive Direction Page 576 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.51: H3CONF Header pattern #3 to identify idle/unassigned cells. Length Type Address Power On Value H3CONF 8 bits Read/Write 24C X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Header byte #3 Name H3CONF(7-0) 24.52: H4CONF Header pattern #4 to identify idle/unassigned cells. Length Type Address Power On Value H4CONF 8 bits Read/Write 24D X'01' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Header byte #4 Name H4CONF(7-0) pnr25.chapt06.01 August 14, 2000 ATM Cell Handler Architecture: Receive Direction Page 577 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.53: H5CONF Dummy byte to align the Payload in the ACB_Rx buffer. Length Type Address Power On Value H5CONF 8 bits Read/Write 24E X'D0' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Payload alignment byte Name H5CONF(7-0) ATM Cell Handler Architecture: Receive Direction Page 578 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Overhead Frame Processor Architecture: Transmit Direction OFP_Tx GPP Handler Address Mapping Base Address = x'400' (Page 1 of 3) Register Name CntEn1 PTRINC Description COUNT ENABLE register Pointer increment event No threshold PTRDEC Pointer decrement event No threshold ND_EVCNT JUSCNT New data event counter, no threshold1 Justification error counter1 With no threshold JUSCNTTh11 RESET CMD1 STAT1 STAT2 MainIRQ M_MainIRQ CntrIRQ1 M_CntrIRQ1 IRQ3 M_IRQ3 CONF1 CONF2 CONF3 Threshold register for counter JUSCNT Default RESET register Njus, Pjus, NDF Init, hug, mode(7-5) Njus, Pjus, NDF MAIN INTerrupt register INTerrupt MASK register (for MainIRQ) COUNTER INTerrupt register INTerrupt MASK register (for CntrIRQ1) USER INTerrupt register INTerrupt MASK register (for IRQ3) Configuration register #1 (general A) Configuration register #2 (general B) Configuration register #3 (fscr reload pattern) CONF4 CONF5 CONF6 CONF7 CONF8 CONF9 CONF10 SOH-A11 SOH-A12 SOH-A13 SOH-A21 SOH-A22 Configuration register #4 (errmask) Configuration register #5 (erraddress) Configuration register #6 (fscr control) Configuration register #7 (DCC control) Configuration register #8 (ThrLoW) Configuration register #9 (ThrNoW) Configuration register #10 (ThrHiW) First A1 Second1 A1 Third A1 First A2 Second A2 X'4B' X'4C' X'4D' X'4E' X'4F' X'50' X'51' X'100' X'101' X'102' X'103' X'104' X'C' X'30' X'31' X'33' X'34' X'38' X'39' X'3A' X'3B' X'3C' X'3D' X'48' X'49' X'4A' X'8/9'1 X'A/B'1 counter 1 X'6/7' 1 Address Offset X'2' X'4/5' 1 Type Width X4 N8 N8 N8 N8 N8 N8 N8 X8 R2 O3 S6 S3 I3 X3 I5 X5 I6 X6 C8 C3 C8 N8 C8 C8 C8 C4 C6 C6 C6 8 8 8 8 8 Initial Value '0000' '00000000' counter1 '00000000' '00000000' '00000000' '10000000' '01' '000' '000' '00000' '000000' '00000011' '000' '11111110' '00000000' '00000000' '00000001' '0000' '000011' '010001' '100000' 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation 2. Address range 100-17F located in 128x8 GRA. Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16-byte addresses of 16 byte J1 path trace to map a full 64 byte space pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 579 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary OFP_Tx GPP Handler Address Mapping Base Address = x'400' (Page 2 of 3) Register Name SOH-A23 SOH-J0 Third A2 J0 Reserved for national use and not included in frame scrambling SOH-B1 B1 Media dependant bytes SOH-E1 E1 Media dependant byte Reserved for future standardization SOH-F1 F1 Reserved for national use SOH-D1 D1 Media dependant bytes SOH-D2 D2 Media dependant byte Reserved for future standardization SOH-D3 D3 Reserved for future standardization SOH-H1 SOH-J0 SOH-H2 SOH-1s SOH-H31 SOH-H32 SOH-H23 SOH-B21 SOH-B22 SOH-B23 SOH-K1 H2 x'FF' First H3 Second H3 Third H3 First B2 Second B2 Third B2 K1 Reserved for future standardization SOH-K2 K2 Reserved for future standardization SOH-D4 D4 Reserved for future standardization SOH-D5 D5 Reserved for future standardization SOH-D6 D6 H1 Description Address Offset X'105' X'106' X'107-8' X'109' X'10A-0B' X'10C' X'10D' X'10E' X'10F' X'110-11' X'112' X'113-14' X'115' X'116' X'117' X'118' X'119-1A' X'11B' X'11C-1D' X'11E' X'11F-20' X'121' X'122' X'123' X'124' X'125' X'126' X'127' X'128-29' X'12A ' X'12B-2C' X'12D' X'12E-2F' X'130' X'131-32' X'133' Type Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 b'1001SS11' with S unspecified Initial Value 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation 2. Address range 100-17F located in 128x8 GRA. Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16-byte addresses of 16 byte J1 path trace to map a full 64 byte space Overhead Frame Processor Architecture: Transmit Direction Page 580 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources OFP_Tx GPP Handler Address Mapping Base Address = x'400' (Page 3 of 3) Register Name Description Reserved for future standardization SOH-D7 D7 Reserved for future standardization SOH-D8 D8 Reserved for future standardization SOH-D9 D9 Reserved for future standardization SOH-D10 D10 Reserved for future standardization SOH-D11 D11 Reserved for future standardization SOH-D12 D12 Reserved for future standardization SOH-S1 SOH-Z11 SOH-M1 SOH-M1 S1 Reserved for future standardization M1 E2 Reserved for future standardization Justification stuff bytes POH-J1 POH-B3 POH-C2 POH-G1 POH-F2 POH-H4 POH-F3 POH-K3 X'POH-N1' J1 B3 C2 G1 F2 H4 F3 K3 N1 Reserved POH-J0-16 16 byte J0 section trace Reserved POH-J1-16 POH-J1-64 16-byte J1 path trace3 3 Address Offset X'134-35' X'136' X'137-38' X'139' X'13A-3B' X'13C' X'13D-3E' X'13F' X'140-41' X'142' X'143-44' X'145' X'146-47' X'148' X'149-4C' X'14D' X'14E' X'14F-50' X'151-53' X'154' X'155' X'156' X'157' X'158' X'159' X'15A' X'15B' 15C X'15D-5F' X'160-6F' X'170-7F' X'180-8F' X'190-BF' Type Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial Value 64-byte J1 path trace 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation 2. Address range 100-17F located in 128x8 GRA. Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16-byte addresses of 16 byte J1 path trace to map a full 64 byte space pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 581 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary OFP_Tx Register Description Counter Registers 24.54: PTRINC Number of pointer increment events (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value PTRINC 8 bits Read 404/405 X'00' 7 6 Bit(s) 7-0 5 4 3 2 Name 1 0 Description Pointer increment counter PTRINC(7-0) 24.55: PTRDEC Number of pointer decrement events (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value PTRDEC 8 bits Read 406/407 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Pointer decrement counter Name PTRDEC(7-0) Overhead Frame Processor Architecture: Transmit Direction Page 582 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.56: ND_EVCNT Number of new data events (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value ND_EVCNT 8 bits Read 408/409 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description New data event counter Name ND_EVCNT(7-0) 24.57: JUSCNT Number of justification errors detected (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value JUSCNT 8 bits Read 40A/40B X'00' 7 6 Bit(s) 7-0 5 4 3 2 Name 1 0 Description Justification error counter JUSCNT(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 583 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.58: JUSCNTTh11 Threshold for number of justification errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value JUSCNTTh11 8 bits Read/Write 40C X'80' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for justificication error counter Name JUSCNTTh11(7-0) 24.59: CntEn1 Counter On/Off control register for OFP_Tx. For each bit position: 0 = Counter is disabled. 1 = Counter is enabled. Length Type Address Power On Value EN-ND_EVCNT 8 bits Read/Write 402 X'00' EN-PTRDEC 1 EN-JUSCNT Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved EN-JUSCNT EN-ND_EVCNT EN-PTRDEC EN-PTRINC Reserved Justification error counter enable New data event counter enable Pointer decrement counter enable Pointer increment counter enable EN-PTRINC 0 Description Overhead Frame Processor Architecture: Transmit Direction Page 584 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.60: Reset Register (RESET) Reset/Halt chiplet control register. This register is automatically preset to the default value by the reset signal ResOT coming from GPPINT chiplet. For each bit position: 0 = Reset/Halt not active. 1 = Reset/Halt active. Length Type Address Power On Value 8 bits Read/Write 430 X'01' Reset OFP_Tx 0 Description Reserved Halt (freeze) OFP_Tx chiplet Reset (disable) OFP_Tx chiplet Reserved 7 6 Bit(s) 7-2 1 0 5 4 3 2 pnr25.chapt06.01 August 14, 2000 Halt OFP_Tx 1 Overhead Frame Processor Architecture: Transmit Direction Page 585 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.61: Command Register (CMD1) Command register for the chiplet. Single-cycle active if b'1' is written into bit position. Length Type Address Power On Value NDF Pjus 1 8 bits Read/Write 431 X'00' Njus 0 Description Reserved Force a start-of-new-VC-4 event Perform a positive frequency justification Perform a negative frequency justification Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved NDF Pjus Njus Overhead Frame Processor Architecture: Transmit Direction Page 586 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Status Registers 24.62: STAT1 Status register #1 of the chiplet. This is an event latch register. Length Type Address Power On Value HUG 3 2 1 Name Reserved HUG Init Reserved 0 1 0 1 Higher order unequipped generator inactive Higher order unequipped generator active Default GRA initialization not completed Default GRA initialization completed' 8 bits Read/Write 433 X'00' Reserved 7 6 Bit(s) 7-2 1 0 5 4 Init 0 Description 24.63: STAT2 Status register #2 of the chiplet. This is an event latch register. Length Type Address Power On Value NDF Pjus 1 8 bits Read/Write 434 Njus 0 Description Reserved 0 1 0 1 0 1 No NDF transmitted NDF transmitted No positive frequency justification transmitted Positive frequency justification transmitted No negative frequency justification transmitted Negative frequency justification transmitted Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved NDF Pjus Njus pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 587 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Interrupt and Mask Registers 24.64: MainIRQ Register to indicate fatal interrupt events and to point to user IRQ registers with active requests. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value CntrIRQ1 1 8 bits Read/Write 438 - IRQ3 Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved IRQ3 CntrIRQ1 Fatal Reserved Active request in IRQ3 register Active request in CntrIRQ1 register Fatal event occured Fatal 0 Description Overhead Frame Processor Architecture: Transmit Direction Page 588 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.65: M_MainIRQ Register to mask pending interrupt requests. A masked request will not generate an outgoing IRQ to the GPPINT. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates signal IRQOT to GPPINT. Length Type Address Power On Value CntrIRQ1 1 8 bits Read/Write 439 X'00' IRQ3 Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved IRQ3 CntrIRQ1 Fatal Reserved Active request in IRQ3 register Active request in CntrIRQ1 register Fatal event occured Fatal 0 Description pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 589 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.66: CntrIRQ1 Register to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-ND_EVCNT 8 bits Read/Write 43A - Reserved 7 6 Bit(s) 7-5 4 3 2 0 1 5 4 3 2 1 Name Reserved TH-JUSCNT OV-JUSCNT OV-ND_EVCNT OV-PTRINC OV-PTRDEC Reserved OV-PTRDEC 0 Description Threshold overstep justification error counter Overflow justification error counter Overflow new data event counter Overflow pointer increment counter Overflow pointer decrement counter OV-JUSCNT TH-JUSCNT Overhead Frame Processor Architecture: Transmit Direction OV-PTRINC Page 590 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.67: M_CntrIRQ1 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-ND_EVCNT 8 bits Read/Write 43B X'00' Reserved 7 6 Bit(s) 7-5 4 3 2 0 1 5 4 3 2 1 Name Reserved TH-JUSCNT OV-JUSCNT OV-ND_EVCNT OV-PTRINC OV-PTRDEC Reserved OV-PTRDEC 0 Description Threshold overstep justification error counter Overflow justification error counter Overflow new data event counter Overflow pointer increment counter Overflow pointer decrement counter OV-JUSCNT TH-JUSCNT pnr25.chapt06.01 August 14, 2000 OV-PTRINC Overhead Frame Processor Architecture: Transmit Direction Page 591 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.68: IRQ3 Register to indicate active user interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value Reserved 8 bits Read/Write 43C - 7 6 Bit(s) 7-6 5 4 3 2: 1 0 5 4 3 2 1 Name Reserved DLoss FLow FHigh FrmErr SPCIR TxLPow Reserved Data loss = Data FIFO empty FIFO low threshold overflow FIFO high threshold overflow Framing error detected SPC FSM interrupt request TxLPow 0 Description Low Power indication from Optical/Electrical module FrmErr Overhead Frame Processor Architecture: Transmit Direction SPCIR DLoss FHigh FLow Page 592 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.69: M_IRQ3 Register to mask pending user interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value Reserved 8 bits Read/Write 43D X'00' 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 1 Name Reserved DLoss FLow FHigh FrmErr SPCIR TxLPow Reserved Data loss = Data FIFO empty FIFO low threshold overflow FIFO high threshold overflow Framing error detected SPC FSM interrupt request TxLPow 0 Description Low Power indication from Optical/Electrical module FrmErr pnr25.chapt06.01 August 14, 2000 SPCIR DLoss FHigh FLow Overhead Frame Processor Architecture: Transmit Direction Page 593 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Configuration Registers 24.70: CONF1 Configuration register #1. General OFP_Tx configuration signals A. Length Type Address Power On Value AutRst_Sta 1 8 bits Read/Write 448 X'03' AutRst_Int 0 Description Specifies STM-N row number in which an interrupt request will be issued 0 1 0 1 0 1 Transmit 16-byte J1 path trace Transmit 64-byte J1 path trace Allow pointer modification to be performed on frame-to-frame basis Enforces three frames being interleaved between two pointer modification operations No action on read access Auto-reset status register upon read access 0 No action on read access 1 Auto-reset interrupt request registers upon read access J1Mode 4 3 SPCI(7-4) J1Mode JusFrm AutRst_Int SPCI 7 6 Bit(s) 7-4 3 2 1 0 5 Name AutRst_Sta Overhead Frame Processor Architecture: Transmit Direction JusFrm 2 Page 594 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.71: CONF2 Configuration register #2. General OFP_Tx configuration signals B. Length Type Address Power On Value TxSDown 8 bits Read/Write 449 X'00' 7 6 Bit(s) 7-3 2 5 4 3 2 HUG 1 Reserved Name Reserved TxSDown Reserved MsAIS 0 Description Directly connected to output pin : 0 Optical/Electrical normal operation 1 Transmit shutdown for Optical/Electrical module 0 1 0 1 No unequipped STM-N signal Enforce unequipped STM-N signal No multiplex section AIS Enforce multiplex section AIS 1 0 HUG MsAIS 24.72: CONF3 Configuration register #3. Length Type Address Power On Value 8 bits Read/Write 44A X'FE' Not Used FSCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit(s) 31-0 7-0 FSCR(7-0) Name Not used Reload pattern for frame scrambler Description 9 8 7 6 5 4 3 2 1 0 pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 595 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.73: CONF4 Configuration register #4. Length Type Address Power On Value ErrMask 8 bits Read/Write 44B X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Mask register forcing bit error insertion. XORed with retrieved SOH/POH Name ErrMask(7-0) 24.74: CONF5 Configuration register #5. Length Type Address Power On Value ErrAddr 8 bits Read/Write 44C X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Error mask address register. Indicates address of SOH/POH byte to be corrupted Name ErrAddr(7-0) Overhead Frame Processor Architecture: Transmit Direction Page 596 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.75: CONF6 Configuration register #6. Frame scrambling control register. Length Type Address Power On Value CIDEn 3 2 1 Name CIDnum(7-2) CIDEn Number of all - '1'/'0' bytes CID Insertion Enable: 0 No CID insertion 1 Perform CID insertion Scramble Enable: 0 No scrambling 1 Perform scrambling 8 bits Read/Write 44D X'01' ScrEn 0 Description CIDnum 7 6 Bit(s) 7-2 1 5 4 0 ScrEn pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 597 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.76: CONF7 Configuration register #7. DCC control register. Length Type Address Power On Value Edge Mode 8 bits Read/Write 44E X'00' ClkMode OpMode 1 Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved EdgeMode ClkMode OpMode Enable Reserved 0 1 0 1 0 1 0 1 Active falling edge actIve rising edge Continuous clock Strobed clock DCC1 channel (D1 - D3) CC2 channel (D4 - D12) Disable DCC1 processing Enable DCC1 processing Enable 0 Description 24.77: CONF8 Configuration registers #8. Low water FIFO threshold register. Length Type Address Power On Value Reserved 8 bits Read/Write 44F X'03' ThrLoW (7-2) 7 6 Bit(s) 7-6 5-0 5 4 3 2 1 0 Description Reserved Low Water FIFO threshold; default value is three Name Reserved ThrLoW(7-2) Overhead Frame Processor Architecture: Transmit Direction Page 598 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.78: CONF9 Configuration registers #9. Normal water FIFO threshold register. Length Type Address Power On Value Reserved 8 bits Read/Write 450 X'11' ThrNoW (7-2) 7 6 Bit(s) 7-6 5-0 5 4 3 2 1 0 Description Reserved Normal Water FIFO threshold; default value is 17 Name Reserved ThrNoW(7-2) 24.79: CONF10 Configuration registers #10. High water FIFO threshold register. Length Type Address Power On Value Reserved 8 bits Read/Write 451 X'20' ThrHiW (7-2) 7 6 Bit(s) 7-6 5-0 5 4 3 2 1 0 Description Reserved High Water FIFO threshold; default value is 32 Name Reserved ThrHiW(7-2) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Transmit Direction Page 599 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Overhead Frame Processor Architecture: Receive Direction OFP_Rx GPP Handler Address Mapping Base Address = x'800' (Page 1 of 4) Register Name ROFmid CntEn1 CntEn2 B1BITCNT B1BITCNTTh12 B1BITCNTTh11 B1BLKCNT B1BLKCNTTh12 B1BLKCNTTh11 B2BITCNT B2BITCNTTh12 B2BITCNTTh11 B2BITCNTTh22 B2BITCNTTh21 B2BLKCNT B2BLKCNTTh12 B2BLKCNTTh11 B2BLKCNTTh22 B2BLKCNTTh21 B3BITCNT B3BITCNTTh12 B3BITCNTTh11 B3BLKCNT B3BLKCNTTh12 B3BLKCNTTh11 MSREICNT MSREICNTTh12 MSREICNTTh11 HPREICNT HPREICNTTh12 HPREICNTTh11 PJ_EVCNT NJ_EVCNT Read-on-the-fly register COUNT ENABLE register #1 COUNT ENABLE register #2 BIP-8 B1 bit error counter Threshold register Byte2 (least significant byte) for B1BITCNT Threshold register Byte1 for counter B1BITCNT BIP-8 B1 block error counter1) Threshold register Byte2 (least significant byte) for B1BLKCNT Threshold register Byte1 for counter B1BLKCNT BIP-24 B2 bit error counter, 2 thresholds1 Description Address Offset X'0' X'2' X'3' X'4/5' X'6' X'7' X'8/9'1 X'A' X'B' X'C/D'1 X'E' X'F' X'10' X'11' X'12/13'1 X'14' X'15' X'16' X'17' X'18/19' X'1A' X'1B' X'1C/1D'1 X'1E' X'1F' X'20/21' X'22' X'23' 1 1 1 1 Type Width F8 X8 X3 N 16 X8 X8 N 16 X8 X8 N 16 X8 X8 X8 X8 N 16 X8 X8 X8 X8 N 16 X8 X8 N 16 X8 X8 N 16 X8 X8 Initial Value '00000000' '00000000' '000' 'x'0000'' '00000000' '01111101' 'x'0000'' '00000000' '01111101' 'x'0000'' '00100000' '01001110' '00000000' '01111101' 'x'0000'' '00100000' '01001110' '00000000' '01111101' 'x'0000'' '00000000' '01111101' 'x'0000'' '00000000' '01111101' 'x'0000'' '00000000' '01111101' 'x'0000'' '00000000' '01111101' '00000000' '00000000' Degradation threshold Byte2 (least significant byte) for B2BITCNT Degradation threshold Byte1 for B2BITCNT Failure threshold Byte2 (least significant byte) for B2BITCNT Failure threshold Byte1 for B2BITCNT BIP-24 B2 block error counter, 2 thresholds1 Degration threshold Byte2 (least significant byte) for B2BLKCNT Degradation threshold Byte1 forB2BLKCNT Failure threshold Byte2 (least significant byte) for B2BLKCNT Failure threshold Byte1 for B2BLKCNT BIP-8 B3 bit error counter1 Threshold register Byte2 (least significant byte) for B3BITCNT Threshold register Byte1 for counter B3BITCNT BIP-8 B3 block error counter1 Threshold register Byte2 (least significant byte) for B3BLKCNT Threshold register Byte1 for counter B3BLKCNT Multiplex section remote error indication counter 1 Threshold register Byte2 (least significant byte) for MSREICNT Threshold register Byte1 for counter MSREICNT Higher-order path remote error indication counter X'24/25' X'26' X'27' X'28/29' 1 N 16 X8 X8 Threshold register Byte2 (least significant byte) for HPREICNT Threshold register Byte1 for counter HPREICNT Positive justification counter, no threshold 1 1 1 N8 N8 Negative justification counter, no threshold X'2A/2B'1 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. 2. Address range 100-17F located in 128x8. GRA Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16 byte addresses of 16 byte J1 path trace to map a full 64 byte space. Overhead Frame Processor Architecture: Receive Direction Page 600 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources OFP_Rx GPP Handler Address Mapping Base Address = x'800' (Page 2 of 4) Register Name ND_EVCNT RESET STAT1 STAT2 STAT3 STAT4 MainIRQ M_MainIRQ CntrIRQ1 M_CntrIRQ1 CntrIRQ2 M_CntrIRQ2 CntrIRQ3 M_CntrIRQ3 IRQ6 M_IRQ6 IRQ7 M_IRQ7 IRQ8 M_IRQ8 CONF1 CONF2 CONF3 CONF4 CONF7 CONF8 CONF9 SOH-A11 SOH-A12 SOH-A13 SOH-A21 SOH-A22 SOH-A23 SOH-J0 Description New data event counter, no threshold1 Default RESET register Status register #1 (Mode) Status register #2 (AU pointer) Status register #3 (SOH) Status register #4 (POH) MAIN INTerrupt register INTerrupt MASK register for MainIRQ COUNTER INTerrupt register INTerrupt MASK register for CntrIRQ1 COUNTER INTerrupt register INTerrupt MASK register for CntrIRQ2 COUNTER INTerrupt register INTerrupt MASK register for CntrIRQ3 USER INTerrupt register INTerrupt MASK register for IRQ6 USER INTerrupt register INTerrupt MASK register for IRQ7 USER INTerrupt register INTerrupt MASK register for IRQ8 Configuration register #1 (general) Configuration register #2 (SOH processing) Configuration register #3 (POH processing) Configuration register #4 (APS processing) Configuration register #7 (miscellaneous) Configuration register #8 (FSCR) Configuration register #9 (SL) First A1 Second1 A1 Third A1 First A2 Second A2 Third A2 J0 Reserved for national use and not included in frame scrambling (C1) Address Offset X'2C/2D'1 X'30' X'33' X'34' X'35' X'36' X'38' X'39' X'3A' X'3B' X'3C' X'3D' X'3E' X'3F' X'40' X'41' X'42' X'43' X'44' X'45' X'48' X'49' X'4A' X'4B' X'4E' X'4F' X'50' X'100' X'101' X'102' X'103' X'104' X'105' X'106' X'107-8' Type Width N8 R2 S3 S6 S6 S4 I7 X7 I8 X8 I8 X8 I5 X5 I4 X4 I8 X8 I8 X8 C8 C6 C4 C8 C8 C8 C8 8 8 8 8 8 8 8 8 '00000000' '00111111' '0000' '0000' '00000000' '00100000' '11111110' '00010011' '00000000' '0000' '00000' '00000000' '00000000' '0000000' Initial Value '00000000' '01' 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. 2. Address range 100-17F located in 128x8. GRA Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16 byte addresses of 16 byte J1 path trace to map a full 64 byte space. pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 601 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary OFP_Rx GPP Handler Address Mapping Base Address = x'800' (Page 3 of 4) Register Name SOH-B1 B1 Media dependant bytes SOH-E1 E1 Media dependant byte Reserved for future standardization SOH-F1 F1 Reserved for national use SOH-D1 D1 Media dependant bytes SOH-D2 D2 Media dependant byte Reserved for future standardization SOH-D3 D3 Reserved for future standardization SOH-H1 SOH-J0 SOH-H2 SOH-1s SOH-H31 SOH-H32 SOH-H23 SOH-B21 SOH-B22 SOH-B23 SOH-K1 H1 b'1001SS11' with S unspecified H2 x'FF' First H3 Second H3 Third H3 First B2 Second B2 Third B2 K1 Reserved for future standardization SOH-K2 K2 Reserved for future standardization SOH-D4 D4 Reserved for future standardization SOH-D5 D5 Reserved for future standardization SOH-D6 D6 Reserved for future standardization SOH-D7 D7 Reserved for future standardization SOH-D8 D8 Reserved for future standardization Description Address Offset X'109' X'10A-0B' X'10C' X'10D' X'10E' X'10F' X'110-11' X'112' X'113-14' X'115' X'116' X'117' X'118' X'119-1A' X'11B' X'11C-1D' X'11E' X'11F-20' X'121' X'122' X'123' X'124' X'125' X'126' X'127' X'128-29' X'12A' X'12B-2C' X'12D' X'12E-2F' X'130' X'131-32' X'133' X'134-35' X'136' X'137-38' X'139' X'13A-3B' Type Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial Value 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. 2. Address range 100-17F located in 128x8. GRA Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16 byte addresses of 16 byte J1 path trace to map a full 64 byte space. Overhead Frame Processor Architecture: Receive Direction Page 602 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources OFP_Rx GPP Handler Address Mapping Base Address = x'800' (Page 4 of 4) Register Name SOH-D9 D9 Reserved for future standardization SOH-D10 D10 Reserved for future standardization SOH-D11 D11 Reserved for future standardization SOH-D12 D12 Reserved for future standardization SOH-S1 S1 Reserved for future standardization SOH-M1 SOH-M1 M1 E2 Reserved for future standardization Reserved POH-J1 POH-B3 POH-C2 POH-G1 POH-F2 POH-H4 POH-F3 POH-K3 POH-N1 J1 B3 C2 G1 F2 H4 F3 K3 N1 Reserved POH-J0-16-E POH-J0-16-R POH-J1-16 POH-J1-64 Expected 16-byte J0 section trace Received 16-byte J0 section trace Expected 16-byte J1 path trace3 64-byte J1 path trace3 Description Address Offset X'13C' X'13D-3E' X'13F' X'140-41' X'142' X'143-44' X'145' X'146-47' X'148' X'149-9C' X'14D' X'14E' X'14F-50' X'151-53' X'154' X'155' X'156' X'157' X'158' X'159' X'15A' X'15B' X'15C' X'15D-5F' X'160-6F' X'170-7F' X'180-8F' X'190-BF' Type Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Initial Value 1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the counter after read operation. 2. Address range 100-17F located in 128x8. GRA Address range 180-1BF located in 64x8 GRA. 3. The 64-byte J1 path trace processing uses the 16 byte addresses of 16 byte J1 path trace to map a full 64 byte space. pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 603 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Counter Registers 24.80: ROFmid Read-on-the-fly registers. Length Type Address Power On Value ROFmid 8 bits Read 800 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Read-on-the-fly register, most significant byte Name ROFmid(7-0) 24.81: B1BITCNT Number of BIP-8 B1 bit errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B1BITCNT (8:15) 8 bits Read 804/805 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-8 B1 bit error counter, least significant byte Name B1BITCNT(8:15) Overhead Frame Processor Architecture: Receive Direction Page 604 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.82: B1BITCNTTh11 Threshold for number of BIP-8 B1 bit errors. Length Type Address Power On Value B1BITCNTTh11 8 bits Read/Write 807 X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B1 bit error counter, most significant byte Name B1BITCNTTh11(7-0) 24.83: B1BITCNTTh12 Threshold for number of BIP-8 B1 bit errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B1BITCNTTh12 8 bits Read/Write 806 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B1 bit error error counter, least significant byte Name B1BITCNTTh12(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 605 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.84: B1BLKCNT Number of BIP-8 B1 block errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B1BLKCNT (8:15) 8 bits Read 808/809 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-8 B1 block error counter, least significant byte Name B1BLKCNT(8:15) 24.85: B1BLKCNTTh11 Threshold for number of BIP-8 B1 block errors. Length Type Address Power On Value B1BLKCNTTh11 8 bits Read/Write 80B X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B1 block error counter, most significant byte Name B1BLKCNTTh11(7-0) Overhead Frame Processor Architecture: Receive Direction Page 606 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.86: B1BLKCNTTh12 Threshold for number of BIP-8 B1 block errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B1BLKCNTTh12 8 bits Read/Write 80A X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B1 block error counter, least significant byte Name B1BLKCNTTh12(7-0) 24.87: B2BITCNT Number of BIP-24 B2 bit errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B2BITCNT (8:15) 8 bits Read 80C/80D X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-24 B2 bit error counter, least significant byte Name B2BITCNT(8:15) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 607 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.88: B2BITCNTTh11 Degradation threshold for number of BIP-24 B2 bit errors. Length Type Address Power On Value B2BITCNTTh11 8 bits Read/Write 80F X'4E' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Degradation threshold for BIP-24 B2 bit error counter, most significant byte Name B2BITCNTTh11(7-0) 24.89: B2BITCNTTh12 Degradation threshold for number of BIP-24 B2 bit errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B2BITCNTTh12 8 bits Read/Write 80E X'20' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Degradation threshold for BIP-24 B2 bit error counter, least significant byte Name B2BITCNTTh12(7-0) Overhead Frame Processor Architecture: Receive Direction Page 608 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.90: B2BITCNTTh21 Failure threshold for number of BIP-24 B2 bit errors. Length Type Address Power On Value B2BITCNTTh21 8 bits Read/Write 811 X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Failure threshold for BIP-24 B2 bit error counter, most significant byte Name B2BITCNTTh21(7-0) 24.91: B2BITCNTTh22 Failure threshold for number of BIP-24 B2 bit errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B2BITCNTTh22 8 bits Read/Write 810 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Failure threshold for BIP-24 B2 bit error counter, least significant byte Name B2BITCNTTh22(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 609 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.92: B2BLKCNT Number of BIP-24 B2 block errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B2BLKCNT 8 bits Read 812/813 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-24 B2 block error counter, least significant byte Name B2BLKCNT(8:15) 24.93: B2BLKCNTTh11 Degradation threshold for number of BIP-24 B2 block errors. Length Type Address Power On Value B2BLKCNTTh11 8 bits Read/Write 815 X'4E' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Degradation threshold for BIP-24 B2 block error counter, most significant byte Name B2BLKCNTTh11(7-0) Overhead Frame Processor Architecture: Receive Direction Page 610 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.94: B2BLKCNTTh12 Degradation threshold for number of BIP-24 B2 block errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B2BLKCNTTh12 8 bits Read/Write 814 X'20' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Degradation threshold for BIP-24 B2 block error counter, least significant byte Name B2BLKCNTTh12(7-0) 24.95: B2BLKCNTTh21 Failure threshold for number of BIP-24 B2 block errors. Length Type Address Power On Value B2BLKCNTTh21 8 bits Read/Write 817 X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Failure threshold for BIP-24 B2 block error counter, most significant byte Name B2BLKCNTTh21(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 611 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.96: B2BLKCNTTh22 Failure threshold for number of BIP-24 B2 block errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B2BLKCNTTh22 8 bits Read/Write 816 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Failure threshold for BIP-24 B2 block error counter, least significant byte Name B2BLKCNTTh22(7-0) 24.97: B3BITCNT Number of BIP-8 B3 bit errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B3BITCNT 8 bits Read 818/819 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-8 B3 bit error counter, least significant byte Name B3BITCNT(8:15) Overhead Frame Processor Architecture: Receive Direction Page 612 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.98: B3BITCNTTh11 Threshold for number of BIP-8 B3 bit errors. Length Type Address Power On Value B3BITCNTTh11 8 bits Read/Write 81B X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B3 bit error counter, most significant byte Name B3BITCNTTh11(7-0) 24.99: B3BITCNTTh12 Threshold for number of BIP-8 B3 bit errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B3BITCNTTh12 8 bits Read/Write 81A X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B3 bit error counter, least significant byte Name B3BITCNTTh12(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 613 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.100: B3BLKCNT Number of BIP-8 B3 block errors counted since last counter reset (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value B3BLKCNT 8 bits Read 81C/81D X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description BIP-8 B3 block error counter, least significant byte Name B3BLKCNT(8:15) 24.101: B3BLKCNTTh11 Threshold for number of BIP-8 B3 block errors. Length Type Address Power On Value B3BLKCNTTh11 8 bits Read/Write 81F X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B3 block error counter, most significant byte Name B3BLKCNTTh11(7-0) Overhead Frame Processor Architecture: Receive Direction Page 614 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.102: B3BLKCNTTh12 Threshold for number of BIP-8 B3 block errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value B3BLKCNTTh12 8 bits Read/Write 81E X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for BIP-8 B3 block error counter, least significant byte Name B3BLKCNTTh12(7-0) 24.103: MSREICNT Multiplex Section Remote Error Indication counter (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value MSREICNT (8:15) 8 bits Read 820/821 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Multiplex Section Remote Error Indication counter, least significant byte Name MSREICNT(8:15) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 615 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.104: MSREICNTTh11 Threshold for number of Multiplex Section Remote Errors. Length Type Address Power On Value MSREICNTTh11 8 bits Read/Write 823 X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for Multiplex Indication counter Section Remote Error, most significant byte Name MSREICNTTh11(7-0) 24.105: MSREICNTTh12 Threshold for number of Multiplex Section Remote Errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value MSREICNTTh12 8 bits Read/Write 822 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for Multiplex Indication counter Section Remote Error, least significant byte Name MSREICNTTh12(7-0) Overhead Frame Processor Architecture: Receive Direction Page 616 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.106: HPREICNT Higher-order Path Remote Error Indication counter (16-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value HPREICNT (8:15) 8 bits Read 824/825 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Higher-order Path Remote Error Indication counter, least significant byte Name HPREICNT(8:15) 24.107: HPREICNTTh11 Threshold for number of Higher-order Path Remote Errors. Length Type Address Power On Value HPREICNTTh11 8 bits Read/Write 827 X'7D' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for Higher-order Path Remote Error Indication counter, most significant byte Name HPREICNTTh11(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 617 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.108: HPREICNTTh12 Threshold for number of Higher-order Path Remote Errors. Threshold overstep leads to an interrupt request. Length Type Address Power On Value HPREICNTTh12 8 bits Read/Write 826 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Threshold for Higher-order Path Remote Error Indication counter, least significant byte Name HPREICNTTh12(7-0) 24.109: PJ_EVCNT Positive Justification Event counter (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value PJ_EVCNT 8 bits Read 828/829 X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Positive Justification Event counter Name PJ_EVCNT(7-0) Overhead Frame Processor Architecture: Receive Direction Page 618 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.110: NJ_EVCNT Negative Justification Event counter (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value NJ_EVCNT 8 bits Read 82A/82B X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Negative Justification Event counter Name NJ_EVCNT(7-0) 24.111: ND_EVCNT New Data Event counter (eight-bit counter). Overflow leads to an interrupt request. Length Type Address Power On Value ND_EVCNT 8 bits Read 82C/82D X'00' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description New Data Event counter Name ND_EVCNT(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 619 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.112: CntEn1 Counter On/Off control register #1 for OFP_Rx. For each bit position: 0 = Counter is disabled. 1 = Counter is enabled. Length Type Address Power On Value EN-MSREICNT EN-B3BLKCNT EN-B2BLKCNT EN-B1BLKCNT 1 EN-HPREICNT EN-B3BITCNT EN-B2BITCNT 8 bits Read/Write 802 X'00' EN-B1BITCNT 0 Description Higher-order Path Remote Error Indication counter enable Multiplex Section Remote Error Indication counter enable BIP-8 B3 block error counter enable BIP-8 B3 bit error counter enable BIP-24 B2 block error counter enable BIP-24 B2 bit error counter enable BIP-8 B1 block error counter enable BIP-8 B1 bit error counter enable 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name EN-HPREICNT EN-MSREICNT EN-B3BLKCNT EN-B3BITCNT EN-B2BLKCNT EN-B2BITCNT EN-B1BLKCNT EN-B1BITCNT Overhead Frame Processor Architecture: Receive Direction Page 620 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.113: CntEn2 Counter On/Off control register #2 for OFP_Rx. For each bit position: 0 = Counter is disabled. 1 = Counter is enabled. Length Type Address Power On Value EN-ND_EVCNT EN-NJ_EVCNT 1 8 bits Read/Write 803 X'00' EN-PJ_EVCNT 0 Description Reserved New Data Event counter enable Negative Justification Event counter enable Positive Justification Event counter enable Reserved 7 6 Bit(s) 7-3 2 1 0 5 4 3 2 Name Reserved EN-ND_EVCNT EN-NJ_EVCNT EN-PJ_EVCNT pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 621 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.114: Reset Register (RESET) Reset/Halt chiplet control register. This register is automatically preset to the default value by the reset signal ResOT coming from GPPINT chiplet. For each bit position: 0 = Reset/Halt not active. 1 = Reset/Halt active. Length Type Address Power On Value Halt OFP_Rx 3 2 1 8 bits Read/Write 830 X'01' Reset OFP_rx 0 Description Reserved Halt (freeze) OFP_Rx chiplet Reset (disable) OFP_Rx chiplet Reserved 7 6 Bit(s) 7-2 1 0 5 4 Status Registers 24.115: STAT1 Status register #1 of the chiplet. OFP_Rx Mode status information. This is an event latch register. Length Type Address Power On Value Reserved 8 bits 833 - 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Reserved Overhead Frame Processor Architecture: Receive Direction Page 622 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.116: STAT2 Status register #2 of the chiplet. AU pointer status information of OFP_Rx. This is an event latch register. Length Type Address Power On Value Reserved CONCrx 8 bits Read/Write 834 - NewPtr InvPtr NDF 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 1 Name Reserved CONCrx NewPtr InvPtr NDF Pjus Njus Reserved Concatenation indication received Valid New Pointer received Invalid Pointer received NDF received Positive frequency justification received Negative frequency justification received Njus 0 Description pnr25.chapt06.01 August 14, 2000 Pjus Overhead Frame Processor Architecture: Receive Direction Page 623 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.117: STAT3 Status register #3 of the chiplet. Section Overhead (SOH) status of OFP_Rx. This is an event latch register. Length Type Address Power On Value Reserved 8 bits Read/Write 835 - 7 6 Bit(s) 7-6 5 4 3 2 1 0 5 4 3 2 1 Name Reserved E1chg E2chg F1chg D1chg D4chg M1chg Reserved Orderwire channel E1 content changed Orderwire channel E2 content changed M1chg 0 Description User communication channel F1 content changed D1-D3 communication channel content changed D4-D12 communication channel content changed Number of bit blocks in error changed D1chg Overhead Frame Processor Architecture: Receive Direction D4chg E1chg E2chg F1chg Page 624 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.118: STAT4 Status register #4 of the chiplet. Path Overhead (POH) status of OFP_Rx. This is an event latch register. Length Type Address Power On Value G1chg C2chg F2chg 1 8 bits Read/Write 836 - 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved C2chg G1chg F2chg Z5 Reserved Payload composition indication changed Path status indication changed Z5 0 Description User communication channel F2 content changed Z5 content changed Reserved pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 625 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Interrupt and Mask Registers 24.119: MainIRQ Register to indicate fatal interrupt events and to point to user IRQ registers with active requests. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value Reserved CntrIRQ3 CntrIRQ2 CntrIRQ1 1 8 bits Read/Write 838 - IRQ8 IRQ7 IRQ6 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name Reserved IRQ8 IRQ7 IRQ6 CntrIRQ3 CntrIRQ2 CntrIRQ1 Fatal Reserved Active request in IRQ8 register Active request in IRQ7 register Active request in IRQ6 register Active request in CntrIRQ3 register Active request in CntrIRQ2 register Active request in CntrIRQ1 register Fatal event occured Fatal 0 Description Overhead Frame Processor Architecture: Receive Direction Page 626 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.120: M_MainIRQ Register to mask pending interrupt requests. A masked request will not generate an outgoing IRQ to the GPPINT. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates signal IRQOR to GPPINT. Length Type Address Power On Value Reserved CntrIRQ3 CntrIRQ2 CntrIRQ1 1 8 bits Read/Write 839 X'00' IRQ8 IRQ7 IRQ6 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name Reserved IRQ8 IRQ7 IRQ6 CntrIRQ3 CntrIRQ2 CntrIRQ1 Fatal Reserved Active request in IRQ8 register Active request in IRQ7 register Active request in IRQ6 register Active request in CntrIRQ3 register Active request in CntrIRQ2 register Active request in CntrIRQ1 register Fatal event occured Fatal 0 Description pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 627 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.121: CntrIRQ1 Register #1 to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-B2BLKCNT OV-B1BLKCNT TH-B1BLKCNT OV-B2BITCNT TH-B2BITCNT TH-B1BITCNT 1 8 bits Read/Write 83A OV-B1BITCNT 0 Description Overflow BIP-24 B2 block error counter Failure threshold overstep BIP-24 B2 bit error counter Degradation threshold overstep BIP-24 B2 bit error counter Overflow BIP-24 B2 bit error counter Threshold overstep BIP-8 B1 block error counter Overflow BIP-8 B1 block error counter Threshold overstep BIP-8 B1 bit error counter Overflow BIP-8 B1 bit error counter 7 T2-B2BITCNT 6 5 4 3 2 Bit(s) 7 6 5 4 3 2 1 0 Name OV-B2BLKCNT T2-B2BITCNT TH-B2BITCNT OV-B2BITCNT TH-B1BLKCNT OV-B1BLKCNT TH-B1BITCNT OV-B1BITCNT Overhead Frame Processor Architecture: Receive Direction Page 628 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.122: M_CntrIRQ1 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-B2BLKCNT OV-B1BLKCNT TH-B1BLKCNT OV-B2BITCNT TH-B2BITCNT TH-B1BITCNT 1 8 bits Read/Write 83B X'00' OV-B1BITCNT 0 Description Overflow BIP-24 B2 block error counter Failure threshold overstep BIP-24 B2 bit error counter Degradation threshold overstep BIP-24 B2 bit error counter Overflow BIP-24 B2 bit error counter Threshold overstep BIP-8 B1 block error counter Overflow BIP-8 B1 block error counter Threshold overstep BIP-8 B1 bit error counter Overflow BIP-8 B1 bit error counter 7 T2-B2BITCNT 6 5 4 3 2 Bit(s) 7 6 5 4 3 Name OV-B2BLKCNT T2-B2BITCNT TH-B2BITCNT OV-B2BITCNT TH-B1BLKCNT 2OV-B1BLKCNT 1 0 TH-B1BITCNT OV-B1BITCNT pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 629 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.123: CntrIRQ2 Register #2 to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-MSREICNT OV-B3BLKCNT TH-MSREICNT TH-B3BLKCNT T2-B2BLKCNT 1 OV-B3BITCNT TH-B3BITCNT 8 bits Read/Write 83C TH-B2BLKCNT 0 Description Threshold overstep Multiplex Section Remote Error Indication counter Overflow Multiplex Section Remote Error indication counter Threshold overstep BIP-8 B3 block error counter Overflow BIP-8 B3 block error counter Threshold overstep BIP-8 B3 bit error counter Overflow BIP-8 B3 bit error counter Failure threshold overstep BIP-24 B2 block error counter Degradation threshold overstep BIP-24 B2 block error counter 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name TH-MSREICNT OV-MSREICNT TH-B3BLKCNT OV-B3BLKCNT TH-B3BITCNT OV-B3BITCNT T2-B2BLKCNT TH-B2BLKCNT Overhead Frame Processor Architecture: Receive Direction Page 630 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.124: M_CntrIRQ2 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-MSREICNT OV-B3BLKCNT TH-MSREICNT TH-B3BLKCNT T2-B2BLKCNT 1 OV-B3BITCNT TH-B3BITCNT 8 bits Read/Write 83D X'00' TH-B2BLKCNT 0 Description Threshold overstep Multiplex Section Remote Error Indication counter Overflow Multiplex Section Remote Error indication counter Threshold overstep BIP-8 B3 block error counter Overflow BIP-8 B3 block error counter Threshold overstep BIP-8 B3 bit error counter Overflow BIP-8 B3 bit error counter Failure threshold overstep BIP-24 B2 block error counter Degradation threshold overstep BIP-24 B2 block error counter 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name TH-MSREICNT OV-MSREICNT TH-B3BLKCNT OV-B3BLKCNT TH-B3BITCNT OV-B3BITCNT T2-B2BLKCNT TH-B2BLKCNT pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 631 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.125: CntrIRQ3 Register #3 to indicate active counter interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value OV-ND_EVCNT OV-NJ_EVCNT OV-PJ_EVCNT TH-HPREICNT 1 8 bits Read/Write 83E OV-HPREICNT 0 Description Reserved Overflow New Data event counter Overflow Negative Justification event counter Overflow Positive Justification event counter Threshold overstep Higher-order Path Remote Error indication counter Overflow HPR error indication counter Reserved 7 6 Bit(s) 7-5 4 3 2 1 0 5 4 3 2 Name Reserved OV-ND_EVCNT OV-NJ_EVCNT OV-PJ_EVCNT TH-HPREICNT OV-HPREICNT Overhead Frame Processor Architecture: Receive Direction Page 632 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.126: M_CntrIRQ3 Register to mask pending counter interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value OV-ND_EVCNT OV-NJ_EVCNT OV-PJ_EVCNT TH-HPREICNT 1 8 bits Read/Write 83F X'00' OV-HPREICNT 0 Description Reserved Overflow New Data event counter Overflow Negative Justification event counter Overflow Positive Justification event counter Threshold overstep Higher-order Path Remote Error indication counter Overflow HPR error indication counter Reserved 7 6 Bit(s) 7-5 4 3 2 1 0 5 4 3 2 Name Reserved OV-ND_EVCNT OV-NJ_EVCNT OV-PJ_EVCNT TH-HPREICNT OV-HPREICNT pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 633 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.127: IRQ6 Register to indicate active user interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value SDBfull FrmErr S1chg 1 8 bits Read/Write 840 HPREI 0 Description Reserved SDB_Rx FIFO full Interrupt from ORxAUG FSM Synchronization status changed Higher-order Path Remote Error Indication Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved SDBfull FrmErr S1chg HPREI Overhead Frame Processor Architecture: Receive Direction Page 634 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.128: M_IRQ6 Register to mask pending user interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value SDBfull FrmErr S1chg 1 8 bits Read/Write 841 X'00' HPREI 0 Description Reserved SDB_Rx FIFO full Interrupt from ORxAUG FSM Synchronization status changed Higher-order Path Remote Error Indication Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved SDBfull FrmErr S1chg HPREI pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 635 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.129: IRQ7 Register to indicate active user interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value HPRDI HPAIS UNEQ 1 8 bits Read/Write 842 - OOF 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name OOF LOS LOF LOP HPAIS HPRDI UNEQ SLM Out of frame alarm Loss of signal alarm Loss of frame alarm Loss of pointer alarm Higher-order path AIS Higher-order path RDI Unequipped signal Signal label mismatch alarm SLM 0 Description LOS Overhead Frame Processor Architecture: Receive Direction LOP LOF Page 636 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.130: M_IRQ7 Register to mask pending user interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value HPRDI HPAIS UNEQ 1 8 bits Read/Write 843 X'00' OOF 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 3 2 Name OOF LOS LOF LOP HPAIS HPRDI UNEQ SLM Out of frame alarm Loss of signal alarm Loss of frame alarm Loss of pointer alarm Higher-order path AIS Higher-order path RDI Unequipped signal Signal label mismatch alarm SLM 0 Description LOS pnr25.chapt06.01 August 14, 2000 LOP LOF Overhead Frame Processor Architecture: Receive Direction Page 637 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.131: IRQ8 Register to indicate active user interrupt requests of this chiplet. For each bit position: 0 = No interrupt request pending. 1 = Interrupt request pending. Length Type Address Power On Value MSTIM MSRDI MSAIS HPTIM 1 8 bits Read/Write 844 - Reserved 7 6 Bit(s) 7 6 5-3 2 1 0 5 4 3 2 Name MSAIS MSRDI Reserved MSTIM HPTIM PtrErr Multiplex Section AIS Multiplex Section RDI Reserved Multiplex Section trace identifier mismatch Higher-order path trace identifier mismatch Pointer processing error PtrErr 0 Description Overhead Frame Processor Architecture: Receive Direction Page 638 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.132: M_IRQ8 Register to mask pending user interrupt requests. For each bit position: 0 = The corresponding pending request bit is masked (DEFAULT). 1 = The corresponding pending request bit activates the pointer bit in MainIRQ register. Length Type Address Power On Value MSTIM MSRDI MSAIS HPTIM 1 8 bits Read/Write 845 X'00' Reserved 7 6 Bit(s) 7 6 5-3 2 1 0 5 4 3 2 Name MSAIS MSRDI Reserved MSTIM HPTIM PtrErr Multiplex Section AIS Multiplex Section RDI Reserved Multiplex Section trace identifier mismatch Higher-order path trace identifier mismatch Pointer processing error PtrErr 0 Description pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 639 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Configuration Registers 24.133: CONF1 Configuration register #1. General OFP_Rx configuration signals. Length Type Address Power On Value AutRst_Sta 1 8 bits Read/Write 848 X'3F' AutRst_Int 0 Description 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hunt free running Reset Hunt to PIM Operate according to ITU standard Operate according to Bellcore specification Do not write J1 section trace to GRA Write J1 section trace to GRA Do not write J0 section trace to GRA Write J0 section trace to GRA Do not write C4 payload to FIFO Write C4 payload to FIFO Do not write SOH/POH info to GRA Write received SOH/POH info to GRA No action on read access Auto-reset status register upon read access No action on read access Auto-reset interrupt request registers upon read access ResHunt Bellcore FIFOen 3 7 6 Bit(s) 7 6 5 4 3 2 1 0 5 4 Name ResHunt Bellcore J1GRA J0GRA FIFOen GRAen AutRst_Sta AutRst_Int Overhead Frame Processor Architecture: Receive Direction GRAen 2 J1GRA J0GRA Page 640 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.134: CONF2 Configuration register #2. SOH processing configuration signals. Length Type Address Power On Value M1en 1 K2en S1en 8 bits Read/Write 849 X'00' Oproc 0 Description Reserved 0 1 0 1 0 1 0 1 Disable K2 AIS processing Enable K2 AIS processing Disable S1 synchronization status processing Enable S1 synchronization status processing Disable M1 REI processing Enable M1 REI processing Disable J0 section trace processing Enable J0 section trace processing Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved K2en S1en M1en J0proc pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 641 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.135: CONF3 Configuration register #3. POH byte processing configuration signals. Length Type Address Power On Value J1mode64 1 8 bits Read/Write 84A X'00' Reserved 7 6 Bit(s) 7-4 3 2 1 0 5 4 3 2 Name Reserved C2en G1en J1mode64 J1proc 0 1 0 1 0 1 0 1 Disable C2 signal label processing Enable C2 signal label processing Disable G1 path status processing Enable G1 path status processing 16-byte J1 trace 64-byte J1 trace Disable J1 path trace processing Enable J1 path trace processing J1proc 0 Description Overhead Frame Processor Architecture: Receive Direction G1en C2en Page 642 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.136: CONF4 Configuration register #4. APS processing configuration signals. Length Type Address Power On Value SDFen 8 bits Read/Write 84B X'00' AAen SFen Prior 4 ChNum (7-4) 7 6 Bit(s) 7 6 5 4 3-0 5 3 2 1 0 Description 0 1 0 1 0 1 Disable SF K2 MS_RDI processing Enable SF K2 MS_RDI processing Disable automatic Alarm processing for K2 Enable automatic Alarm processing for K2 Disable automatic SDF K1 processing Enable automatic SDF K1 processing Name SFen AAen SDFen Prior ChNum(7-4) Priority level Channel Number pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 643 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary 24.137: CONF7 Configuration register #7. Miscellaneous OFP_Rx configuration signals. Length Type Address Power On Value OUTnum (7-6) 8 bits Read/Write 84E X'20' 7 6 Bit(s) 7 6 5 4 3-2 1-0 5 4 3 2 1 INnum (7-6) 0 Description 0 1 0 1 0 1 0 1 Active falling edge Active rising edge Continuous clock mode Strobed clock mode DCC 1 channel selected DCC 2 channel selected Disable DCC processing Enable DCC processing EdgeMode ClkMode OpMode DCCen Name EdgeMode ClkMode OpMode DCCen OUTnum(7-6) INnum(7-6) Number of s for in-frame to out-of-frame transition Number of s for out-of-frame to in-frame transition Overhead Frame Processor Architecture: Receive Direction Page 644 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources 24.138: CONF8 Configuration register #8. Pattern register signals. Length Type Address Power On Value FSCRrx 8 bits Read/Write 84F X'FE' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Frame descrambling reload pattern Name FSCRrx(7-0) 24.139: CONF9 Configuration register #9. Pattern register signals. Length Type Address Power On Value Slexpct 8 bits Read/Write 850 X'13' 7 6 Bit(s) 7-0 5 4 3 2 1 0 Description Expected signal label Name Slexpct(7-0) pnr25.chapt06.01 August 14, 2000 Overhead Frame Processor Architecture: Receive Direction Page 645 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Overhead Frame Processor Architecture: Receive Direction Page 646 of 676 pnr25.chapt06.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources Memory Map for Registers and Arrays Address XXXX 0000 - FF XXXX 0100 - FF XXXX 0400 - FF XXXX 0500 - FF XXXX 0600 - 8FF XXXX 0900 - FF XXXX 0A00 - FF XXXX 0B00 - FF XXXX 0D00 - FF XXXX 0E00 - FF XXXX 1000 - 1FF XXXX 1200 - 3FF XXXX 1400 - 5FF XXXX 1600 - 7FF XXXX 1800 - FFF XXXX 2000 - FFF XXXX 3000 - FFF XXXX 4000 - FFF XXXX 5000 - FFF Entity PCINT GPDMA INTST CRSET DMAQS COMET/PAKIT CHKSM LINKC VIMEM ARBIT BCACH CSKED SEGBF REASM RXQUE NPBUS/FRAMR POOLS PCORE PPOCM Elements Accessed Registers Registers & Array Registers Registers Registers & Array Registers Registers Registers Registers Registers Registers & Array Registers & Array Registers & Array Registers & Array Registers & Arrays Registers & External EEPROM Registers & Arrays Registers & Arrays Arrays pnr25.chapt07.01 August 14, 2000 Page 647 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary Signal Pin Listing By Signal Name Signal Name BIST0DI1 CM0CS(0) CM0CS(1) CM0CS(2) CM0CS(3) CM0DQM(0) CM0DQM(1) CM0DQM(2) CM0DQM(3) CMADDR(0) CMADDR(1) CMADDR(10) CMADDR(11) CMADDR(12) CMADDR(13) CMADDR(14) CMADDR(15) CMADDR(16) CMADDR(17) CMADDR(18) CMADDR(19) CMADDR(2) CMADDR(20) CMADDR(3) CMADDR(4) CMADDR(5) CMADDR(6) CMADDR(7) CMADDR(8) CMADDR(9) CMCLK(0) CMCLK(1) CMCLK(2) CMCLK(3) Grid Position Book 0W01 AD17 0Y15 AE16 AE15 0U14 AB15 AE14 AC14 0W02 0U03 0R05 0P03 0R03 0R04 0R02 0N04 0N07 0N08 0M11 0N10 0R08 0N06 0U02 0T05 0U04 0R07 0T03 0R06 0N09 0J01 0K01 0L01 0M01 K C C C C C C C C C C C C C C C C C C C C C C C C C C C C C B B B B Signal Name CMCLK(4) CMCLKE CMDATA(0) CMDATA(1) CMDATA(10) CMDATA(11) CMDATA(12) CMDATA(13) CMDATA(14) CMDATA(15) CMDATA(16) CMDATA(17) CMDATA(18) CMDATA(19) CMDATA(2) CMDATA(20) CMDATA(21) CMDATA(22) CMDATA(23) CMDATA(24) CMDATA(25) CMDATA(26) CMDATA(27) CMDATA(28) CMDATA(29) CMDATA(3) CMDATA(30) CMDATA(31) CMDATA(32) CMDATA(33) CMDATA(34) CMDATA(35) CMDATA(36) CMDATA(37) (Page 1 of 5) Grid Position Book 0N01 AD13 0M09 0N03 0L05 0L06 0J02 0L07 0L10 0K05 0J05 0H01 0J03 0K09 0N02 0J04 0J07 0H03 0K07 0G02 0F01 0J09 0H05 0J06 0G04 0L02 0F03 0J08 0G05 0H07 0D03 0F05 0G06 0G07 B C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Signal Name CMDATA(38) CMDATA(4) CMDATA(5) CMDATA(6) CMDATA(7) CMDATA(8) CMDATA(9) CMSYNCAS(0) CMSYNCAS(1) CMSYNRAS(0) CMSYNRAS(1) CMWE(0) CMWE(1) CTS DSR DTR ENSTATE(0) ENSTATE(1) ENSTATE(10) ENSTATE(11) ENSTATE(12) ENSTATE(13) ENSTATE(14) ENSTATE(15) ENSTATE(16) ENSTATE(17) ENSTATE(18) ENSTATE(19) ENSTATE(2) ENSTATE(20) ENSTATE(21) ENSTATE(22) ENSTATE(23) ENSTATE(24) Grid Position Book 0E04 0L03 0L09 0M03 0L04 0L08 0K03 0U15 AC17 AE18 AA17 0W13 AA13 0P07 0W03 AA05 0C24 0B25 AE24 AD21 AE04 AD05 AE01 AC02 AD01 AB01 AA02 0B01 0E24 0E02 0D01 0C02 0B03 0A02 C C C C C C C C C C C C C T O O A A A A A A A A A A A A A A A A A A Page 648 of 676 pnr25.chapt07.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources (Page 2 of 5) Grid Position Book AE23 AC23 AC25 AA25 AC24 0C25 0C23 0A23 0A21 AD23 AE25 AE22 AA20 0W18 AA19 AB21 0Y19 AC20 0L17 0J23 0H25 0J21 0K21 0L18 0L19 0L20 0K25 0L25 0L21 0L22 AA23 0W25 AC19 0P19 K K K K A K K K K A A A L L L L L L N N I I L N G G G G G L T T T T Signal Name FYRDAT(12) FYRDAT(13) FYRDAT(14) FYRDAT(15) FYRDAT(2) FYRDAT(3) FYRDAT(4) FYRDAT(5) FYRDAT(6) FYRDAT(7) FYRDAT(8) FYRDAT(9) FYREOP FYRMOD FYRPAR(0) FYRPAR(1) FYRRDB FYRSCLKN FYRSCLKP FYRSDATN FYRSDATP FYRSOC FYTADR(0) FYTADR(1) FYTADR(2) FYTADR(3) FYTADR(4) FYTCA FYTDAT(0) FYTDAT(1) FYTDAT(10) FYTDAT(11) FYTDAT(12) FYTDAT(13) Grid Position Book 0M19 0C19 AA14 0W14 0W23 AC21 AA21 0P21 0M21 0E21 0C21 AE19 0L23 0L24 0K23 0M17 0R23 0J25 0J24 0M25 0M23 0R24 0N20 0N21 0T25 0N22 0N24 0N25 0F21 0K17 0H21 0M15 0K19 0H23 T T T T T T T T T T T T L L N N N DA DA DA DA L G G G G G L J J G G G G Signal Pin Listing By Signal Name Signal Name ENSTATE(25) ENSTATE(26) ENSTATE(27) ENSTATE(28) ENSTATE(29) ENSTATE(3) ENSTATE(30) ENSTATE(31) ENSTATE(32) ENSTATE(33) ENSTATE(34) ENSTATE(35) ENSTATE(36) ENSTATE(37) ENSTATE(38) ENSTATE(39) ENSTATE(4) ENSTATE(40) ENSTATE(41) ENSTATE(42) ENSTATE(43) ENSTATE(44) ENSTATE(45) ENSTATE(46) ENSTATE(47) ENSTATE(48) ENSTATE(49) ENSTATE(5) ENSTATE(50) ENSTATE(51) ENSTATE(52) ENSTATE(53) ENSTATE(54) ENSTATE(55) Grid Position Book 0A04 0B05 0A22 0B21 0A25 AA24 0B23 0A24 0N23 0R22 0R19 0U22 0T21 0U24 0R18 0U23 AB25 0W24 0V23 0V25 0T19 0R17 0R16 0U20 0U21 0V21 0W22 AD25 AA01 AC01 AC03 AE03 AE05 AE21 A A A A A A A A J J J J J J J J A J J J J J J J J J J A K K K K K K Signal Name ENSTATE(56) ENSTATE(57) ENSTATE(58) ENSTATE(59) ENSTATE(6) ENSTATE(60) ENSTATE(61) ENSTATE(62) ENSTATE(63) ENSTATE(7) ENSTATE(8) ENSTATE(9) FCDP(0) FCDP(1) FCGBUSY FCPHASE(0) FCPHASE(1) FCSYNC FY0EMP FY0FUL FY0RENB FY0TENB FYDISCRD FYDTCT FYRADR(0) FYRADR(1) FYRADR(2) FYRADR(3) FYRADR(4) FYRCA FYRDAT(0) FYRDAT(1) FYRDAT(10) FYRDAT(11) pnr25.chapt07.01 August 14, 2000 Page 649 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary (Page 3 of 5) Grid Position Book 0C22 0U19 0J16 0J17 0H15 AA03 0C07 0C16 AA12 0Y25 0D21 0D11 0A15 0D17 0B17 AC05 0C13 0F13 0C15 0D15 0A16 0C14 0A14 0E15 0J15 0K15 0G16 0H17 0L14 0G18 0F17 0E17 0E18 0C18 D N D D D E T D V F D D D D D T D D D D D D D D D D D D D D D D D D Signal Name PAD(25) PAD(26) PAD(27) PAD(28) PAD(29) PAD(3) PAD(30) PAD(31) PAD(4) PAD(5) PAD(6) PAD(7) PAD(8) PAD(9) PAD64(32) PAD64(33) PAD64(34) PAD64(35) PAD64(36) PAD64(37) PAD64(38) PAD64(39) PAD64(40) PAD64(41) PAD64(42) PAD64(43) PAD64(44) PAD64(45) PAD64(46) PAD64(47) PAD64(48) PAD64(49) PAD64(50) PAD64(51) Grid Position Book 0A18 0G19 0E20 0F19 0E19 0G13 0C20 0A20 0H13 0J13 0K13 0D13 0B13 0A13 0C04 0D05 0A06 0C06 0E06 0E07 0B07 0F07 0D07 0G09 0F09 0E08 0J10 0G08 0H09 0G10 0C08 0K11 0D09 0J11 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D Signal Pin Listing By Signal Name Signal Name FYTDAT(14) FYTDAT(15) FYTDAT(2) FYTDAT(3) FYTDAT(4) FYTDAT(5) FYTDAT(6) FYTDAT(7) FYTDAT(8) FYTDAT(9) FYTEOP FYTMOD FYTPAR(0) FYTPAR(1) FYTSCLKN FYTSCLKP FYTSDATN FYTSDATP FYTSOC FYTWRB IBDINH1 IBDINH2 IBDRINH JTAG0RST JTAGTCK JTAGTDI JTAGTDO JTAGTMS JTCOMPLY LEAKTST MACK64 MDEVSEL MEXTPMEVENT MFRAME Grid Position Book 0L16 0J22 0G20 0G21 0E22 0J18 0D23 0G22 0J19 0J20 0R21 0P17 0P15 0N19 0R25 0T23 0P25 0P23 0U25 0R20 0E05 0A03 0C01 0G12 0E12 0E14 0A07 0G14 0C03 0A05 0C10 0E16 0G15 0C17 G G J J J J J J G G H H J J DA DA DB DB G N Q R U T T T K T M S D D N D Signal Name MGNT MHALTPPC MINT2 MINTA MIRDY MPCIRST MPEGCLK MPERR MPLLRESET MPMEVENT MREQ MREQ64 MSERR MSTOP MTRDY NSELFT PAD(0) PAD(1) PAD(10) PAD(11) PAD(12) PAD(13) PAD(14) PAD(15) PAD(16) PAD(17) PAD(18) PAD(19) PAD(2) PAD(20) PAD(21) PAD(22) PAD(23) PAD(24) Page 650 of 676 pnr25.chapt07.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources (Page 4 of 5) Grid Position Book 0A17 0B19 0D19 0A12 0C12 0L12 0C11 0G25 0Y23 0G01 0G03 0C05 0E03 0G17 0T17 0G23 0E23 0R14 AC15 AD15 AE13 0Y13 0V13 0U13 AD11 0A19 AA04 0W06 0Y03 0Y01 0U07 0W04 0V05 0U05 D D D D D D D PLL N T T T T D N P P C C C C C C C C E C C C C C C C C Signal Name PMADDR(16) PMADDR(17) PMADDR(18) PMADDR(19) PMADDR(2) PMADDR(20) PMADDR(3) PMADDR(4) PMADDR(5) PMADDR(6) PMADDR(7) PMADDR(8) PMADDR(9) PMCLK(0) PMCLK(1) PMCLK(2) PMCLK(3) PMCLK(4) PMCLKE PMDATA(0) PMDATA(1) PMDATA(10) PMDATA(11) PMDATA(12) PMDATA(13) PMDATA(14) PMDATA(15) PMDATA(16) PMDATA(17) PMDATA(18) PMDATA(19) PMDATA(2) PMDATA(20) PMDATA(21) Grid Position Book 0U06 0P11 0P09 0T07 0Y05 0V03 0T09 0V07 0R10 0W05 0U08 AB03 0R09 0P01 0R01 0T01 0U01 0V01 AC11 AB11 AE10 0W11 AB09 AA10 AD09 0V11 AC09 AD07 AC08 AE08 0W10 AE12 0U11 0T11 C C C C C C C C C C C C C B B B B B C C C C C C C C C C C C C C C C Signal Pin Listing By Signal Name Signal Name PAD64(52) PAD64(53) PAD64(54) PAD64(55) PAD64(56) PAD64(57) PAD64(58) PAD64(59) PAD64(60) PAD64(61) PAD64(62) PAD64(63) PB0EPRM PB0PHY1 PB0PHY2 PBADDR16 PBADDR17 PBALE1 PBALE2 PBDATA(0) PBDATA(1) PBDATA(2) PBDATA(3) PBDATA(4) PBDATA(5) PBDATA(6) PBDATA(7) PBINTRA PBPHYRST PBRDRDY PBRNWRT PBSCLK PBSDATA PCBE(0) Grid Position Book 0C09 0A08 0E09 0E10 0H11 0G11 0A09 0B09 0F11 0A10 0A11 0E11 0V17 AC22 AB19 0W17 0Y17 AA18 0U16 0W21 0U18 0W20 0V19 AB23 0Y21 0W19 AA22 AE20 AD19 0W16 AC18 0T15 AB17 0B15 D D D D D D D D D D D D N N N N N N N J J J J J J J J N N N N N J D Signal Name PCBE(1) PCBE(2) PCBE(3) PCBE64(4) PCBE64(5) PCBE64(6) PCBE64(7) PCICLK PDBLCLK PFFCFG(0) PFFCFG(1) PFFCFG(2) PFFOSC PIDSEL PINTCLK PLLTUNE(0) PLLTUNE(1) PM0CS(0) PM0CS(1) PM0CS(2) PM0CS(3) PM0DQM(0) PM0DQM(1) PM0DQM(2) PM0DQM(3) PM66EN PMADDR(0) PMADDR(1) PMADDR(10) PMADDR(11) PMADDR(12) PMADDR(13) PMADDR(14) PMADDR(15) pnr25.chapt07.01 August 14, 2000 Page 651 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary (Page 5 of 5) Grid Position Book 0V15 AA16 0W15 AE17 0R12 AC13 0F15 0B11 0U17 0W12 0E25 0M07 AE07 0M05 0E01 AC07 0P05 C C C C C C D D J V PLL O T T W T O Signal Name UNUSED_GND00 UNUSED_GND01 UNUSED_GND02 UNUSED_GND03 UNUSED_GND04 UNUSED_GND05 UNUSED_GND06 UNUSED_GND07 UNUSED_GND08 UNUSED_GND09 UNUSED_VDD2500 UNUSED_VDD2501 UNUSED_VDD2502 UNUSED_VDD2503 UNUSED_VDD3300 UNUSED_VDD3301 UNUSED_VDD3302 UNUSED_VDD3303 Grid Position Book 0D25 0F23 0H19 0N16 0N18 AA15 0T13 AD03 0J12 0J14 AC16 AB13 AE02 0N05 0F25 0G24 0N17 0E13 X X X X X X X X X X Y Y Y Y Z Z Z Z Signal Pin Listing By Signal Name Signal Name PMDATA(22) PMDATA(23) PMDATA(24) PMDATA(25) PMDATA(26) PMDATA(27) PMDATA(28) PMDATA(29) PMDATA(3) PMDATA(30) PMDATA(31) PMDATA(32) PMDATA(33) PMDATA(34) PMDATA(35) PMDATA(36) PMDATA(37) PMDATA(38) PMDATA(4) PMDATA(5) PMDATA(6) PMDATA(7) PMDATA(8) PMDATA(9) Grid Position Book 0Y09 AA09 AA08 AB07 0W09 AE06 AC06 0U10 AC12 0U09 0Y07 AA07 0V09 AA06 0W08 AB05 0W07 AC04 AA11 0U12 AE09 0Y11 AE11 AC10 C C C C C C C C C C C C C C C C C C C C C C C C Signal Name PMSYNCAS(0) PMSYNCAS(1) PMSYNRAS(0) PMSYNRAS(1) PMWE(0) PMWE(1) PPAR PPAR64 PPLLOUT PPLLTI PVDDA RTS RXCLK RXD TESTM TXCLK TXD Page 652 of 676 pnr25.chapt07.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources AC Timing Characteristics PHY Timing Description FYTWRB High to FYTDAT(15:0) FYTWRB High to FYTPAR(1:0) FYTWRB High to FYTSOC, FY0TENB, FYTMOD, FYTEOP, FYTADR(4:0) FYTCA to FYTWRB Setup FYTCA to FYTWRB Hold FY0FUL to FYTWRB Setup FY0FUL to FYTWRB Hold FYRRDB High to FYRENB, FYRADR(4:0) FYRDAT(15:0) to FYRRDB Setup FYRDAT(15:0) to FYRRDB Hold FYRPAR(1:0) to FYRRDB Setup FYRPAR(1:0) to FYRRDB Hold FYRSOC to FYRRDB Setup FYRSOC to FYRRDB Hold FY0FUL to FYRRDB Setup FY0FUL to FYRRDB Hold FY0EMP to FYRRDB Setup FY0EMP to FYRRDB Hold FY0DISCRD to FYRRDB Setup FY0DISCRD to FYRRDB Hold FY0DTCT to FYRRDB Setup FY0DTCT to FYRRDB Hold FYRCA to FYRRDB Setup FYRCA to FYRRDB Hold FYRMOD to FYRRDB Setup FYRMOD to FYRRDB Hold FYREOP to FYRRDB Setup FYREOP to FYRRDB Hold Min 2 2 2 3 1 3 1 2 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1 Max 10 10 10 ----10 --------------------Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pnr25.chapt07.01 August 14, 2000 Page 653 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary NPBUS Timing Description PINTCLK High to PBDATA(7:0) PINTCLK High to PBDATAP PINTCLK High to PBRNWRT PINTCLK High to PBRDRDY PINTCLK High to PBADDR(15:0) PBDATA(7:0) to PINTCLK Setup PBDATA(7:0) to PINTCLK Hold PBDATAP to PINTCLK Setup PBDATAP to PINTCLK Hold PBRDRDY to PINTCLK Setup PBRDRDY to PINTCLK Hold PBRNWRT to PINTCLK Setup PBRNWRT to PINTCLK Hold Min 2 2 2 2 2 15 0 15 0 15 0 15 0 Max 6 6 6 6 6 --------Units ns ns ns ns ns ns ns ns ns ns ns ns ns I/O PCI Bus Timing PCICLK High to PAD(31:0) PCICLK High to PPAR PCICLK High to PCBE(3:0) PCICLK High to MFRAME PCICLK High to MTRDY PCICLK High to MIRDY PCICLK High to MSTOP PCICLK High to MDEVSEL PCICLK High to MREQ PCICLK High to MPERR PCICLK High to MSERR PCICLK High to MINITA PCICLK High to MINT2 PCICLK High to MREQ64 PCICLK High to PPAR64 PCICLK High to PAD64(63:32) PCICLK High to MACK64 MFRAME to PCICLK Setup MFRAME to PCICLK Hold PCBE(3:0) to PCICLK Setup (Page 1 of 2) Min 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 0 3 Max 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 ---Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Page 654 of 676 pnr25.chapt07.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources (Page 2 of 2) Min 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 Max ---------------------Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns I/O PCI Bus Timing PCBE(3:0) to PCICLK Hold PAD(31:0) to PCICLK Setup PAD(31:0) to PCICLK Hold PPAR to PCICLK Setup PPAR to PCICLK Hold MPERR to PCICLK Setup MPERR to PCICLK Hold PIDSEL to PCICLK Setup PIDSEL to PCICLK Hold MDEVSEL to PCICLK Setup MDEVSEL to PCICLK Hold MTRDY to PCICLK Setup MTRDY to PCICLK Hold MIRDY to PCICLK Setup MIRDY to PCICLK Hold MSTOP to PCICLK Setup MSTOP to PCICLK Hold MGNT to PCICLK Setup MGNT to PCICLK Hold PCBE64(7:4) to PCICLK Setup PCBE64(7:4) to PCICLK Hold Description pnr25.chapt07.01 August 14, 2000 Page 655 of 676 Page 656 of 676 Synchronous DRAM Timing Diagrams SDRAM Read Cycle (1 of 4) Synchronous DRAM Timing Diagrams IBM Processor for Network Resources IBM3206K0424 CAS Latency=2, Burst Length=1 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 T8 T9 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) CMADDR XXXXXXXX Row XXXXXX Col XXXXXXXXXX CM0CS (3:2) pnr25.chapt07.01 August 14, 2000 Bank Address Preliminary CMDATA ZZZZZZZZZZZZZ Data Out ZZZZZZZZZZ pnr25.chapt07.01 August 14, 2000 Synchronous DRAM Timing Diagrams SDRAM Read Cycle (2 of 4) Preliminary CAS Latency=3, Burst Length=1 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 T8 T9 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) IBM Processor for Network Resources CMADDR XXX Row XXXXXX Col XXXXXXXXXX CM0CS (3:2) Bank Address Page 657 of 676 IBM3206K0424 ZZZZZZZZZZZZZZZZZZZ CMDATA Data Out ZZZZZ Page 658 of 676 Synchronous DRAM Timing Diagrams SDRAM Read Cycle (3 of 4) IBM Processor for Network Resources IBM3206K0424 CAS Latency=2, Burst Length=2 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 T8 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) CMADDR XXXXXXXX Row Col XXXXXXXX CM0CS (3:2) Bank Address pnr25.chapt07.01 August 14, 2000 CMDATA ZZZZZZZZ Data Out ZZZZZZZ Preliminary pnr25.chapt07.01 August 14, 2000 Synchronous DRAM Timing Diagrams SDRAM Read Cycle (4 of 4) Preliminary CAS Latency=3, Burst Length=2 1 CMCLK (4:0) 2 3 4 5 6 7 8 9 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) IBM Processor for Network Resources CMADDR XXX Row Col XXXXXXXX CM0CS (3:2) Bank Address Page 659 of 676 IBM3206K0424 CMDATA ZZZZZZZZZZ Data Out ZZZZZ Page 660 of 676 Synchronous DRAM Timing Diagrams SDRAM Write Cycle (1 of 4) IBM Processor for Network Resources IBM3206K0424 CAS Latency=2, Burst Length=1 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) CMADDR XXXXXXXX Row XXXXXX Col XXXXXXXXXX CM0CS (3:2) pnr25.chapt07.01 August 14, 2000 Bank Address Preliminary CMDATA ZZZZZZZZ XXXXXX Data ZZZZZZZZZZZ pnr25.chapt07.01 August 14, 2000 Synchronous DRAM Timing Diagrams SDRAM Write Cycle (2 of 4) Preliminary CAS Latency=3, Burst Length=1 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) IBM Processor for Network Resources CMADDR XXXXXXXX Row XXXXXX Col XXXXXXXXXX CM0CS (3:2) Bank Address Page 661 of 676 IBM3206K0424 CMDATA ZZZZZZZZ XXXXXX Data ZZZZZZZZZZZ Page 662 of 676 Synchronous DRAM Timing Diagrams SDRAM Write Cycle (3 of 4) IBM Processor for Network Resources IBM3206K0424 CAS Latency=2, Burst Length=2 T1 T2 T3 T4 T5 T6 T7 CMCLK (4:0) CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) CMADDR XXXXXXXX Row Col XXXXXXXXX CM0CS (3:2) pnr25.chapt07.01 August 14, 2000 Bank Address Preliminary CMDATA ZZZZZZZZZZ 00000000 Data ZZZZZZZZZZZ pnr25.chapt07.01 August 14, 2000 Synchronous DRAM Timing Diagrams SDRAM Write Cycle (4 of 4) Preliminary CAS Latency=3, Burst Length=2 T1 CMCLK (4:0) T2 T3 T4 T5 T6 T7 T8 T9 CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) IBM Processor for Network Resources CMADDR XXXXXXXX Row Col XXXXXXX CM0CS (3:2) Bank Address Page 663 of 676 IBM3206K0424 CMDATA ZZZZZZZZ 00000000 Data ZZZZZZZZ Page 664 of 676 Synchronous DRAM Timing Diagrams SDRAM Write of 64-byte Burst with CAS Latency=2 IBM Processor for Network Resources IBM3206K0424 CAS Latency=2, Burst Length=2 T1 T2 T3 T4 T5 T6 T17 T18 T19 T20 T21 T22 T23 T24 T25 CMCLK (4:0) CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) CMADDR XX Row Col0 Col1 Col2 Col 14 Col 15 XXXXXXXX CM0CS (3:2) pnr25.chapt07.01 August 14, 2000 Bank Address Preliminary CMDATA ZZZZZZZZ Data 0 Data 1 Data 2 Data 14 Data 15 ZZZZZZZZ pnr25.chapt07.01 August 14, 2000 CMCLK (4:0) CMSYNRAS (1:0) CM0CS (1:0) CMSYNCAS CMWE (1:0) CM0DQM (3:0) Synchronous DRAM Timing Diagrams CMADDR CM0CS (3:2) SDRAM Write of 64-byte Burst with CAS Latency=3 Preliminary CAS Latency=3, Burst Length=2 T1 T2 T3 T4 T5 T6 T18 T19 T20 T21 T22 T23 IBM Processor for Network Resources XX Row Col0 Col1 Col 14 Col 15 XXXXXXXX Bank Address Page 665 of 676 IBM3206K0424 CMDATA ZZZZZZZZ Data 0 Data 1 Data 14 Data 15 ZZZZZZZZ IBM3206K0424 IBM Processor for Network Resources Preliminary SRAM Timing Diagrams SRAM Read Cycle 6 3 4 2 XXXXXXXX Addr XXXXXXXX 1 CM0CS (Bit 1) CMWE (Bit 0) CMDATA (35:0) CMCLK (4:0) ZZZZZZZZ Data 5 ZZZ SRAM Timing Diagrams CMSYNRAS (1:0) Page 666 of 676 CMSYNCAS (1:0) CMADDR pnr25.chapt07.01 August 14, 2000 IBM3206K0424 Preliminary IBM Processor for Network Resources SRAM Write Cycle T5 T6 ZZZZZZZZ T4 T3 Addr Data T2 XXXXXXXX ZZZZZZZZ T1 CM0CS (Bit 1) CMWE (Bit 0) CMDATA (35:0) CMCLK (4:0) CMSYNRAS (1:0) F SRAM Timing Diagrams CMSYNCAS (1:0) pnr25.chapt07.01 August 14, 2000 CMADDR 0 F Page 667 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary SRAM Read Cycle with Byte Enables 5 4 XXXXXXXX Data ZZZZZZZZ 6 3 Addr 2 XXXXXXXX ZZZZZZZZ 1 CM0CS (Bit 1) CMWE (Bit 0) CMDATA (35:0) CMCLK (4:0) CMSYNRAS (1:0) F CMSYNCAS (1:0) pnr25.chapt07.01 August 14, 2000 SRAM Timing Diagrams Page 668 of 676 CMADDR 0 F IBM3206K0424 Preliminary IBM Processor for Network Resources SRAM Write Cycle with Byte Enables T5 T6 ZZZZZZZZ T4 T3 Addr Data T2 XXXXXXXX ZZZZZZZZ T1 CM0CS (Bit 1) CMWE (Bit 0) CMDATA (35:0) CMCLK (4:0) CMSYNRAS (1:0) F SRAM Timing Diagrams CMSYNCAS (1:0) CMADDR pnr25.chapt07.01 August 14, 2000 0 F Page 669 of 676 IBM3206K0424 IBM Processor for Network Resources Preliminary EPROM Timing Diagrams Parallel EPROM Read T19 T17 T13 T15 `1' Hi-Z T11 Data T9 T1 T3 T5 T7 PBRNWRT PDRDRDY PINTCLK PBDATA (7:0) Hi-Z Enstate (47:32) (Address 15:0) PBEPRM PBADDR16 PBADDR17 PBPHY1 Address EPROM Timing Diagrams Page 670 of 676 pnr25.chapt07.01 August 14, 2000 :H or L IBM3206K0424 Preliminary IBM Processor for Network Resources Parallel EPROM Write T17 T11 T13 T15 Data T1 T3 T5 T7 T9 Enstate (47:32) (Address 15:0) PBADDR16 PBADDR17 PBRNWRT PDRDRDY PBEPRM PBDATA (7:0) PINTCLK PBPHY1 Address pnr25.chapt07.01 August 14, 2000 EPROM Timing Diagrams Page 671 of 676 :H or L Page 672 of 676 EPROM Timing Diagrams PBSCLK PBSDATA PBSDATA (continued) PBSDATA (continued) PBSDATA (continued) Serial EPROM READ Follows I2C Bus Protocol PBSDATA is single sequence split over several lines) Serial EPROM Read IBM Processor for Network Resources IBM3206K0424 pnr25.chapt07.01 August 14, 2000 Preliminary pnr25.chapt07.01 August 14, 2000 PBSCLK PBSDATA PBSDATA (continued) PBSDATA (continued) Serial EPROM WRITE Follows I2C Bus Protocol PBSDATA is single sequence split over several lines) EPROM Timing Diagrams Serial EPROM Write Preliminary IBM Processor for Network Resources Page 673 of 676 IBM3206K0424 IBM3206K0424 IBM Processor for Network Resources Preliminary PHY Timing Diagrams PHY Read T24 T22 T23 T9 T21 Hi-Z Data T1 T3 T5 Enstate (47:32) (Address 15:0) PBADDR16 PBADDR17 PBRNWRT PDRDRDY PBEPRM PBDATA (7:0) PINTCLK PBPHY1 Address T7 PHY Timing Diagrams Page 674 of 676 pnr25.chapt07.01 August 14, 2000 :H or L IBM3206K0424 Preliminary IBM Processor for Network Resources PHY Write T24 T22 T23 T9 data T21 T1 T3 T5 T7 Enstate (47:32) (Address 15:0) PBRNWRT PBRDRDY PBDATA PBEPRM PBADDR16 PBADDR17 (7:0) PINTCLK PBPHY1 Address pnr25.chapt07.01 August 14, 2000 PHY Timing Diagrams Page 675 of 676 :H or L IBM3206K0424 IBM Processor for Network Resources Preliminary Revision Log Rev. 8/31/99 Initial release (00). First revision (01). 8/14/00 In the Input/Output Definitions section, corrected the definition of RXCLK in Clock, Configuration, and LSSD Pin Descriptions on page 58. Changed page numbering of Contents from roman to numeric. Description PHY Timing Diagrams Page 676 of 676 pnr25.chapt07.01 August 14, 2000 |
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